73 lines
1.9 KiB
Systemverilog
73 lines
1.9 KiB
Systemverilog
`timescale 1ns / 1ps
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module sampler
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#(
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parameter DATA_WIDTH = 12,
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parameter PACK_FACTOR = 3,
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parameter PROCESS_MODE = 1
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)
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(
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input clk_in,
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input rst,
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input [DATA_WIDTH-1:0] data_in,
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input out_of_range,
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output logic [DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata,
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output logic m_axis_tvalid
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);
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logic [DATA_WIDTH-1:0] data_converted;
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logic out_of_range_reg;
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always @( posedge clk_in) begin
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if (rst) begin
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data_converted <= '0;
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end else begin
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out_of_range_reg <= out_of_range;
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if (PROCESS_MODE) begin
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if (data_in == 12'b100000000000) begin
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data_converted <= data_in;
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end else begin
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data_converted <= data_in[DATA_WIDTH-1] ? {1'b1, (~data_in[DATA_WIDTH-2:0] + 1'b1)} : data_in;
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end
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end else begin
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data_converted <= data_in;
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end
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end
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end
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logic [DATA_WIDTH*PACK_FACTOR-1:0] buffer;
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logic buffer_ready;
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logic [$clog2(PACK_FACTOR):0] cnt;
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always @(posedge clk_in) begin
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if (rst) begin
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buffer <= '0;
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cnt <= -1; //
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buffer_ready <= 0;
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end
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else begin
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buffer_ready <= 0;
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if (!out_of_range_reg) begin
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buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
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if (cnt == PACK_FACTOR-1) begin
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cnt <= 0;
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buffer_ready <= 1;
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buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
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end
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else begin
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cnt <= cnt + 1;
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end
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end
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end
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end
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assign m_axis_tdata = buffer;
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assign m_axis_tvalid = buffer_ready;
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endmodule
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