`timescale 1ns / 1ps



module sampler
#(
    parameter DATA_WIDTH = 12,
    parameter PACK_FACTOR = 3,
    parameter PROCESS_MODE = 1
    )
(
    input clk_in,
    input rst,
    input [DATA_WIDTH-1:0] data_in,
    input out_of_range,

    output logic [DATA_WIDTH*PACK_FACTOR-1:0]  m_axis_tdata,
    output logic                              m_axis_tvalid
    );
    logic [DATA_WIDTH-1:0] data_converted;
    logic out_of_range_reg;

    always @( posedge clk_in) begin
        if (rst) begin
            data_converted <= '0;
        end else begin
            out_of_range_reg <= out_of_range;
            if (PROCESS_MODE) begin
                if (data_in == 12'b100000000000) begin
                    data_converted <= data_in;
                end else begin
                    data_converted <= data_in[DATA_WIDTH-1]  ? {1'b1, (~data_in[DATA_WIDTH-2:0] + 1'b1)} : data_in; 
                    
                end
            end else begin
                data_converted <= data_in; 
            end
        end
    end 
    
         
    logic [DATA_WIDTH*PACK_FACTOR-1:0] buffer;
    logic buffer_ready;

    logic [$clog2(PACK_FACTOR):0] cnt;
    
    always @(posedge clk_in) begin
        if (rst) begin
            buffer <= '0;
            cnt <= -1; //
            buffer_ready <= 0;
        end
        else begin
            buffer_ready <= 0;
            if (!out_of_range_reg) begin
                buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
                if (cnt == PACK_FACTOR-1) begin
                    cnt <= 0;
                    buffer_ready <= 1;
                    buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
                end
                else begin
                    cnt <= cnt + 1;
                end
            end
        end
    end
    
    assign m_axis_tdata = buffer;
    assign m_axis_tvalid = buffer_ready;
    
endmodule