52 lines
1.3 KiB
Verilog
52 lines
1.3 KiB
Verilog
module arp_cache
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(
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input clk ,
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input rst_n ,
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input arp_found,
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input [31:0] arp_rec_source_ip_addr,
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input [47:0] arp_rec_source_mac_addr,
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input [31:0] destination_ip_addr,
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output reg [47:0] destination_mac_addr,
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output reg mac_not_exist
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) ;
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reg [79:0] arp_cache ;
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//init arp cache
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always @(posedge clk or negedge rst_n)
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begin
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if (~rst_n)
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arp_cache <= 80'h00_00_00_00_ff_ff_ff_ff_ff_ff ;
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else if (arp_found)
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arp_cache <= {arp_rec_source_ip_addr, arp_rec_source_mac_addr} ;
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else
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arp_cache <= arp_cache ;
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end
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always @(posedge clk or negedge rst_n)
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begin
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if (~rst_n)
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destination_mac_addr <= 48'hff_ff_ff_ff_ff_ff ;
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else if (destination_ip_addr == arp_cache[79:48])
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destination_mac_addr <= arp_cache[47:0] ;
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else
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destination_mac_addr <= 48'hff_ff_ff_ff_ff_ff ;
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end
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always @(posedge clk or negedge rst_n)
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begin
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if (~rst_n)
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mac_not_exist <= 1'b0 ;
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else if (destination_ip_addr != arp_cache[79:48])
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mac_not_exist <= 1'b1 ;
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else if (destination_ip_addr == arp_cache[79:48] && arp_cache[47:0] == 48'hff_ff_ff_ff_ff_ff)
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mac_not_exist <= 1'b1 ;
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else
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mac_not_exist <= 1'b0 ;
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end
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endmodule
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