104 lines
2.7 KiB
Systemverilog
104 lines
2.7 KiB
Systemverilog
`timescale 1ns / 1ps
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module generator
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#(
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parameter DATA_WIDTH = 14
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)
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(
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input clk_in,
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input rst,
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input start,
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input [31:0] pulse_width,
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input [31:0] pulse_period,
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input [DATA_WIDTH-1:0] pulse_height,
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input [15:0] pulse_num,
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output pulse,
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output[DATA_WIDTH-1:0] pulse_height_out
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);
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logic [DATA_WIDTH-1:0] pulse_height_reg, pulse_height_out_reg;
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logic pulse_reg;
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logic [31:0] pulse_width_reg, pulse_period_reg;
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logic [15:0] pulse_num_reg;
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logic enable;
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logic [15:0] cnt_pulse_num;
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logic [31:0] cnt_period;
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logic start_d;
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always @(posedge clk_in) begin
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start_d <= start;
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end
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wire start_pulse = start & ~start_d;
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always @(posedge clk_in) begin
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if (rst) begin
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pulse_reg <= '0;
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pulse_height_reg <= 0;
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pulse_height_out_reg <= '0;
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pulse_width_reg <= '0;
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pulse_period_reg <= '0;
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pulse_num_reg <= '0;
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enable <= 0;
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cnt_pulse_num <= '0;
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cnt_period <= '0;
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end else begin
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if (start) begin
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enable <= 1'b1;
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// pulse_width_reg <= pulse_width;
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// pulse_period_reg <= pulse_period;
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// pulse_num_reg <= pulse_num;
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// pulse_height_reg <= pulse_height;
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cnt_pulse_num <= '0;
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cnt_period <= '0;
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end
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if (enable) begin
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pulse_reg <= 1;
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pulse_width_reg <= pulse_width;
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pulse_period_reg <= pulse_period;
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pulse_num_reg <= pulse_num;
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pulse_height_reg <= pulse_height;
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if (pulse_reg) begin
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if (cnt_period < pulse_width_reg) begin
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pulse_height_out_reg <= pulse_height_reg;
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end else begin
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pulse_height_out_reg <= '0;
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end
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if (cnt_period == pulse_period_reg - 1) begin
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cnt_period <= 0;
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if (cnt_pulse_num == pulse_num_reg - 1) begin
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enable <= 0;
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pulse_reg <= 0;
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end else begin
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cnt_pulse_num <= cnt_pulse_num + 1;
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end
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end else begin
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cnt_period <= cnt_period + 1;
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end
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end
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end
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end
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end
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OBUF OBUF_pulse_clk (
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.I(clk_in),
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.O(pulse)
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);
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assign pulse_height_out = pulse_height_out_reg;
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endmodule
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