`timescale 1ns / 1ps


module generator
#(
    parameter DATA_WIDTH = 14
    )
(
    input clk_in,
    input rst,
    input start,
    input [31:0]           pulse_width,
    input [31:0]           pulse_period,
    input [DATA_WIDTH-1:0] pulse_height,
    input [15:0]           pulse_num,
    
    output pulse,
    output[DATA_WIDTH-1:0] pulse_height_out
    
    );
    
    logic [DATA_WIDTH-1:0] pulse_height_reg, pulse_height_out_reg;
    logic pulse_reg;
    
    logic [31:0] pulse_width_reg, pulse_period_reg;
    logic [15:0] pulse_num_reg;
    
    logic enable;
    logic [15:0] cnt_pulse_num;
    logic [31:0] cnt_period;
    
    logic start_d;

    always @(posedge clk_in) begin
        start_d <= start;
    end

    wire start_pulse = start & ~start_d;

    
    always @(posedge clk_in) begin
        if (rst) begin
            pulse_reg <= '0;
            pulse_height_reg <= 0;
            pulse_height_out_reg <= '0;
            
            pulse_width_reg <= '0;
            pulse_period_reg <= '0;
            pulse_num_reg <= '0;
            enable <= 0;
            cnt_pulse_num <= '0;
            cnt_period <= '0;
        end else begin
            if (start) begin
                enable <= 1'b1;
//                pulse_width_reg <= pulse_width;
//                pulse_period_reg <= pulse_period;
//                pulse_num_reg <= pulse_num;
//                pulse_height_reg <= pulse_height;
                
                cnt_pulse_num <= '0;
                cnt_period <= '0;
            end
            if (enable) begin
                pulse_reg <= 1;
                
                pulse_width_reg <= pulse_width;
                pulse_period_reg <= pulse_period;
                pulse_num_reg <= pulse_num;
                pulse_height_reg <= pulse_height;
                
                if (pulse_reg) begin
                
                if (cnt_period < pulse_width_reg) begin
                    pulse_height_out_reg <= pulse_height_reg;
                end else begin
                    pulse_height_out_reg <= '0;
                end
                if (cnt_period == pulse_period_reg - 1) begin
                    cnt_period <= 0;
                    if (cnt_pulse_num == pulse_num_reg - 1) begin
                        enable <= 0;
                        pulse_reg <= 0;
                    end else begin
                        cnt_pulse_num <= cnt_pulse_num + 1;
                    end
                end else begin
                    cnt_period <= cnt_period + 1;
                end
                
                end
            end
        end
    end

     OBUF OBUF_pulse_clk (
        .I(clk_in),
        .O(pulse)
    );
    
    assign pulse_height_out = pulse_height_out_reg;
    
endmodule