221 lines
8.0 KiB
Systemverilog
221 lines
8.0 KiB
Systemverilog
import dma_reg_pkg::*;
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module controller_wrapper_axil #(
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parameter int unsigned ADDR_W = 16,
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parameter int unsigned DATA_W = 32,
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parameter int unsigned USER_W = 1,
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parameter int unsigned DAC_DATA_WIDTH = 12
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)
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(
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input logic ctrl_clk,
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input logic dac_clk_in,
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input logic adc_clk_in,
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input logic rst_n,
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axi4l_if.slave s_axil,
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// adc_clk_in domain
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input logic finish,
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output logic [31:0] adc_window_size,
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// dac_clk_in domain outputs
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output logic [31:0] dac_pulse_width,
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output logic [31:0] dac_pulse_period,
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output logic [DAC_DATA_WIDTH-1:0] dac_pulse_height,
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output logic [15:0] dac_pulse_num,
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// adc_clk_in domain outputs
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output logic [31:0] adc_pulse_period,
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output logic [15:0] adc_pulse_num,
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// pulse outputs
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output logic dac_start,
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output logic adc_start,
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output logic dac_rst,
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output logic adc_rst,
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// AXIS DMA
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axis_if.slave s_axis_status_read,
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axis_if.slave s_axis_status_write,
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axis_if.master m_axis_desc_read,
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axis_if.master m_axis_desc_write
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);
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logic start, rst_soft, send_desc_read, send_desc_write, take_status_read, take_status_write, cfg_bus_valid, busy;
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logic [31:0] pulse_width, pulse_period, pulse_num, pulse_height_raw, pulse_period_ADC, window_size;
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logic [7:0] error_code;
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logic [31:0] desc_read_addr, desc_read_len, desc_read_config, status_read;
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logic [31:0] desc_write_addr, desc_write_len_and_tag, status_write_len, status_write_config;
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logic desc_read_dma_busy, desc_write_dma_busy, status_read_dma_busy, status_write_dma_busy;
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logic desc_read_dma_hs, desc_write_dma_hs, status_read_dma_hs, status_write_dma_hs;
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axi4l_reg_map_controller #(
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.ADDR_W(ADDR_W),
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.DATA_W(DATA_W),
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.USER_W(USER_W)
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) axi4l_reg_map_controller_inst (
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.clk(ctrl_clk),
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.rst_n(rst_n),
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.s_axil(s_axil),
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// CONTROLLER ADC/ DAC
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.start_o(start),
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.cfg_bus_valid_o(cfg_bus_valid),
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.pulse_width_o(pulse_width),
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.pulse_period_o(pulse_period),
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.pulse_num_o(pulse_num),
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.pulse_height_raw_o(pulse_height_raw),
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.pulse_period_ADC_o(pulse_period_ADC),
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.window_size_o(window_size),
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.rst_soft_o(rst_soft),
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.busy_i(busy),
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.error_code_i(error_code),
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// CONTROLLER DMA
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.send_desc_read_o(send_desc_read),
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.send_desc_write_o(send_desc_write),
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.take_status_read_o(take_status_read),
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.take_status_write_o(take_status_write),
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.desc_read_addr_o(desc_read_addr),
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.desc_read_len_o(desc_read_len),
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.desc_read_config_o(desc_read_config),
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.status_read_i(status_read),
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.desc_write_addr_o(desc_write_addr),
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.desc_write_len_and_tag_o(desc_write_len_and_tag),
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.status_write_len_i(status_write_len),
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.status_write_config_i(status_write_config),
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.desc_read_dma_busy_i(desc_read_dma_busy),
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.desc_write_dma_busy_i(desc_write_dma_busy),
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.status_read_dma_busy_i(status_read_dma_busy),
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.status_write_dma_busy_i(status_write_dma_busy),
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.desc_read_dma_hs_i(desc_read_dma_hs),
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.desc_write_dma_hs_i(desc_write_dma_hs),
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.status_read_dma_hs_i(status_read_dma_hs),
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.status_write_dma_hs_i(status_write_dma_hs)
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);
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// CONTROLLER DAC ADC
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// -------------------------------------------------------------------------
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// Field layout inside cfg_bus:
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// [31:0] pulse_width
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// [63:32] pulse_period
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// [79:64] pulse_num
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// [95:80] pulse_height_raw[15:0]
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// [127:96] pulse_period_ADC
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// [159:128] window_size
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// -------------------------------------------------------------------------
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(* MARK_DEBUG="true" *) logic [159:0] cfg_bus;
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assign cfg_bus = {window_size, pulse_period_ADC, pulse_height_raw[15:0], pulse_num[15:0], pulse_period, pulse_width};
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control #(
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.DAC_DATA_WIDTH(DAC_DATA_WIDTH)
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)
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controller (
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.ctrl_clk(ctrl_clk),
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.dac_clk_in(dac_clk_in),
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.adc_clk_in(adc_clk_in),
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.rst_n(rst_n),
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.rst_soft(rst_soft),
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.finish(finish),
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.cfg_bus_input(cfg_bus),
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.cfg_bus_valid(cfg_bus_valid),
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.start(start),
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.busy(busy),
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.dac_pulse_width(dac_pulse_width),
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.dac_pulse_period(dac_pulse_period),
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.dac_pulse_height(dac_pulse_height),
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.dac_pulse_num(dac_pulse_num),
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.adc_pulse_period(adc_pulse_period),
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.adc_pulse_num(adc_pulse_num),
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.adc_window_size(adc_window_size),
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.dac_start(dac_start),
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.adc_start(adc_start),
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.dac_rst(dac_rst),
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.adc_rst(adc_rst)
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);
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// CONTROLLER DMA
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dma_read_desc_t desc_read_cmd, desc_read_cmd_out;
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assign desc_read_cmd.addr = desc_read_addr;
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assign desc_read_cmd.len = desc_read_len;
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assign desc_read_cmd.tag = desc_read_config[TAG_WIDTH-1:0];
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assign desc_read_cmd.id = desc_read_config[TAG_WIDTH +: AXIS_ID_WIDTH];
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assign desc_read_cmd.dest = desc_read_config[TAG_WIDTH+AXIS_ID_WIDTH +: AXIS_DEST_WIDTH];
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assign desc_read_cmd.user = desc_read_config[TAG_WIDTH+AXIS_ID_WIDTH+AXIS_DEST_WIDTH +: AXIS_USER_WIDTH];
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dma_write_desc_t desc_write_cmd, desc_write_cmd_out;
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assign desc_write_cmd.addr = desc_write_addr;
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assign desc_write_cmd.len = desc_write_len_and_tag[LEN_WIDTH-1:0];
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assign desc_write_cmd.tag = desc_write_len_and_tag[LEN_WIDTH +: TAG_WIDTH];
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dma_read_status_t status_read_cmd, status_read_cmd_in;
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assign status_read = { status_read_cmd.error, status_read_cmd.tag};
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dma_write_status_t status_write_cmd, status_write_cmd_in;
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assign status_write_len = status_write_cmd.len;
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assign status_write_config = { status_write_cmd.error, status_write_cmd.user,
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status_write_cmd.dest, status_write_cmd.id, status_write_cmd.tag};
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dma_controller dma_controller_inst
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(
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.dma_clk(ctrl_clk),
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.rst_n(rst_n),
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.send_desc_read(send_desc_read),
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.send_desc_write(send_desc_write),
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.take_status_read(take_status_read),
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.take_status_write(take_status_write),
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.desc_read_cmd(desc_read_cmd),
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.desc_write_cmd(desc_write_cmd),
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.status_read_cmd(status_read_cmd),
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.status_write_cmd(status_write_cmd),
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.desc_read_cmd_out(desc_read_cmd_out),
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.desc_write_cmd_out(desc_write_cmd_out),
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.status_read_cmd_in(status_read_cmd_in),
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.status_write_cmd_in(status_write_cmd_in),
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.ready_desc_read(m_axis_desc_read.resp.ready),
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.ready_desc_write(m_axis_desc_write.resp.ready),
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.ready_status_read(s_axis_status_read.resp.ready),
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.ready_status_write(s_axis_status_write.resp.ready),
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.valid_desc_read(m_axis_desc_read.req.t.valid),
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.valid_desc_write(m_axis_desc_write.req.t.valid),
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.valid_status_read(s_axis_status_read.req.t.valid),
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.valid_status_write(s_axis_status_write.req.t.valid),
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.desc_read_dma_busy(desc_read_dma_busy),
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.desc_write_dma_busy(desc_write_dma_busy),
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.status_read_dma_busy(status_read_dma_busy),
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.status_write_dma_busy(status_write_dma_busy),
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.desc_read_dma_hs(desc_read_dma_hs),
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.desc_write_dma_hs(desc_write_dma_hs),
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.status_read_dma_hs(status_read_dma_hs),
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.status_write_dma_hs(status_write_dma_hs)
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);
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axis_defaults_master defaults_rd (.axis(m_axis_desc_read));
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axis_defaults_master defaults_wr (.axis(m_axis_desc_write));
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assign m_axis_desc_read.req.t.data = desc_read_cmd_out;
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assign m_axis_desc_write.req.t.data = desc_write_cmd_out;
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assign status_read_cmd_in = s_axis_status_read.req.t.data;
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assign status_write_cmd_in = s_axis_status_write.req.t.data;
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endmodule |