import dma_reg_pkg::*; module controller_wrapper_axil #( parameter int unsigned ADDR_W = 16, parameter int unsigned DATA_W = 32, parameter int unsigned USER_W = 1, parameter int unsigned DAC_DATA_WIDTH = 12 ) ( input logic ctrl_clk, input logic dac_clk_in, input logic adc_clk_in, input logic rst_n, axi4l_if.slave s_axil, // adc_clk_in domain input logic finish, output logic [31:0] adc_window_size, // dac_clk_in domain outputs output logic [31:0] dac_pulse_width, output logic [31:0] dac_pulse_period, output logic [DAC_DATA_WIDTH-1:0] dac_pulse_height, output logic [15:0] dac_pulse_num, // adc_clk_in domain outputs output logic [31:0] adc_pulse_period, output logic [15:0] adc_pulse_num, // pulse outputs output logic dac_start, output logic adc_start, output logic dac_rst, output logic adc_rst, // AXIS DMA axis_if.slave s_axis_status_read, axis_if.slave s_axis_status_write, axis_if.master m_axis_desc_read, axis_if.master m_axis_desc_write ); logic start, rst_soft, send_desc_read, send_desc_write, take_status_read, take_status_write, cfg_bus_valid, busy; logic [31:0] pulse_width, pulse_period, pulse_num, pulse_height_raw, pulse_period_ADC, window_size; logic [7:0] error_code; logic [31:0] desc_read_addr, desc_read_len, desc_read_config, status_read; logic [31:0] desc_write_addr, desc_write_len_and_tag, status_write_len, status_write_config; logic desc_read_dma_busy, desc_write_dma_busy, status_read_dma_busy, status_write_dma_busy; logic desc_read_dma_hs, desc_write_dma_hs, status_read_dma_hs, status_write_dma_hs; axi4l_reg_map_controller #( .ADDR_W(ADDR_W), .DATA_W(DATA_W), .USER_W(USER_W) ) axi4l_reg_map_controller_inst ( .clk(ctrl_clk), .rst_n(rst_n), .s_axil(s_axil), // CONTROLLER ADC/ DAC .start_o(start), .cfg_bus_valid_o(cfg_bus_valid), .pulse_width_o(pulse_width), .pulse_period_o(pulse_period), .pulse_num_o(pulse_num), .pulse_height_raw_o(pulse_height_raw), .pulse_period_ADC_o(pulse_period_ADC), .window_size_o(window_size), .rst_soft_o(rst_soft), .busy_i(busy), .error_code_i(error_code), // CONTROLLER DMA .send_desc_read_o(send_desc_read), .send_desc_write_o(send_desc_write), .take_status_read_o(take_status_read), .take_status_write_o(take_status_write), .desc_read_addr_o(desc_read_addr), .desc_read_len_o(desc_read_len), .desc_read_config_o(desc_read_config), .status_read_i(status_read), .desc_write_addr_o(desc_write_addr), .desc_write_len_and_tag_o(desc_write_len_and_tag), .status_write_len_i(status_write_len), .status_write_config_i(status_write_config), .desc_read_dma_busy_i(desc_read_dma_busy), .desc_write_dma_busy_i(desc_write_dma_busy), .status_read_dma_busy_i(status_read_dma_busy), .status_write_dma_busy_i(status_write_dma_busy), .desc_read_dma_hs_i(desc_read_dma_hs), .desc_write_dma_hs_i(desc_write_dma_hs), .status_read_dma_hs_i(status_read_dma_hs), .status_write_dma_hs_i(status_write_dma_hs) ); // CONTROLLER DAC ADC // ------------------------------------------------------------------------- // Field layout inside cfg_bus: // [31:0] pulse_width // [63:32] pulse_period // [79:64] pulse_num // [95:80] pulse_height_raw[15:0] // [127:96] pulse_period_ADC // [159:128] window_size // ------------------------------------------------------------------------- (* MARK_DEBUG="true" *) logic [159:0] cfg_bus; assign cfg_bus = {window_size, pulse_period_ADC, pulse_height_raw[15:0], pulse_num[15:0], pulse_period, pulse_width}; control #( .DAC_DATA_WIDTH(DAC_DATA_WIDTH) ) controller ( .ctrl_clk(ctrl_clk), .dac_clk_in(dac_clk_in), .adc_clk_in(adc_clk_in), .rst_n(rst_n), .rst_soft(rst_soft), .finish(finish), .cfg_bus_input(cfg_bus), .cfg_bus_valid(cfg_bus_valid), .start(start), .busy(busy), .dac_pulse_width(dac_pulse_width), .dac_pulse_period(dac_pulse_period), .dac_pulse_height(dac_pulse_height), .dac_pulse_num(dac_pulse_num), .adc_pulse_period(adc_pulse_period), .adc_pulse_num(adc_pulse_num), .adc_window_size(adc_window_size), .dac_start(dac_start), .adc_start(adc_start), .dac_rst(dac_rst), .adc_rst(adc_rst) ); // CONTROLLER DMA dma_read_desc_t desc_read_cmd, desc_read_cmd_out; assign desc_read_cmd.addr = desc_read_addr; assign desc_read_cmd.len = desc_read_len; assign desc_read_cmd.tag = desc_read_config[TAG_WIDTH-1:0]; assign desc_read_cmd.id = desc_read_config[TAG_WIDTH +: AXIS_ID_WIDTH]; assign desc_read_cmd.dest = desc_read_config[TAG_WIDTH+AXIS_ID_WIDTH +: AXIS_DEST_WIDTH]; assign desc_read_cmd.user = desc_read_config[TAG_WIDTH+AXIS_ID_WIDTH+AXIS_DEST_WIDTH +: AXIS_USER_WIDTH]; dma_write_desc_t desc_write_cmd, desc_write_cmd_out; assign desc_write_cmd.addr = desc_write_addr; assign desc_write_cmd.len = desc_write_len_and_tag[LEN_WIDTH-1:0]; assign desc_write_cmd.tag = desc_write_len_and_tag[LEN_WIDTH +: TAG_WIDTH]; dma_read_status_t status_read_cmd, status_read_cmd_in; assign status_read = { status_read_cmd.error, status_read_cmd.tag}; dma_write_status_t status_write_cmd, status_write_cmd_in; assign status_write_len = status_write_cmd.len; assign status_write_config = { status_write_cmd.error, status_write_cmd.user, status_write_cmd.dest, status_write_cmd.id, status_write_cmd.tag}; dma_controller dma_controller_inst ( .dma_clk(ctrl_clk), .rst_n(rst_n), .send_desc_read(send_desc_read), .send_desc_write(send_desc_write), .take_status_read(take_status_read), .take_status_write(take_status_write), .desc_read_cmd(desc_read_cmd), .desc_write_cmd(desc_write_cmd), .status_read_cmd(status_read_cmd), .status_write_cmd(status_write_cmd), .desc_read_cmd_out(desc_read_cmd_out), .desc_write_cmd_out(desc_write_cmd_out), .status_read_cmd_in(status_read_cmd_in), .status_write_cmd_in(status_write_cmd_in), .ready_desc_read(m_axis_desc_read.resp.ready), .ready_desc_write(m_axis_desc_write.resp.ready), .ready_status_read(s_axis_status_read.resp.ready), .ready_status_write(s_axis_status_write.resp.ready), .valid_desc_read(m_axis_desc_read.req.t.valid), .valid_desc_write(m_axis_desc_write.req.t.valid), .valid_status_read(s_axis_status_read.req.t.valid), .valid_status_write(s_axis_status_write.req.t.valid), .desc_read_dma_busy(desc_read_dma_busy), .desc_write_dma_busy(desc_write_dma_busy), .status_read_dma_busy(status_read_dma_busy), .status_write_dma_busy(status_write_dma_busy), .desc_read_dma_hs(desc_read_dma_hs), .desc_write_dma_hs(desc_write_dma_hs), .status_read_dma_hs(status_read_dma_hs), .status_write_dma_hs(status_write_dma_hs) ); axis_defaults_master defaults_rd (.axis(m_axis_desc_read)); axis_defaults_master defaults_wr (.axis(m_axis_desc_write)); assign m_axis_desc_read.req.t.data = desc_read_cmd_out; assign m_axis_desc_write.req.t.data = desc_write_cmd_out; assign status_read_cmd_in = s_axis_status_read.req.t.data; assign status_write_cmd_in = s_axis_status_write.req.t.data; endmodule