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1c2eccaf1d
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rtl: reconstruction of registers for dma
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2026-07-20 17:28:48 +03:00 |
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c057890007
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fix: invalid signals
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2026-07-14 20:07:23 +03:00 |
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42df57be7d
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axis flat to if / if to flat correction
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2026-07-14 19:24:25 +03:00 |
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606d1d7f1c
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little axis desc status correction
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2026-07-14 19:07:32 +03:00 |
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8aefa4f3f6
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axis dma desc and status interface
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2026-07-14 18:39:48 +03:00 |
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6c171c55d7
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controller_wrapper_axil syntaxis corrected
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2026-07-14 13:55:42 +03:00 |
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d0f48ba513
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controller_wrapper_axil with DMA control registers
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2026-07-14 13:07:48 +03:00 |
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7bd1aa68da
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add window_sizereg and cfg_bus_valid_reg
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2026-07-10 14:03:07 +03:00 |
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99a344d534
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debugging controller
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2026-07-08 17:53:25 +03:00 |
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fc3134f2d8
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controller's changes
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2026-07-08 12:50:28 +03:00 |
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d71655885c
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rtl: axil wrapper logic for controller
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2026-07-07 17:33:25 +03:00 |
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