91 lines
2.9 KiB
Systemverilog
91 lines
2.9 KiB
Systemverilog
module axi4l_reg_map_controller #(
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parameter int unsigned ADDR_W = 16,
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parameter int unsigned DATA_W = 32,
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parameter int unsigned USER_W = 1
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)(
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input logic clk,
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input logic rst_n,
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axi4l_if.slave s_axil,
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// dac adc registers
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output logic start_o,
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output logic send_o,
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output logic cfg_bus_valid_o,
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output logic [31:0] pulse_width_o,
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output logic [31:0] pulse_period_o,
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output logic [31:0] pulse_num_o,
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output logic [31:0] pulse_height_raw_o,
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output logic [31:0] pulse_period_ADC_o,
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output logic [31:0] window_size_o,
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// DMA read descriptors and status register
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output logic [31:0] desc_read_addr_o,
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output logic [31:0] desc_read_len_o,
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output logic [31:0] desc_read_config_o,
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input logic [31:0] status_read_i,
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// DMA write descriptors and status register
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output logic [31:0] desc_write_addr_o,
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output logic [31:0] desc_write_len_and_tag_o,
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input logic [31:0] status_write_len_i,
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input logic [31:0] status_write_config_i,
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output logic rst_soft_o,
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input logic [7:0] busy_i,
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input logic [7:0] error_code_i
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);
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import axi4l_reg_map_controller_pkg::*;
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localparam int unsigned N_REGS = AXI4L_REG_MAP_EXAMPLE_N_REGS;
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logic [N_REGS-1:0][31:0] reg_i;
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logic [N_REGS-1:0][31:0] reg_o;
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logic [N_REGS-1:0][31:0] reg_pulse;
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axi4l_reg_map #(
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.ADDR_W (ADDR_W),
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.DATA_W (DATA_W),
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.USER_W (USER_W),
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.N_REGS (N_REGS),
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.REG_MODE (AXI4L_REG_MAP_EXAMPLE_REG_MODE),
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.REG_RST (AXI4L_REG_MAP_EXAMPLE_REG_RST)
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) u_reg_map (
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.clk (clk),
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.rst_n (rst_n),
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.s_axil (s_axil),
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.reg_i (reg_i),
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.reg_o (reg_o),
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.reg_pulse(reg_pulse)
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);
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always_comb begin
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reg_i = '0;
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reg_i[REG_STATUS][0] = busy_i;
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reg_i[REG_ERROR][7:0] = error_code_i;
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reg_i[REG_READ_STATUS] = status_read_i;
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reg_i[REG_STATUS_WRITE_LEN] = status_write_len_i;
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reg_i[REG_STATUS_WRITE_CONFIG] = status_write_config_i;
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end
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assign start_o = reg_pulse[REG_CONTROL][0];
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assign rst_soft_o = reg_pulse[REG_CONTROL][1];
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assign send_o = reg_pulse[REG_CONTROL][2];
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assign cfg_bus_valid_o = reg_pulse[REG_CONTROL][3];
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assign pulse_width_o = reg_o[REG_DAC_WIDTH];
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assign pulse_period_o = reg_o[REG_DAC_PERIOD];
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assign pulse_num_o = reg_o[REG_DAC_PULSE_NUM];
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assign pulse_height_raw_o = reg_o[REG_DAC_PULSE_HEIGHT];
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assign pulse_period_ADC_o = reg_o[REG_ADC_PERIOD];
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assign window_size_o = reg_o[REG_WINDOW_SIZE];
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assign desc_read_addr_o = reg_o[REG_DESC_READ_ADDR];
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assign desc_read_len_o = reg_o[REG_DESC_READ_LEN];
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assign desc_read_config_o = reg_o[REG_DESC_READ_CONFIG];
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assign desc_write_addr_o = reg_o[REG_DESC_WRITE_ADDR];
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assign desc_write_len_and_tag_o = reg_o[REG_DESC_WRITE_LEN_AND_TAG];
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endmodule
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