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126b66e4f5
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fix: port names in axi4l reg_map
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2026-07-10 17:51:30 +03:00 |
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c0a2f0e403
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add window_size register
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2026-07-10 14:15:17 +03:00 |
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a82140feda
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add send signal to start a dma transaction
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2026-07-08 12:49:51 +03:00 |
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56e31a6cc6
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rtl: add window_size register
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2026-07-07 17:32:42 +03:00 |
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a6ade44b4d
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rtl: eth remove
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2026-07-03 16:28:08 +03:00 |
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14f4a5eb2a
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rtl: register map addition for DMA control
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2026-06-30 17:13:00 +03:00 |
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1eb21b5087
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rtl: controller adc_dac management register map
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2026-06-30 13:12:51 +03:00 |
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