module axi4l_reg_map_controller #(
  parameter int unsigned ADDR_W = 16,
  parameter int unsigned DATA_W = 32,
  parameter int unsigned USER_W = 1
)(
  input  logic clk,
  input  logic rst_n,
  axi4l_if.slave s_axil,
// dac adc registers
  output logic        start_o,
  output logic        send_o,
  output logic        cfg_bus_valid_o,
  output logic [31:0] pulse_width_o,
  output logic [31:0] pulse_period_o,
  output logic [31:0] pulse_num_o,
  output logic [31:0] pulse_height_raw_o,
  output logic [31:0] pulse_period_ADC_o,
  output logic [31:0] window_size_o,

  // DMA read descriptors and status register
  output logic [31:0] desc_read_addr_o,
  output logic [31:0] desc_read_len_o,
  output logic [31:0] desc_read_config_o,

  input  logic [31:0] status_read_i,

  // DMA write descriptors and status register
  output logic [31:0] desc_write_addr_o,
  output logic [31:0] desc_write_len_and_tag_o,

  input  logic [31:0] status_write_len_i,
  input  logic [31:0] status_write_config_i,
  
  output logic        rst_soft_o,
  input  logic [7:0]  busy_i,
  input  logic [7:0]  error_code_i
);
  import axi4l_reg_map_controller_pkg::*;
  localparam int unsigned N_REGS = AXI4L_REG_MAP_EXAMPLE_N_REGS;

  logic [N_REGS-1:0][31:0] reg_i;
  logic [N_REGS-1:0][31:0] reg_o;
  logic [N_REGS-1:0][31:0] reg_pulse;

  axi4l_reg_map #(
    .ADDR_W  (ADDR_W),
    .DATA_W  (DATA_W),
    .USER_W  (USER_W),
    .N_REGS  (N_REGS),
    .REG_MODE (AXI4L_REG_MAP_EXAMPLE_REG_MODE),
    .REG_RST (AXI4L_REG_MAP_EXAMPLE_REG_RST)
  ) u_reg_map (
    .clk      (clk),
    .rst_n    (rst_n),
    .s_axil   (s_axil),
    .reg_i    (reg_i),
    .reg_o    (reg_o),
    .reg_pulse(reg_pulse)
  );

  always_comb begin
    reg_i = '0;

    reg_i[REG_STATUS][0] = busy_i;
    reg_i[REG_ERROR][7:0] = error_code_i;

    reg_i[REG_READ_STATUS] = status_read_i;
    reg_i[REG_STATUS_WRITE_LEN] = status_write_len_i;
    reg_i[REG_STATUS_WRITE_CONFIG] = status_write_config_i;

  end

  assign start_o                  = reg_pulse[REG_CONTROL][0];
  assign rst_soft_o               = reg_pulse[REG_CONTROL][1];
  assign send_o                   = reg_pulse[REG_CONTROL][2];
  assign cfg_bus_valid_o          = reg_pulse[REG_CONTROL][3];
  assign pulse_width_o            = reg_o[REG_DAC_WIDTH];
  assign pulse_period_o           = reg_o[REG_DAC_PERIOD];
  assign pulse_num_o              = reg_o[REG_DAC_PULSE_NUM];
  assign pulse_height_raw_o       = reg_o[REG_DAC_PULSE_HEIGHT]; 
  assign pulse_period_ADC_o       = reg_o[REG_ADC_PERIOD]; 
  assign window_size_o            = reg_o[REG_WINDOW_SIZE];

  assign desc_read_addr_o         = reg_o[REG_DESC_READ_ADDR];
  assign desc_read_len_o          = reg_o[REG_DESC_READ_LEN];
  assign desc_read_config_o       = reg_o[REG_DESC_READ_CONFIG];
  assign desc_write_addr_o        = reg_o[REG_DESC_WRITE_ADDR];
  assign desc_write_len_and_tag_o = reg_o[REG_DESC_WRITE_LEN_AND_TAG];

endmodule