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dev/contro
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3
.gitmodules
vendored
Normal file
3
.gitmodules
vendored
Normal file
@ -0,0 +1,3 @@
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[submodule "external/rtl_libs"]
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path = external/rtl_libs
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url = https://git.radiophotonics.ru/baulin.fa/rtl_libs.git
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189
designs/controller_dma_connective/src/axi_dma_wrapper_if.sv
Normal file
189
designs/controller_dma_connective/src/axi_dma_wrapper_if.sv
Normal file
@ -0,0 +1,189 @@
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// SPDX-License-Identifier: MIT
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//
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// SystemVerilog interface wrapper around alexforencich/verilog-axi axi_dma.v.
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//
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// AXI memory, AXI-Stream data, DMA descriptor, and DMA status channels are all
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// exposed through compact interfaces. The original Forencich core remains
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// untouched and is connected through local flat wires.
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`default_nettype none
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import dma_reg_pkg::*;
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// DMA Specific wrappers & converters
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module axi_dma_wrapper #(
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parameter int unsigned AXI_DATA_WIDTH = 32,
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parameter int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8,
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parameter int unsigned AXI_ID_WIDTH = 8,
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parameter int unsigned AXI_USER_WIDTH = 1,
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parameter int unsigned AXI_MAX_BURST_LEN = 16,
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parameter int unsigned AXIS_DATA_WIDTH = AXI_DATA_WIDTH,
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parameter int unsigned AXIS_KEEP_ENABLE = AXIS_DATA_WIDTH > 8,
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parameter int unsigned AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH / 8,
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parameter int unsigned AXIS_LAST_ENABLE = 1,
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parameter int unsigned AXIS_ID_ENABLE = 1,
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parameter int unsigned AXIS_DEST_ENABLE = 0,
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parameter int unsigned AXIS_USER_ENABLE = 1,
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parameter int unsigned ENABLE_SG = 0,
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parameter int unsigned ENABLE_UNALIGNED = 0
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)(
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input logic clk,
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input logic rst,
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axis_if.slave s_axis_read_desc,
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axis_if.master m_axis_read_desc_status,
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axis_if.master m_axis_read_data,
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axis_if.slave s_axis_write_desc,
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axis_if.master m_axis_write_desc_status,
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axis_if.slave s_axis_write_data,
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axi4_if.master m_axi
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);
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dma_read_desc_t read_desc;
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assign read_desc = dma_read_desc_t'(s_axis_read_desc.req.t.data);
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dma_write_desc_t write_desc;
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assign write_desc = dma_write_desc_t'(s_axis_write_desc.req.t.data);
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dma_read_status_t read_status;
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assign m_axis_read_desc_status.req.t.data = read_status;
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logic m_axis_read_desc_status_valid;
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assign m_axis_read_desc_status.req.t.valid = m_axis_read_desc_status_valid;
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dma_write_status_t write_status;
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assign m_axis_write_desc_status.req.t.data = write_status;
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logic m_axis_write_desc_status_valid;
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assign m_axis_write_desc_status.req.t.valid = m_axis_write_desc_status_valid;
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// Original DMA: flat ports only.
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axi_dma #(
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.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
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.AXI_ADDR_WIDTH (dma_reg_pkg::AXI_ADDR_WIDTH),
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.AXI_STRB_WIDTH (AXI_STRB_WIDTH),
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.AXI_ID_WIDTH (AXI_ID_WIDTH),
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.AXI_MAX_BURST_LEN (AXI_MAX_BURST_LEN),
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.AXIS_DATA_WIDTH (AXIS_DATA_WIDTH),
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.AXIS_KEEP_ENABLE (AXIS_KEEP_ENABLE),
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.AXIS_KEEP_WIDTH (AXIS_KEEP_WIDTH),
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.AXIS_LAST_ENABLE (AXIS_LAST_ENABLE),
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.AXIS_ID_ENABLE (AXIS_ID_ENABLE),
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.AXIS_ID_WIDTH (dma_reg_pkg::AXIS_ID_WIDTH),
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.AXIS_DEST_ENABLE (AXIS_DEST_ENABLE),
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.AXIS_DEST_WIDTH (dma_reg_pkg::AXIS_DEST_WIDTH),
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.AXIS_USER_ENABLE (AXIS_USER_ENABLE),
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.AXIS_USER_WIDTH (dma_reg_pkg::AXIS_USER_WIDTH),
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.LEN_WIDTH (dma_reg_pkg::LEN_WIDTH),
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.TAG_WIDTH (dma_reg_pkg::TAG_WIDTH),
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.ENABLE_SG (ENABLE_SG),
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.ENABLE_UNALIGNED (ENABLE_UNALIGNED)
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) i_axi_dma (
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.clk (clk),
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.rst (rst),
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.s_axis_read_desc_addr (read_desc.addr),
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.s_axis_read_desc_len (read_desc.len),
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.s_axis_read_desc_tag (read_desc.tag),
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.s_axis_read_desc_id (read_desc.id),
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.s_axis_read_desc_dest (read_desc.dest),
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.s_axis_read_desc_user (read_desc.user),
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.s_axis_read_desc_valid (s_axis_read_desc.req.t.valid),
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.s_axis_read_desc_ready (s_axis_read_desc.resp.ready),
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.m_axis_read_desc_status_tag (read_status.tag),
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.m_axis_read_desc_status_error (read_status.error),
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.m_axis_read_desc_status_valid (m_axis_read_desc_status_valid),
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.m_axis_read_data_tdata (m_axis_read_data.req.t.data),
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.m_axis_read_data_tkeep (m_axis_read_data.req.t.keep),
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.m_axis_read_data_tvalid (m_axis_read_data.req.t.valid),
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.m_axis_read_data_tready (m_axis_read_data.resp.ready),
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.m_axis_read_data_tlast (m_axis_read_data.req.t.last),
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.m_axis_read_data_tid (m_axis_read_data.req.t.id),
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.m_axis_read_data_tdest (m_axis_read_data.req.t.dest),
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.m_axis_read_data_tuser (m_axis_read_data.req.t.user),
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.s_axis_write_desc_addr (write_desc.addr),
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.s_axis_write_desc_len (write_desc.len),
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.s_axis_write_desc_tag (write_desc.tag),
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.s_axis_write_desc_valid (s_axis_write_desc.req.t.valid),
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.s_axis_write_desc_ready (s_axis_write_desc.resp.ready),
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.m_axis_write_desc_status_len (write_status.len),
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.m_axis_write_desc_status_tag (write_status.tag),
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.m_axis_write_desc_status_id (write_status.id),
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.m_axis_write_desc_status_dest (write_status.dest),
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.m_axis_write_desc_status_user (write_status.user),
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.m_axis_write_desc_status_error (write_status.error),
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.m_axis_write_desc_status_valid (m_axis_write_desc_status_valid),
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.s_axis_write_data_tdata (s_axis_write_data.req.t.data),
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.s_axis_write_data_tkeep (s_axis_write_data.req.t.keep),
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.s_axis_write_data_tvalid (s_axis_write_data.req.t.valid),
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.s_axis_write_data_tready (s_axis_write_data.resp.ready),
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.s_axis_write_data_tlast (s_axis_write_data.req.t.last),
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.s_axis_write_data_tid (s_axis_write_data.req.t.id),
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.s_axis_write_data_tdest (s_axis_write_data.req.t.dest),
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.s_axis_write_data_tuser (s_axis_write_data.req.t.user),
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.m_axi_awid (m_axi.req.aw.id),
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.m_axi_awaddr (m_axi.req.aw.addr),
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.m_axi_awlen (m_axi.req.aw.len),
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.m_axi_awsize (m_axi.req.aw.size),
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.m_axi_awburst (m_axi.req.aw.burst),
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.m_axi_awlock (m_axi.req.aw.lock),
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.m_axi_awcache (m_axi.req.aw.cache),
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.m_axi_awprot (m_axi.req.aw.prot),
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.m_axi_awvalid (m_axi.req.aw.valid),
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.m_axi_awready (m_axi.resp.aw_ready),
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.m_axi_wdata (m_axi.req.w.data),
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.m_axi_wstrb (m_axi.req.w.strb),
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.m_axi_wlast ( m_axi.req.w.last),
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.m_axi_wvalid (m_axi.req.w.valid),
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.m_axi_wready (m_axi.resp.w_ready),
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.m_axi_bid (m_axi.resp.b.id),
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.m_axi_bresp (m_axi.resp.b.resp),
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.m_axi_bvalid (m_axi.resp.b.valid),
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.m_axi_bready (m_axi.req.b_ready),
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.m_axi_arid (m_axi.req.ar.id),
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.m_axi_araddr (m_axi.req.ar.addr),
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.m_axi_arlen (m_axi.req.ar.len),
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.m_axi_arsize (m_axi.req.ar.size),
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.m_axi_arburst (m_axi.req.ar.burst),
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.m_axi_arlock (m_axi.req.ar.lock),
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.m_axi_arcache (m_axi.req.ar.cache),
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.m_axi_arprot (m_axi.req.ar.prot),
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.m_axi_arvalid (m_axi.req.ar.valid),
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.m_axi_arready (m_axi.resp.ar_ready),
|
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.m_axi_rid (m_axi.resp.r.id),
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.m_axi_rdata (m_axi.resp.r.data),
|
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.m_axi_rresp (m_axi.resp.r.resp),
|
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.m_axi_rlast (m_axi.resp.r.last),
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.m_axi_rvalid (m_axi.resp.r.valid),
|
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.m_axi_rready (m_axi.req.r_ready),
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.read_enable (1'b1),
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.write_enable (1'b1),
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.write_abort (1'b0)
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);
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endmodule : axi_dma_wrapper
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`default_nettype wire
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169
designs/controller_dma_connective/src/wrapper_controller_dma.sv
Normal file
169
designs/controller_dma_connective/src/wrapper_controller_dma.sv
Normal file
@ -0,0 +1,169 @@
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import dma_reg_pkg::*;
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module wrapper_controller_dma
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#(
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parameter int unsigned ADDR_W = 16,
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parameter int unsigned DATA_W = 32,
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parameter int unsigned USER_W = 1,
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parameter int unsigned DAC_DATA_WIDTH = 12,
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parameter int unsigned AXI_DATA_WIDTH = 32,
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parameter int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8,
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parameter int unsigned AXI_ID_WIDTH = 8,
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parameter int unsigned AXI_USER_WIDTH = 1,
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parameter int unsigned AXI_MAX_BURST_LEN = 16,
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parameter int unsigned AXIS_DATA_WIDTH = AXI_DATA_WIDTH,
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parameter int unsigned AXIS_KEEP_ENABLE = AXIS_DATA_WIDTH > 8,
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parameter int unsigned AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH / 8,
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parameter int unsigned AXIS_LAST_ENABLE = 1,
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parameter int unsigned AXIS_ID_ENABLE = 1,
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parameter int unsigned AXIS_DEST_ENABLE = 0,
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parameter int unsigned AXIS_USER_ENABLE = 1,
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parameter int unsigned ENABLE_SG = 0,
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parameter int unsigned ENABLE_UNALIGNED = 0
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)
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(
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input logic ctrl_clk,
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input logic dac_clk_in,
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input logic adc_clk_in,
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||||
input logic rst_n,
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||||
axi4l_if.slave s_axil,
|
||||
|
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// adc_clk_in domain
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input logic finish,
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||||
output logic [31:0] adc_window_size,
|
||||
|
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// dac_clk_in domain outputs
|
||||
output logic [31:0] dac_pulse_width,
|
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output logic [31:0] dac_pulse_period,
|
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output logic [DAC_DATA_WIDTH-1:0] dac_pulse_height,
|
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output logic [15:0] dac_pulse_num,
|
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|
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// adc_clk_in domain outputs
|
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output logic [31:0] adc_pulse_period,
|
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output logic [15:0] adc_pulse_num,
|
||||
|
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// pulse outputs
|
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output logic dac_start,
|
||||
output logic adc_start,
|
||||
output logic dac_rst,
|
||||
output logic adc_rst,
|
||||
|
||||
axis_if.master m_axis_read_data,
|
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axis_if.slave s_axis_write_data,
|
||||
|
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axi4_if.master m_axi
|
||||
);
|
||||
|
||||
axis_if #(
|
||||
.DATA_W($bits(dma_read_status_t)),
|
||||
.KEEP_W(($bits(dma_read_status_t)+7)/8),
|
||||
.ID_W(dma_reg_pkg::AXIS_ID_WIDTH),
|
||||
.DEST_W(dma_reg_pkg::AXIS_DEST_WIDTH),
|
||||
.USER_W(dma_reg_pkg::AXIS_USER_WIDTH)
|
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) s_axis_status_read (
|
||||
.aclk(ctrl_clk),
|
||||
.aresetn(rst_n)
|
||||
);
|
||||
|
||||
axis_if #(
|
||||
.DATA_W($bits(dma_write_status_t)),
|
||||
.KEEP_W(($bits(dma_write_status_t)+7)/8),
|
||||
.ID_W(dma_reg_pkg::AXIS_ID_WIDTH),
|
||||
.DEST_W(dma_reg_pkg::AXIS_DEST_WIDTH),
|
||||
.USER_W(dma_reg_pkg::AXIS_USER_WIDTH)
|
||||
) s_axis_status_write (
|
||||
.aclk(ctrl_clk),
|
||||
.aresetn(rst_n)
|
||||
);
|
||||
|
||||
axis_if #(
|
||||
.DATA_W($bits(dma_read_desc_t)),
|
||||
.KEEP_W(($bits(dma_read_desc_t)+7)/8),
|
||||
.ID_W(dma_reg_pkg::AXIS_ID_WIDTH),
|
||||
.DEST_W(dma_reg_pkg::AXIS_DEST_WIDTH),
|
||||
.USER_W(dma_reg_pkg::AXIS_USER_WIDTH)
|
||||
) m_axis_desc_read (
|
||||
.aclk(ctrl_clk),
|
||||
.aresetn(rst_n)
|
||||
);
|
||||
|
||||
axis_if #(
|
||||
.DATA_W($bits(dma_write_desc_t)),
|
||||
.KEEP_W(($bits(dma_write_desc_t)+7)/8),
|
||||
.ID_W(dma_reg_pkg::AXIS_ID_WIDTH),
|
||||
.DEST_W(dma_reg_pkg::AXIS_DEST_WIDTH),
|
||||
.USER_W(dma_reg_pkg::AXIS_USER_WIDTH)
|
||||
) m_axis_desc_write (
|
||||
.aclk(ctrl_clk),
|
||||
.aresetn(rst_n)
|
||||
);
|
||||
|
||||
controller_wrapper_axil
|
||||
#(
|
||||
.ADDR_W(ADDR_W),
|
||||
.DATA_W(DATA_W),
|
||||
.USER_W(USER_W),
|
||||
.DAC_DATA_WIDTH(DAC_DATA_WIDTH)
|
||||
)
|
||||
controller_wrapper_axil_inst
|
||||
(
|
||||
.ctrl_clk(ctrl_clk),
|
||||
.dac_clk_in(dac_clk_in),
|
||||
.adc_clk_in(adc_clk_in),
|
||||
.rst_n(rst_n),
|
||||
|
||||
.s_axil(s_axil),
|
||||
|
||||
.finish(finish),
|
||||
.adc_window_size(adc_window_size),
|
||||
.dac_pulse_width(dac_pulse_width),
|
||||
.dac_pulse_period(dac_pulse_period),
|
||||
.dac_pulse_height(dac_pulse_height),
|
||||
.dac_pulse_num(dac_pulse_num),
|
||||
.adc_pulse_period(adc_pulse_period),
|
||||
.adc_pulse_num(adc_pulse_num),
|
||||
.dac_start(dac_start),
|
||||
.adc_start(adc_start),
|
||||
.dac_rst(dac_rst),
|
||||
.adc_rst(adc_rst),
|
||||
|
||||
.s_axis_status_read(s_axis_status_read),
|
||||
.s_axis_status_write(s_axis_status_write),
|
||||
.m_axis_desc_read(m_axis_desc_read),
|
||||
.m_axis_desc_write(m_axis_desc_write)
|
||||
);
|
||||
|
||||
axi_dma_wrapper
|
||||
#(
|
||||
.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
|
||||
.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
|
||||
.AXI_USER_WIDTH(AXI_USER_WIDTH),
|
||||
.AXI_MAX_BURST_LEN(AXI_MAX_BURST_LEN),
|
||||
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
|
||||
.AXIS_KEEP_ENABLE(AXIS_KEEP_ENABLE),
|
||||
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
|
||||
.AXIS_LAST_ENABLE(AXIS_LAST_ENABLE),
|
||||
.AXIS_ID_ENABLE(AXIS_ID_ENABLE),
|
||||
.AXIS_DEST_ENABLE(AXIS_DEST_ENABLE),
|
||||
.AXIS_USER_ENABLE(AXIS_USER_ENABLE),
|
||||
.ENABLE_SG(ENABLE_SG),
|
||||
.ENABLE_UNALIGNED(ENABLE_UNALIGNED)
|
||||
)
|
||||
axi_dma_wrapper_inst
|
||||
(
|
||||
.clk(ctrl_clk),
|
||||
.rst(!rst_n),
|
||||
.s_axis_read_desc(m_axis_desc_read),
|
||||
.m_axis_read_desc_status(s_axis_status_read),
|
||||
.m_axis_read_data(m_axis_read_data),
|
||||
.s_axis_write_desc(m_axis_desc_write),
|
||||
.m_axis_write_desc_status(s_axis_status_write),
|
||||
.s_axis_write_data(s_axis_write_data),
|
||||
.m_axi(m_axi)
|
||||
);
|
||||
endmodule
|
||||
46
designs/controller_dma_connective/tests/Makefile
Normal file
46
designs/controller_dma_connective/tests/Makefile
Normal file
@ -0,0 +1,46 @@
|
||||
TOPLEVEL_LANG = verilog
|
||||
SIM ?= verilator
|
||||
|
||||
PWD := $(shell pwd)
|
||||
|
||||
WRAP_DIR = $(PWD)/../src
|
||||
RTL_DIR = $(PWD)/../../controller/src
|
||||
LIBS_DIR = $(PWD)/../../../external/rtl_libs
|
||||
|
||||
VERILOG_SOURCES += $(LIBS_DIR)/axi/rtl/axi_pkg.sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/dma_reg_pkg.sv
|
||||
VERILOG_SOURCES += $(LIBS_DIR)/axi/rtl/axi_if.sv
|
||||
VERILOG_SOURCES += $(LIBS_DIR)/axi/axi_reg/axi4l_reg_map.sv
|
||||
VERILOG_SOURCES += $(LIBS_DIR)/external/verilog-axi/rtl/axi_dma_rd.v
|
||||
VERILOG_SOURCES += $(LIBS_DIR)/external/verilog-axi/rtl/axi_dma_wr.v
|
||||
VERILOG_SOURCES += $(LIBS_DIR)/external/verilog-axi/rtl/axi_dma.v
|
||||
VERILOG_SOURCES += $(RTL_DIR)/controller.sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/dma_controller.sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/shaper_axis_desc.sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/shaper_axis_status.sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/controller_wrapper_axil.sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/axi4l_reg_map_controller_pkg.sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/axis_defaults_helper.sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/axi4l_reg_map_controller.sv
|
||||
VERILOG_SOURCES += $(WRAP_DIR)/wrapper_controller_dma.sv
|
||||
VERILOG_SOURCES += $(WRAP_DIR)/axi_dma_wrapper_if.sv
|
||||
VERILOG_SOURCES += $(PWD)/tb_controller_dma_wrapper_axil.sv
|
||||
|
||||
TOPLEVEL = tb_controller_dma_wrapper_axil
|
||||
MODULE = test_controller_and_dma
|
||||
|
||||
|
||||
ifeq ($(SIM),verilator)
|
||||
EXTRA_ARGS += --trace --trace-structs
|
||||
EXTRA_ARGS += -I$(LIBS_DIR)/axi/rtl/
|
||||
COMPILE_ARGS += -Wno-fatal
|
||||
COMPILE_ARGS += -I$(LIBS_DIR)/axi/rtl/
|
||||
EXTRA_ARGS += --trace
|
||||
EXTRA_ARGS += --trace-structs
|
||||
EXTRA_ARGS += --public-flat-rw
|
||||
EXTRA_ARGS += -Wno-fatal
|
||||
EXTRA_ARGS += --timing
|
||||
endif
|
||||
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
@ -0,0 +1,236 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<wave_config>
|
||||
<wave_state>
|
||||
</wave_state>
|
||||
<db_ref_list>
|
||||
<db_ref path="tb_control_behav.wdb" id="1">
|
||||
<top_modules>
|
||||
<top_module name="glbl" />
|
||||
<top_module name="tb_control" />
|
||||
</top_modules>
|
||||
</db_ref>
|
||||
</db_ref_list>
|
||||
<zoom_setting>
|
||||
<ZoomStartTime time="160.614 ns"></ZoomStartTime>
|
||||
<ZoomEndTime time="1,564.737 ns"></ZoomEndTime>
|
||||
<Cursor1Time time="1,330.716 ns"></Cursor1Time>
|
||||
</zoom_setting>
|
||||
<column_width_setting>
|
||||
<NameColumnWidth column_width="479"></NameColumnWidth>
|
||||
<ValueColumnWidth column_width="116"></ValueColumnWidth>
|
||||
</column_width_setting>
|
||||
<WVObjectSize size="34" />
|
||||
<wvobject fp_name="/tb_control/dac_clk_in" type="logic">
|
||||
<obj_property name="ElementShortName">dac_clk_in</obj_property>
|
||||
<obj_property name="ObjectShortName">dac_clk_in</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FFA500</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/adc_clk_in" type="logic">
|
||||
<obj_property name="ElementShortName">adc_clk_in</obj_property>
|
||||
<obj_property name="ObjectShortName">adc_clk_in</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/rst_n" type="logic">
|
||||
<obj_property name="ElementShortName">rst_n</obj_property>
|
||||
<obj_property name="ObjectShortName">rst_n</obj_property>
|
||||
<obj_property name="CustomSignalColor">#800080</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/rst_soft" type="logic">
|
||||
<obj_property name="ElementShortName">rst_soft</obj_property>
|
||||
<obj_property name="ObjectShortName">rst_soft</obj_property>
|
||||
<obj_property name="CustomSignalColor">#008080</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/start" type="logic">
|
||||
<obj_property name="ElementShortName">start</obj_property>
|
||||
<obj_property name="ObjectShortName">start</obj_property>
|
||||
<obj_property name="CustomSignalColor">#E0FFFF</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/dut/adc_start_pulse" type="logic">
|
||||
<obj_property name="ElementShortName">adc_start_pulse</obj_property>
|
||||
<obj_property name="ObjectShortName">adc_start_pulse</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/dut/dac_start_pulse" type="logic">
|
||||
<obj_property name="ElementShortName">dac_start_pulse</obj_property>
|
||||
<obj_property name="ObjectShortName">dac_start_pulse</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/busy" type="logic">
|
||||
<obj_property name="ElementShortName">busy</obj_property>
|
||||
<obj_property name="ObjectShortName">busy</obj_property>
|
||||
<obj_property name="CustomSignalColor">#E0FFFF</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/finish" type="logic">
|
||||
<obj_property name="ElementShortName">finish</obj_property>
|
||||
<obj_property name="ObjectShortName">finish</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FAAFBE</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/dut/finish_pulse" type="logic">
|
||||
<obj_property name="ElementShortName">finish_pulse</obj_property>
|
||||
<obj_property name="ObjectShortName">finish_pulse</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/cfg_bus_valid" type="logic">
|
||||
<obj_property name="ElementShortName">cfg_bus_valid</obj_property>
|
||||
<obj_property name="ObjectShortName">cfg_bus_valid</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FF0080</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/cfg_bus_input" type="array">
|
||||
<obj_property name="ElementShortName">cfg_bus_input[159:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">cfg_bus_input[159:0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FF0080</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/dac_pulse_width" type="array">
|
||||
<obj_property name="ElementShortName">dac_pulse_width[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">dac_pulse_width[31:0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FFA500</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/dac_pulse_period" type="array">
|
||||
<obj_property name="ElementShortName">dac_pulse_period[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">dac_pulse_period[31:0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FFA500</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/dac_pulse_height" type="array">
|
||||
<obj_property name="ElementShortName">dac_pulse_height[11:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">dac_pulse_height[11:0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FFA500</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/dac_pulse_num" type="array">
|
||||
<obj_property name="ElementShortName">dac_pulse_num[15:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">dac_pulse_num[15:0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FFA500</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/adc_pulse_period" type="array">
|
||||
<obj_property name="ElementShortName">adc_pulse_period[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">adc_pulse_period[31:0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FFA500</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/adc_pulse_num" type="array">
|
||||
<obj_property name="ElementShortName">adc_pulse_num[15:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">adc_pulse_num[15:0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FFA500</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/adc_window_size" type="array">
|
||||
<obj_property name="ElementShortName">adc_window_size[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">adc_window_size[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/dac_start" type="logic">
|
||||
<obj_property name="ElementShortName">dac_start</obj_property>
|
||||
<obj_property name="ObjectShortName">dac_start</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FFA500</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/adc_start" type="logic">
|
||||
<obj_property name="ElementShortName">adc_start</obj_property>
|
||||
<obj_property name="ObjectShortName">adc_start</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/dac_rst" type="logic">
|
||||
<obj_property name="ElementShortName">dac_rst</obj_property>
|
||||
<obj_property name="ObjectShortName">dac_rst</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FFA500</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/adc_rst" type="logic">
|
||||
<obj_property name="ElementShortName">adc_rst</obj_property>
|
||||
<obj_property name="ObjectShortName">adc_rst</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="group499" type="group">
|
||||
<obj_property name="label">tb signals</obj_property>
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
<wvobject fp_name="/tb_control/dac_rst_count" type="array">
|
||||
<obj_property name="ElementShortName">dac_rst_count[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">dac_rst_count[31:0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#F0E68C</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/adc_rst_count" type="array">
|
||||
<obj_property name="ElementShortName">adc_rst_count[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">adc_rst_count[31:0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#F0E68C</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/dac_start_count" type="array">
|
||||
<obj_property name="ElementShortName">dac_start_count[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">dac_start_count[31:0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#F0E68C</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/adc_start_count" type="array">
|
||||
<obj_property name="ElementShortName">adc_start_count[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">adc_start_count[31:0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#F0E68C</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/dut/cfg_req_toggle_adc" type="logic">
|
||||
<obj_property name="ElementShortName">cfg_req_toggle_adc</obj_property>
|
||||
<obj_property name="ObjectShortName">cfg_req_toggle_adc</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FFFF00</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/dut/cfg_req_toggle_dac" type="logic">
|
||||
<obj_property name="ElementShortName">cfg_req_toggle_dac</obj_property>
|
||||
<obj_property name="ObjectShortName">cfg_req_toggle_dac</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FFFF00</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/dut/cfg_ack_toggle_adc" type="logic">
|
||||
<obj_property name="ElementShortName">cfg_ack_toggle_adc</obj_property>
|
||||
<obj_property name="ObjectShortName">cfg_ack_toggle_adc</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FF00FF</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/dut/cfg_ack_toggle_dac" type="logic">
|
||||
<obj_property name="ElementShortName">cfg_ack_toggle_dac</obj_property>
|
||||
<obj_property name="ObjectShortName">cfg_ack_toggle_dac</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FF00FF</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/dut/cfg_wait_adc_ack" type="logic">
|
||||
<obj_property name="ElementShortName">cfg_wait_adc_ack</obj_property>
|
||||
<obj_property name="ObjectShortName">cfg_wait_adc_ack</obj_property>
|
||||
<obj_property name="CustomSignalColor">#0000FF</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/dut/cfg_wait_dac_ack" type="logic">
|
||||
<obj_property name="ElementShortName">cfg_wait_dac_ack</obj_property>
|
||||
<obj_property name="ObjectShortName">cfg_wait_dac_ack</obj_property>
|
||||
<obj_property name="CustomSignalColor">#0000FF</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/dut/cfg_req_pulse_adc" type="logic">
|
||||
<obj_property name="ElementShortName">cfg_req_pulse_adc</obj_property>
|
||||
<obj_property name="ObjectShortName">cfg_req_pulse_adc</obj_property>
|
||||
<obj_property name="CustomSignalColor">#808000</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/dut/cfg_req_pulse_dac" type="logic">
|
||||
<obj_property name="ElementShortName">cfg_req_pulse_dac</obj_property>
|
||||
<obj_property name="ObjectShortName">cfg_req_pulse_dac</obj_property>
|
||||
<obj_property name="CustomSignalColor">#808000</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/dut/cfg_ack_pulse_adc" type="logic">
|
||||
<obj_property name="ElementShortName">cfg_ack_pulse_adc</obj_property>
|
||||
<obj_property name="ObjectShortName">cfg_ack_pulse_adc</obj_property>
|
||||
<obj_property name="CustomSignalColor">#DCDCDC</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/dut/cfg_ack_pulse_dac" type="logic">
|
||||
<obj_property name="ElementShortName">cfg_ack_pulse_dac</obj_property>
|
||||
<obj_property name="ObjectShortName">cfg_ack_pulse_dac</obj_property>
|
||||
<obj_property name="CustomSignalColor">#DCDCDC</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
</wave_config>
|
||||
@ -0,0 +1,373 @@
|
||||
|
||||
import dma_reg_pkg::*;
|
||||
|
||||
module tb_controller_wrapper_axil #(
|
||||
parameter int unsigned ADDR_W = 16,
|
||||
parameter int unsigned DATA_W = 32,
|
||||
parameter int unsigned USER_W = 1,
|
||||
|
||||
parameter int unsigned DAC_DATA_WIDTH = 12,
|
||||
|
||||
parameter int unsigned AXI_DATA_WIDTH = 32,
|
||||
|
||||
parameter int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8,
|
||||
parameter int unsigned AXI_ID_WIDTH = 8,
|
||||
parameter int unsigned AXI_USER_WIDTH = 1,
|
||||
parameter int unsigned AXI_MAX_BURST_LEN = 16,
|
||||
|
||||
parameter int unsigned AXIS_DATA_WIDTH = AXI_DATA_WIDTH,
|
||||
parameter int unsigned AXIS_KEEP_ENABLE = AXIS_DATA_WIDTH > 8,
|
||||
parameter int unsigned AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH / 8,
|
||||
parameter int unsigned AXIS_LAST_ENABLE = 1,
|
||||
parameter int unsigned AXIS_ID_ENABLE = 1,
|
||||
parameter int unsigned AXIS_DEST_ENABLE = 0,
|
||||
parameter int unsigned AXIS_USER_ENABLE = 1,
|
||||
|
||||
parameter int unsigned ENABLE_SG = 0,
|
||||
parameter int unsigned ENABLE_UNALIGNED = 0
|
||||
)(
|
||||
input logic ctrl_clk,
|
||||
input logic rst,
|
||||
|
||||
input logic [ADDR_W-1:0] s_axil_awaddr,
|
||||
input logic [2:0] s_axil_awprot,
|
||||
input logic s_axil_awvalid,
|
||||
output logic s_axil_awready,
|
||||
|
||||
input logic [DATA_W-1:0] s_axil_wdata,
|
||||
input logic [DATA_W/8-1:0] s_axil_wstrb,
|
||||
input logic s_axil_wvalid,
|
||||
output logic s_axil_wready,
|
||||
|
||||
output logic [1:0] s_axil_bresp,
|
||||
output logic s_axil_bvalid,
|
||||
input logic s_axil_bready,
|
||||
|
||||
input logic [ADDR_W-1:0] s_axil_araddr,
|
||||
input logic [2:0] s_axil_arprot,
|
||||
input logic s_axil_arvalid,
|
||||
output logic s_axil_arready,
|
||||
|
||||
output logic [DATA_W-1:0] s_axil_rdata,
|
||||
output logic [1:0] s_axil_rresp,
|
||||
output logic s_axil_rvalid,
|
||||
input logic s_axil_rready,
|
||||
|
||||
input wire [AXIS_DATA_WIDTH-1:0] s_axis_write_data_tdata,
|
||||
input wire [AXIS_KEEP_WIDTH-1:0] s_axis_write_data_tkeep,
|
||||
input wire s_axis_write_data_tvalid,
|
||||
output wire s_axis_write_data_tready,
|
||||
input wire s_axis_write_data_tlast,
|
||||
input wire [AXIS_ID_WIDTH-1:0] s_axis_write_data_tid,
|
||||
input wire [AXIS_DEST_WIDTH-1:0] s_axis_write_data_tdest,
|
||||
input wire [AXIS_USER_WIDTH-1:0] s_axis_write_data_tuser,
|
||||
|
||||
output wire [AXIS_DATA_WIDTH-1:0] m_axis_read_data_tdata,
|
||||
output wire [AXIS_KEEP_WIDTH-1:0] m_axis_read_data_tkeep,
|
||||
output wire m_axis_read_data_tvalid,
|
||||
input wire m_axis_read_data_tready,
|
||||
output wire m_axis_read_data_tlast,
|
||||
output wire [AXIS_ID_WIDTH-1:0] m_axis_read_data_tid,
|
||||
output wire [AXIS_DEST_WIDTH-1:0] m_axis_read_data_tdest,
|
||||
output wire [AXIS_USER_WIDTH-1:0] m_axis_read_data_tuser,
|
||||
|
||||
output wire [AXI_ID_WIDTH-1:0] m_axi_awid,
|
||||
output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
|
||||
output wire [7:0] m_axi_awlen,
|
||||
output wire [2:0] m_axi_awsize,
|
||||
output wire [1:0] m_axi_awburst,
|
||||
output wire m_axi_awlock,
|
||||
output wire [3:0] m_axi_awcache,
|
||||
output wire [2:0] m_axi_awprot,
|
||||
output wire m_axi_awvalid,
|
||||
input wire m_axi_awready,
|
||||
output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata,
|
||||
output wire [AXI_STRB_WIDTH-1:0] m_axi_wstrb,
|
||||
output wire m_axi_wlast,
|
||||
output wire m_axi_wvalid,
|
||||
input wire m_axi_wready,
|
||||
input wire [AXI_ID_WIDTH-1:0] m_axi_bid,
|
||||
input wire [1:0] m_axi_bresp,
|
||||
input wire m_axi_bvalid,
|
||||
output wire m_axi_bready,
|
||||
output wire [AXI_ID_WIDTH-1:0] m_axi_arid,
|
||||
output wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr,
|
||||
output wire [7:0] m_axi_arlen,
|
||||
output wire [2:0] m_axi_arsize,
|
||||
output wire [1:0] m_axi_arburst,
|
||||
output wire m_axi_arlock,
|
||||
output wire [3:0] m_axi_arcache,
|
||||
output wire [2:0] m_axi_arprot,
|
||||
output wire m_axi_arvalid,
|
||||
input wire m_axi_arready,
|
||||
input wire [AXI_ID_WIDTH-1:0] m_axi_rid,
|
||||
input wire [AXI_DATA_WIDTH-1:0] m_axi_rdata,
|
||||
input wire [1:0] m_axi_rresp,
|
||||
input wire m_axi_rlast,
|
||||
input wire m_axi_rvalid,
|
||||
output wire m_axi_rready
|
||||
|
||||
|
||||
);
|
||||
|
||||
logic rst_n;
|
||||
assign rst_n = ~rst;
|
||||
|
||||
// Для минимального теста держим все clock domain-ы на одном clock.
|
||||
logic dac_clk_in;
|
||||
logic adc_clk_in;
|
||||
assign dac_clk_in = ctrl_clk;
|
||||
assign adc_clk_in = ctrl_clk;
|
||||
|
||||
logic finish;
|
||||
assign finish = 1'b0;
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
// AXI-Lite flat -> axi4l_if
|
||||
// ---------------------------------------------------------------------------
|
||||
|
||||
axi4l_if #(
|
||||
.ADDR_W(ADDR_W),
|
||||
.DATA_W(DATA_W),
|
||||
.USER_W(USER_W)
|
||||
) axil_bus (
|
||||
.aclk(ctrl_clk),
|
||||
.aresetn(rst_n)
|
||||
);
|
||||
|
||||
axi4l_flat_to_if #(
|
||||
.ADDR_W(ADDR_W),
|
||||
.DATA_W(DATA_W),
|
||||
.USER_W(USER_W)
|
||||
) u_axil_flat_to_if (
|
||||
.s_axil_awaddr (s_axil_awaddr),
|
||||
.s_axil_awprot (s_axil_awprot),
|
||||
.s_axil_awvalid(s_axil_awvalid),
|
||||
.s_axil_awready(s_axil_awready),
|
||||
|
||||
.s_axil_wdata (s_axil_wdata),
|
||||
.s_axil_wstrb (s_axil_wstrb),
|
||||
.s_axil_wvalid (s_axil_wvalid),
|
||||
.s_axil_wready (s_axil_wready),
|
||||
|
||||
.s_axil_bresp (s_axil_bresp),
|
||||
.s_axil_bvalid (s_axil_bvalid),
|
||||
.s_axil_bready (s_axil_bready),
|
||||
|
||||
.s_axil_araddr (s_axil_araddr),
|
||||
.s_axil_arprot (s_axil_arprot),
|
||||
.s_axil_arvalid(s_axil_arvalid),
|
||||
.s_axil_arready(s_axil_arready),
|
||||
|
||||
.s_axil_rdata (s_axil_rdata),
|
||||
.s_axil_rresp (s_axil_rresp),
|
||||
.s_axil_rvalid (s_axil_rvalid),
|
||||
.s_axil_rready (s_axil_rready),
|
||||
|
||||
.m_axil(axil_bus)
|
||||
);
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
// AXIS interfaces for the updated controller_wrapper_axil
|
||||
// ---------------------------------------------------------------------------
|
||||
|
||||
// AXIS READ DMA MASTER output
|
||||
axis_if #(
|
||||
.DATA_W (AXIS_DATA_WIDTH),
|
||||
.KEEP_W (AXIS_KEEP_WIDTH),
|
||||
.ID_W (AXIS_ID_WIDTH),
|
||||
.DEST_W (AXIS_DEST_WIDTH),
|
||||
.USER_W (AXIS_USER_WIDTH)
|
||||
) dma_read_data (
|
||||
.aclk(ctrl_clk),
|
||||
.aresetn(rst_n)
|
||||
);
|
||||
|
||||
logic [AXIS_KEEP_WIDTH-1:0] unused_read_tstrb;
|
||||
|
||||
axis_if_to_flat #(
|
||||
.DATA_W (AXIS_DATA_WIDTH),
|
||||
.KEEP_W (AXIS_KEEP_WIDTH),
|
||||
.ID_W (AXIS_ID_WIDTH),
|
||||
.DEST_W (AXIS_DEST_WIDTH),
|
||||
.USER_W (AXIS_USER_WIDTH)
|
||||
) u_read_data_if_to_flat (
|
||||
.s_axis(dma_read_data),
|
||||
|
||||
.m_axis_tdata (m_axis_read_data_tdata),
|
||||
.m_axis_tkeep (m_axis_read_data_tkeep),
|
||||
.m_axis_tstrb (unused_read_tstrb),
|
||||
.m_axis_tlast (m_axis_read_data_tlast),
|
||||
.m_axis_tid (m_axis_read_data_tid),
|
||||
.m_axis_tdest (m_axis_read_data_tdest),
|
||||
.m_axis_tuser (m_axis_read_data_tuser),
|
||||
.m_axis_tvalid(m_axis_read_data_tvalid),
|
||||
.m_axis_tready(m_axis_read_data_tready)
|
||||
);
|
||||
|
||||
// AXIS WRITE DMA SLAVE input
|
||||
axis_if #(
|
||||
.DATA_W (AXIS_DATA_WIDTH),
|
||||
.KEEP_W (AXIS_KEEP_WIDTH),
|
||||
.ID_W (AXIS_ID_WIDTH),
|
||||
.DEST_W (AXIS_DEST_WIDTH),
|
||||
.USER_W (AXIS_USER_WIDTH)
|
||||
) dma_write_data (
|
||||
.aclk(ctrl_clk),
|
||||
.aresetn(rst_n)
|
||||
);
|
||||
|
||||
|
||||
axis_flat_to_if #(
|
||||
.DATA_W (AXIS_DATA_WIDTH),
|
||||
.KEEP_W (AXIS_KEEP_WIDTH),
|
||||
.ID_W (AXIS_ID_WIDTH),
|
||||
.DEST_W (AXIS_DEST_WIDTH),
|
||||
.USER_W (AXIS_USER_WIDTH)
|
||||
) u_write_data_flat_to_if (
|
||||
.s_axis_tdata (s_axis_write_data_tdata),
|
||||
.s_axis_tkeep (s_axis_write_data_tkeep),
|
||||
.s_axis_tstrb (s_axis_write_data_tkeep),
|
||||
.s_axis_tlast (s_axis_write_data_tlast),
|
||||
.s_axis_tid (s_axis_write_data_tid),
|
||||
.s_axis_tdest (s_axis_write_data_tdest),
|
||||
.s_axis_tuser (s_axis_write_data_tuser),
|
||||
.s_axis_tvalid(s_axis_write_data_tvalid),
|
||||
.s_axis_tready(s_axis_write_data_tready),
|
||||
|
||||
.m_axis(dma_write_data)
|
||||
);
|
||||
|
||||
// AXI4 MASTER DMA
|
||||
|
||||
axi4_if #(
|
||||
.ADDR_W(dma_reg_pkg::AXI_ADDR_WIDTH),
|
||||
.DATA_W(AXI_DATA_WIDTH),
|
||||
.ID_W (AXI_ID_WIDTH),
|
||||
.USER_W(AXI_USER_WIDTH)
|
||||
) m_axi (
|
||||
.aclk(ctrl_clk),
|
||||
.aresetn(rst_n)
|
||||
);
|
||||
|
||||
logic [AXI_USER_WIDTH-1:0] unused_awuser;
|
||||
logic [AXI_USER_WIDTH-1:0] unused_wuser;
|
||||
logic [AXI_USER_WIDTH-1:0] unused_aruser;
|
||||
|
||||
axi4_if_to_flat #(
|
||||
.ADDR_W (dma_reg_pkg::AXI_ADDR_WIDTH),
|
||||
.DATA_W (AXI_DATA_WIDTH),
|
||||
.ID_W (AXI_ID_WIDTH),
|
||||
.USER_W (AXI_USER_WIDTH)
|
||||
) u_axi_if_to_flat (
|
||||
.s_axi(m_axi),
|
||||
|
||||
.m_axi_awid (m_axi_awid),
|
||||
.m_axi_awaddr (m_axi_awaddr),
|
||||
.m_axi_awlen (m_axi_awlen),
|
||||
.m_axi_awsize (m_axi_awsize),
|
||||
.m_axi_awburst (m_axi_awburst),
|
||||
.m_axi_awlock (m_axi_awlock),
|
||||
.m_axi_awcache (m_axi_awcache),
|
||||
.m_axi_awprot (m_axi_awprot),
|
||||
.m_axi_awqos (),
|
||||
.m_axi_awregion(),
|
||||
.m_axi_awuser (unused_awuser),
|
||||
.m_axi_awvalid (m_axi_awvalid),
|
||||
.m_axi_awready (m_axi_awready),
|
||||
|
||||
.m_axi_wdata (m_axi_wdata),
|
||||
.m_axi_wstrb (m_axi_wstrb),
|
||||
.m_axi_wlast (m_axi_wlast),
|
||||
.m_axi_wuser (unused_wuser),
|
||||
.m_axi_wvalid (m_axi_wvalid),
|
||||
.m_axi_wready (m_axi_wready),
|
||||
|
||||
.m_axi_bid (m_axi_bid),
|
||||
.m_axi_bresp (m_axi_bresp),
|
||||
.m_axi_buser ({AXI_USER_WIDTH{1'b0}}),
|
||||
.m_axi_bvalid (m_axi_bvalid),
|
||||
.m_axi_bready (m_axi_bready),
|
||||
|
||||
.m_axi_arid (m_axi_arid),
|
||||
.m_axi_araddr (m_axi_araddr),
|
||||
.m_axi_arlen (m_axi_arlen),
|
||||
.m_axi_arsize (m_axi_arsize),
|
||||
.m_axi_arburst (m_axi_arburst),
|
||||
.m_axi_arlock (m_axi_arlock),
|
||||
.m_axi_arcache (m_axi_arcache),
|
||||
.m_axi_arprot (m_axi_arprot),
|
||||
.m_axi_arqos (),
|
||||
.m_axi_arregion(),
|
||||
.m_axi_aruser (unused_aruser),
|
||||
.m_axi_arvalid (m_axi_arvalid),
|
||||
.m_axi_arready (m_axi_arready),
|
||||
|
||||
.m_axi_rid (m_axi_rid),
|
||||
.m_axi_rdata (m_axi_rdata),
|
||||
.m_axi_rresp (m_axi_rresp),
|
||||
.m_axi_rlast (m_axi_rlast),
|
||||
.m_axi_ruser ({AXI_USER_WIDTH{1'b0}}),
|
||||
.m_axi_rvalid (m_axi_rvalid),
|
||||
.m_axi_rready (m_axi_rready)
|
||||
);
|
||||
|
||||
|
||||
// Controller ADC/DAC outputs.
|
||||
logic [31:0] adc_window_size;
|
||||
logic [31:0] dac_pulse_width;
|
||||
logic [31:0] dac_pulse_period;
|
||||
logic [DAC_DATA_WIDTH-1:0] dac_pulse_height;
|
||||
logic [15:0] dac_pulse_num;
|
||||
logic [31:0] adc_pulse_period;
|
||||
logic [15:0] adc_pulse_num;
|
||||
logic dac_start;
|
||||
logic adc_start;
|
||||
logic dac_rst;
|
||||
logic adc_rst;
|
||||
|
||||
wrapper_controller_dma #(
|
||||
.ADDR_W(ADDR_W),
|
||||
.DATA_W(DATA_W),
|
||||
.USER_W(USER_W),
|
||||
.DAC_DATA_WIDTH(DAC_DATA_WIDTH),
|
||||
.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
|
||||
.AXI_ID_WIDTH(AXI_ID_WIDTH),
|
||||
.AXI_USER_WIDTH(AXI_USER_WIDTH),
|
||||
.AXI_MAX_BURST_LEN(AXI_MAX_BURST_LEN),
|
||||
.AXIS_LAST_ENABLE(AXIS_LAST_ENABLE),
|
||||
.AXIS_ID_ENABLE(AXIS_ID_ENABLE),
|
||||
.AXIS_DEST_ENABLE(AXIS_DEST_ENABLE),
|
||||
.AXIS_USER_ENABLE(AXIS_USER_ENABLE),
|
||||
.ENABLE_SG(ENABLE_SG),
|
||||
.ENABLE_UNALIGNED(ENABLE_UNALIGNED)
|
||||
) dut (
|
||||
.ctrl_clk(ctrl_clk),
|
||||
.dac_clk_in(dac_clk_in),
|
||||
.adc_clk_in(adc_clk_in),
|
||||
.rst_n(rst_n),
|
||||
.s_axil(axil_bus),
|
||||
|
||||
.finish(finish),
|
||||
.adc_window_size(adc_window_size),
|
||||
|
||||
.dac_pulse_width(dac_pulse_width),
|
||||
.dac_pulse_period(dac_pulse_period),
|
||||
.dac_pulse_height(dac_pulse_height),
|
||||
.dac_pulse_num(dac_pulse_num),
|
||||
|
||||
.adc_pulse_period(adc_pulse_period),
|
||||
.adc_pulse_num(adc_pulse_num),
|
||||
|
||||
.dac_start(dac_start),
|
||||
.adc_start(adc_start),
|
||||
.dac_rst(dac_rst),
|
||||
.adc_rst(adc_rst),
|
||||
|
||||
.m_axis_read_data(dma_read_data),
|
||||
.s_axis_write_data(dma_write_data),
|
||||
|
||||
.m_axi(m_axi)
|
||||
);
|
||||
|
||||
endmodule : tb_controller_wrapper_axil
|
||||
@ -0,0 +1,216 @@
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.handle import Immediate
|
||||
from cocotb.triggers import RisingEdge
|
||||
from cocotbext.axi import AxiLiteBus, AxiLiteMaster
|
||||
from cocotbext.axi import AxiBus, AxiRam, AxiStreamBus, AxiStreamSource, AxiStreamSink
|
||||
|
||||
|
||||
# Register indexes from axi4l_reg_map_controller_pkg.sv
|
||||
REG_CONTROL = 0
|
||||
REG_STATUS = 1
|
||||
REG_DAC_WIDTH = 2
|
||||
REG_DAC_PERIOD = 3
|
||||
REG_DAC_PULSE_NUM = 4
|
||||
REG_DAC_PULSE_HEIGHT = 5
|
||||
REG_ADC_PERIOD = 6
|
||||
REG_WINDOW_SIZE = 7
|
||||
REG_ERROR = 8
|
||||
REG_DESC_READ_ADDR = 9
|
||||
REG_DESC_READ_LEN = 10
|
||||
REG_DESC_READ_CONFIG = 11
|
||||
REG_READ_STATUS = 12
|
||||
REG_DESC_WRITE_ADDR = 13
|
||||
REG_DESC_WRITE_LEN_AND_TAG = 14
|
||||
REG_STATUS_WRITE_LEN = 15
|
||||
REG_STATUS_WRITE_CONFIG = 16
|
||||
|
||||
|
||||
# REG_CONTROL pulse bits
|
||||
CTRL_START = 0
|
||||
CTRL_RST_SOFT = 1
|
||||
CTRL_CFG_BUS_VALID = 2
|
||||
CTRL_SEND_DESC_READ = 3
|
||||
CTRL_SEND_DESC_WRITE = 4
|
||||
CTRL_TAKE_STATUS_READ = 5
|
||||
CTRL_TAKE_STATUS_WRITE = 6
|
||||
|
||||
|
||||
def reg_addr(reg_index: int) -> int:
|
||||
# AXI-Lite uses byte addresses, 32-bit registers are spaced by 4 bytes.
|
||||
return reg_index * 4
|
||||
|
||||
|
||||
def u32(value: int) -> bytes:
|
||||
return int(value & 0xFFFFFFFF).to_bytes(4, "little")
|
||||
|
||||
|
||||
class TB:
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
cocotb.start_soon(Clock(dut.ctrl_clk, 10, units="ns").start())
|
||||
|
||||
self.axil = AxiLiteMaster(
|
||||
AxiLiteBus.from_prefix(dut, "s_axil"),
|
||||
dut.ctrl_clk,
|
||||
dut.rst
|
||||
)
|
||||
|
||||
|
||||
self.axis_source = AxiStreamSource(
|
||||
AxiStreamBus.from_prefix(dut, "s_axis_write_data"),
|
||||
dut.ctrl_clk,
|
||||
dut.rst
|
||||
)
|
||||
|
||||
self.axis_sink = AxiStreamSink(
|
||||
AxiStreamBus.from_prefix(dut, "m_axis_read_data"),
|
||||
dut.ctrl_clk,
|
||||
dut.rst
|
||||
)
|
||||
|
||||
async def reset(self):
|
||||
self.dut.rst.value = 1
|
||||
for _ in range(5):
|
||||
await RisingEdge(self.dut.ctrl_clk)
|
||||
|
||||
self.dut.rst.value = 0
|
||||
for _ in range(5):
|
||||
await RisingEdge(self.dut.ctrl_clk)
|
||||
|
||||
async def write_reg(self, reg_index: int, value: int):
|
||||
await self.axil.write(reg_addr(reg_index), u32(value))
|
||||
|
||||
async def read_reg(self, reg_index: int) -> int:
|
||||
resp = await self.axil.read(reg_addr(reg_index), 4)
|
||||
return int.from_bytes(bytes(resp.data), "little")
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def simple_axil_write_read(dut):
|
||||
tb = TB(dut)
|
||||
await tb.reset()
|
||||
|
||||
await tb.write_reg(REG_DAC_WIDTH, 0x0000_0123)
|
||||
|
||||
value = await tb.read_reg(REG_DAC_WIDTH)
|
||||
assert value == 0x0000_0123
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def simple_controller_config_write(dut):
|
||||
tb = TB(dut)
|
||||
await tb.reset()
|
||||
|
||||
await tb.write_reg(REG_DAC_WIDTH, 0x10)
|
||||
await tb.write_reg(REG_DAC_PERIOD, 0x40)
|
||||
await tb.write_reg(REG_DAC_PULSE_NUM, 3)
|
||||
await tb.write_reg(REG_DAC_PULSE_HEIGHT, 0x7FF)
|
||||
await tb.write_reg(REG_ADC_PERIOD, 0x80)
|
||||
await tb.write_reg(REG_WINDOW_SIZE, 16)
|
||||
|
||||
assert await tb.read_reg(REG_DAC_WIDTH) == 0x10
|
||||
assert await tb.read_reg(REG_WINDOW_SIZE) == 16
|
||||
|
||||
# write data: set cfg_bus_valid signal
|
||||
await tb.write_reg(REG_CONTROL, 1 << CTRL_CFG_BUS_VALID)
|
||||
|
||||
# wait
|
||||
for _ in range(30):
|
||||
await RisingEdge(dut.ctrl_clk)
|
||||
|
||||
# check config
|
||||
assert int(dut.dac_pulse_width) == 0x10
|
||||
assert int(dut.dac_pulse_period) == 0x40
|
||||
assert int(dut.dac_pulse_num) == 3
|
||||
assert int(dut.dac_pulse_height) == 0x7FF
|
||||
assert int(dut.adc_pulse_period) == 0x80
|
||||
assert int(dut.adc_window_size) == 16
|
||||
|
||||
await RisingEdge(dut.ctrl_clk)
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def simple_controller_start_check(dut):
|
||||
tb = TB(dut)
|
||||
await tb.reset()
|
||||
await tb.write_reg(REG_CONTROL, 1 << CTRL_START)
|
||||
|
||||
await RisingEdge(dut.dac_start)
|
||||
|
||||
@cocotb.test()
|
||||
async def test_dma_write(dut):
|
||||
tb = TB(dut)
|
||||
await tb.reset()
|
||||
|
||||
data = bytes(range(64))
|
||||
|
||||
#write data into memory
|
||||
|
||||
await tb.write_reg(REG_DESC_WRITE_ADDR, 0x1000)
|
||||
await tb.write_reg(REG_DESC_WRITE_LEN_AND_TAG, 64)
|
||||
|
||||
|
||||
await tb.write_reg(REG_CONTROL, 1 << CTRL_SEND_DESC_WRITE)
|
||||
await RisingEdge(dut.ctrl_clk)
|
||||
cocotb.start_soon(tb.axis_source.send(data))
|
||||
|
||||
for _ in range(200):
|
||||
await tb.write_reg( REG_CONTROL, 1 << CTRL_TAKE_STATUS_WRITE)
|
||||
|
||||
await RisingEdge(dut.ctrl_clk)
|
||||
|
||||
status = await tb.read_reg( REG_STATUS_WRITE_LEN)
|
||||
if status == 64:
|
||||
break
|
||||
|
||||
else:
|
||||
assert False, "DMA timeout"
|
||||
|
||||
|
||||
mem = await tb.mem.read( 0x1000, 64)
|
||||
assert mem == data
|
||||
|
||||
@cocotb.test()
|
||||
async def test_dma_read(dut):
|
||||
tb = TB(dut)
|
||||
await tb.reset()
|
||||
|
||||
data = bytes(range(64))
|
||||
|
||||
#read data from memory
|
||||
|
||||
await tb.mem.write( 0x2000, data)
|
||||
|
||||
await tb.write_reg( REG_DESC_READ_ADDR, 0x2000)
|
||||
await tb.write_reg( REG_DESC_READ_LEN, 64)
|
||||
await tb.write_reg( REG_DESC_READ_CONFIG, 1)
|
||||
|
||||
await tb.write_reg( REG_CONTROL, 1 << CTRL_SEND_DESC_READ)
|
||||
|
||||
frame = await tb.axis_sink.recv()
|
||||
assert frame.data == data
|
||||
|
||||
await tb.write_reg(
|
||||
REG_CONTROL,
|
||||
1 << CTRL_TAKE_STATUS_READ
|
||||
)
|
||||
|
||||
for _ in range(100):
|
||||
|
||||
status = await tb.read_reg(
|
||||
REG_READ_STATUS
|
||||
)
|
||||
|
||||
if status != 0:
|
||||
break
|
||||
|
||||
await RisingEdge(dut.ctrl_clk)
|
||||
else:
|
||||
assert False, "DMA read status timeout"
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
13
designs/controller_dma_connective/tests/test_timing.xdc
Normal file
13
designs/controller_dma_connective/tests/test_timing.xdc
Normal file
@ -0,0 +1,13 @@
|
||||
# Primary clocks
|
||||
create_clock -name eth_clk -period 8.000 [get_ports eth_clk_in]
|
||||
create_clock -name dac_clk -period 7.692 [get_ports dac_clk_in]
|
||||
create_clock -name adc_clk -period 15.385 [get_ports adc_clk_in]
|
||||
|
||||
|
||||
# Asynchronous clock groups
|
||||
# eth, dac, adc are independent domains
|
||||
|
||||
set_clock_groups -name ASYNC_ETH_DAC_ADC -asynchronous \
|
||||
-group [get_clocks eth_clk] \
|
||||
-group [get_clocks dac_clk] \
|
||||
-group [get_clocks adc_clk]
|
||||
1
external/rtl_libs
vendored
Submodule
1
external/rtl_libs
vendored
Submodule
Submodule external/rtl_libs added at e4311214eb
122
rtl/controller/src/axi4l_reg_map_controller.sv
Normal file
122
rtl/controller/src/axi4l_reg_map_controller.sv
Normal file
@ -0,0 +1,122 @@
|
||||
module axi4l_reg_map_controller #(
|
||||
parameter int unsigned ADDR_W = 16,
|
||||
parameter int unsigned DATA_W = 32,
|
||||
parameter int unsigned USER_W = 1
|
||||
)(
|
||||
input logic clk,
|
||||
input logic rst_n,
|
||||
axi4l_if.slave s_axil,
|
||||
// dac adc registers
|
||||
output logic start_o,
|
||||
output logic cfg_bus_valid_o,
|
||||
output logic [31:0] pulse_width_o,
|
||||
output logic [31:0] pulse_period_o,
|
||||
output logic [31:0] pulse_num_o,
|
||||
output logic [31:0] pulse_height_raw_o,
|
||||
output logic [31:0] pulse_period_ADC_o,
|
||||
output logic [31:0] window_size_o,
|
||||
|
||||
// DMA CONTROL SIGNALS
|
||||
output logic send_desc_read_o,
|
||||
output logic send_desc_write_o,
|
||||
output logic take_status_read_o,
|
||||
output logic take_status_write_o,
|
||||
|
||||
input logic desc_read_dma_busy_i,
|
||||
input logic desc_write_dma_busy_i,
|
||||
input logic status_read_dma_busy_i,
|
||||
input logic status_write_dma_busy_i,
|
||||
|
||||
input logic desc_read_dma_hs_i,
|
||||
input logic desc_write_dma_hs_i,
|
||||
input logic status_read_dma_hs_i,
|
||||
input logic status_write_dma_hs_i,
|
||||
|
||||
// DMA read descriptors and status register
|
||||
|
||||
output logic [31:0] desc_read_addr_o,
|
||||
output logic [31:0] desc_read_len_o,
|
||||
output logic [31:0] desc_read_config_o,
|
||||
|
||||
input logic [31:0] status_read_i,
|
||||
|
||||
// DMA write descriptors and status register
|
||||
output logic [31:0] desc_write_addr_o,
|
||||
output logic [31:0] desc_write_len_and_tag_o,
|
||||
|
||||
input logic [31:0] status_write_len_i,
|
||||
input logic [31:0] status_write_config_i,
|
||||
|
||||
output logic rst_soft_o,
|
||||
input logic busy_i,
|
||||
input logic [7:0] error_code_i
|
||||
);
|
||||
import axi4l_reg_map_controller_pkg::*;
|
||||
localparam int unsigned N_REGS = CTRL_REG_MAP_N_REGS;
|
||||
|
||||
logic [N_REGS-1:0][31:0] reg_i;
|
||||
logic [N_REGS-1:0][31:0] reg_o;
|
||||
logic [N_REGS-1:0][31:0] reg_pulse;
|
||||
|
||||
axi4l_reg_map #(
|
||||
.ADDR_W (ADDR_W),
|
||||
.DATA_W (DATA_W),
|
||||
.USER_W (USER_W),
|
||||
.N_REGS (N_REGS),
|
||||
.REG_MODE (CTRL_REG_MAP_REG_MODE),
|
||||
.REG_RST (CTRL_REG_MAP_REG_RST)
|
||||
) u_reg_map (
|
||||
.clk (clk),
|
||||
.rst_n (rst_n),
|
||||
.s_axil (s_axil),
|
||||
.reg_i (reg_i),
|
||||
.reg_o (reg_o),
|
||||
.reg_pulse(reg_pulse)
|
||||
);
|
||||
|
||||
always_comb begin
|
||||
reg_i = '0;
|
||||
|
||||
reg_i[REG_STATUS][0] = busy_i;
|
||||
|
||||
reg_i[REG_STATUS][1] = desc_read_dma_busy_i;
|
||||
reg_i[REG_STATUS][2] = desc_write_dma_busy_i;
|
||||
reg_i[REG_STATUS][3] = status_read_dma_busy_i;
|
||||
reg_i[REG_STATUS][4] = status_write_dma_busy_i;
|
||||
|
||||
reg_i[REG_STATUS][5] = desc_read_dma_hs_i;
|
||||
reg_i[REG_STATUS][6] = desc_write_dma_hs_i;
|
||||
reg_i[REG_STATUS][7] = status_read_dma_hs_i;
|
||||
reg_i[REG_STATUS][8] = status_write_dma_hs_i;
|
||||
|
||||
reg_i[REG_ERROR][7:0] = error_code_i;
|
||||
|
||||
reg_i[REG_READ_STATUS] = status_read_i;
|
||||
reg_i[REG_STATUS_WRITE_LEN] = status_write_len_i;
|
||||
reg_i[REG_STATUS_WRITE_CONFIG] = status_write_config_i;
|
||||
|
||||
end
|
||||
|
||||
assign start_o = reg_pulse[REG_CONTROL][0];
|
||||
assign rst_soft_o = reg_pulse[REG_CONTROL][1];
|
||||
assign cfg_bus_valid_o = reg_pulse[REG_CONTROL][2];
|
||||
|
||||
assign send_desc_read_o = reg_pulse[REG_CONTROL][3];
|
||||
assign send_desc_write_o = reg_pulse[REG_CONTROL][4];
|
||||
assign take_status_read_o = reg_pulse[REG_CONTROL][5];
|
||||
assign take_status_write_o = reg_pulse[REG_CONTROL][6];
|
||||
|
||||
assign pulse_width_o = reg_o[REG_DAC_WIDTH];
|
||||
assign pulse_period_o = reg_o[REG_DAC_PERIOD];
|
||||
assign pulse_num_o = reg_o[REG_DAC_PULSE_NUM];
|
||||
assign pulse_height_raw_o = reg_o[REG_DAC_PULSE_HEIGHT];
|
||||
assign pulse_period_ADC_o = reg_o[REG_ADC_PERIOD];
|
||||
assign window_size_o = reg_o[REG_WINDOW_SIZE];
|
||||
|
||||
assign desc_read_addr_o = reg_o[REG_DESC_READ_ADDR];
|
||||
assign desc_read_len_o = reg_o[REG_DESC_READ_LEN];
|
||||
assign desc_read_config_o = reg_o[REG_DESC_READ_CONFIG];
|
||||
assign desc_write_addr_o = reg_o[REG_DESC_WRITE_ADDR];
|
||||
assign desc_write_len_and_tag_o = reg_o[REG_DESC_WRITE_LEN_AND_TAG];
|
||||
|
||||
endmodule
|
||||
109
rtl/controller/src/axi4l_reg_map_controller_pkg.sv
Normal file
109
rtl/controller/src/axi4l_reg_map_controller_pkg.sv
Normal file
@ -0,0 +1,109 @@
|
||||
package axi4l_reg_map_controller_pkg;
|
||||
|
||||
localparam int unsigned CTRL_REG_MAP_N_REGS = 17;
|
||||
|
||||
/*
|
||||
dac adc configuration registers
|
||||
*/
|
||||
localparam logic [31:0] REG_CONTROL = 32'd0;
|
||||
localparam logic [31:0] REG_STATUS = 32'd1;
|
||||
localparam logic [31:0] REG_DAC_WIDTH = 32'd2;
|
||||
localparam logic [31:0] REG_DAC_PERIOD = 32'd3;
|
||||
localparam logic [31:0] REG_DAC_PULSE_NUM = 32'd4;
|
||||
localparam logic [31:0] REG_DAC_PULSE_HEIGHT = 32'd5;
|
||||
localparam logic [31:0] REG_ADC_PERIOD = 32'd6;
|
||||
localparam logic [31:0] REG_WINDOW_SIZE = 32'd7;
|
||||
localparam logic [31:0] REG_ERROR = 32'd8;
|
||||
|
||||
/*
|
||||
AXI read descriptor input and AXI read descriptor status output configuration registers
|
||||
*/
|
||||
localparam logic [31:0] REG_DESC_READ_ADDR = 32'd9;
|
||||
localparam logic [31:0] REG_DESC_READ_LEN = 32'd10;
|
||||
localparam logic [31:0] REG_DESC_READ_CONFIG = 32'd11;
|
||||
|
||||
localparam logic [31:0] REG_READ_STATUS = 32'd12;
|
||||
|
||||
/*
|
||||
AXI write descriptor input and AXI write descriptor status output configuration registers
|
||||
*/
|
||||
localparam logic [31:0] REG_DESC_WRITE_ADDR = 32'd13;
|
||||
localparam logic [31:0] REG_DESC_WRITE_LEN_AND_TAG = 32'd14;
|
||||
|
||||
localparam logic [31:0] REG_STATUS_WRITE_LEN = 32'd15;
|
||||
localparam logic [31:0] REG_STATUS_WRITE_CONFIG = 32'd16;
|
||||
|
||||
|
||||
localparam logic [2:0] REG_BIT_RSVD = 3'd0;
|
||||
localparam logic [2:0] REG_BIT_RO = 3'd1;
|
||||
localparam logic [2:0] REG_BIT_RW = 3'd2;
|
||||
localparam logic [2:0] REG_BIT_W1S = 3'd3;
|
||||
|
||||
localparam logic [CTRL_REG_MAP_N_REGS-1:0][31:0][2:0] CTRL_REG_MAP_REG_MODE = '{
|
||||
default: '{default: REG_BIT_RSVD},
|
||||
|
||||
REG_CONTROL: '{
|
||||
0 : REG_BIT_W1S,
|
||||
1 : REG_BIT_W1S,
|
||||
2 : REG_BIT_W1S,
|
||||
3 : REG_BIT_W1S,
|
||||
4 : REG_BIT_W1S,
|
||||
5 : REG_BIT_W1S,
|
||||
6 : REG_BIT_W1S,
|
||||
default: REG_BIT_RSVD
|
||||
},
|
||||
|
||||
REG_STATUS: '{
|
||||
0 : REG_BIT_RO,
|
||||
1 : REG_BIT_RO,
|
||||
2 : REG_BIT_RO,
|
||||
3 : REG_BIT_RO,
|
||||
4 : REG_BIT_RO,
|
||||
5 : REG_BIT_RO,
|
||||
6 : REG_BIT_RO,
|
||||
7 : REG_BIT_RO,
|
||||
8 : REG_BIT_RO,
|
||||
default: REG_BIT_RSVD
|
||||
},
|
||||
|
||||
REG_DAC_WIDTH: '{default: REG_BIT_RW},
|
||||
REG_DAC_PERIOD: '{default: REG_BIT_RW},
|
||||
REG_DAC_PULSE_NUM: '{default: REG_BIT_RW},
|
||||
REG_DAC_PULSE_HEIGHT: '{default: REG_BIT_RW},
|
||||
REG_ADC_PERIOD: '{default: REG_BIT_RW},
|
||||
REG_WINDOW_SIZE: '{default: REG_BIT_RW},
|
||||
|
||||
REG_ERROR: '{default: REG_BIT_RO},
|
||||
|
||||
REG_DESC_READ_ADDR: '{default: REG_BIT_RW},
|
||||
REG_DESC_READ_LEN: '{default: REG_BIT_RW},
|
||||
REG_DESC_READ_CONFIG: '{default: REG_BIT_RW},
|
||||
REG_READ_STATUS: '{default: REG_BIT_RO},
|
||||
|
||||
REG_DESC_WRITE_ADDR: '{default: REG_BIT_RW},
|
||||
REG_DESC_WRITE_LEN_AND_TAG: '{default: REG_BIT_RW},
|
||||
REG_STATUS_WRITE_LEN: '{default: REG_BIT_RO},
|
||||
REG_STATUS_WRITE_CONFIG: '{default: REG_BIT_RO}
|
||||
};
|
||||
|
||||
localparam logic [CTRL_REG_MAP_N_REGS-1:0][31:0] CTRL_REG_MAP_REG_RST = '{
|
||||
32'h0000_0000,
|
||||
32'h0000_0000,
|
||||
32'h0000_0000,
|
||||
32'h0000_0000,
|
||||
32'h0000_0000,
|
||||
32'h0000_0000,
|
||||
32'h0000_0000,
|
||||
32'h0000_0000,
|
||||
32'h0000_0000,
|
||||
32'h0000_0000,
|
||||
32'h0000_0000,
|
||||
32'h0000_0000,
|
||||
32'h0000_0000,
|
||||
32'h0000_0000,
|
||||
32'h0000_0000,
|
||||
32'h0000_0000,
|
||||
32'h0000_0000
|
||||
};
|
||||
|
||||
endpackage
|
||||
13
rtl/controller/src/axis_defaults_helper.sv
Normal file
13
rtl/controller/src/axis_defaults_helper.sv
Normal file
@ -0,0 +1,13 @@
|
||||
module axis_defaults_master
|
||||
(
|
||||
axis_if.master axis
|
||||
);
|
||||
|
||||
assign axis.req.t.keep = '1;
|
||||
assign axis.req.t.strb = '1;
|
||||
assign axis.req.t.last = 1'b1;
|
||||
assign axis.req.t.id = '0;
|
||||
assign axis.req.t.dest = '0;
|
||||
assign axis.req.t.user = '0;
|
||||
|
||||
endmodule
|
||||
@ -1,19 +1,21 @@
|
||||
module control #(
|
||||
parameter int unsigned DAC_DATA_WIDTH = 12
|
||||
) (
|
||||
input logic eth_clk_in,
|
||||
input logic ctrl_clk,
|
||||
input logic dac_clk_in,
|
||||
input logic adc_clk_in,
|
||||
input logic rst_n,
|
||||
|
||||
// AXI stream slave, eth_clk_in domain
|
||||
input logic [7:0] s_axis_tdata,
|
||||
input logic s_axis_tvalid,
|
||||
output logic s_axis_tready,
|
||||
input logic s_axis_tlast,
|
||||
input logic rst_n,
|
||||
input logic rst_soft,
|
||||
|
||||
// adc_clk_in domain
|
||||
input logic finish,
|
||||
input logic [159:0] cfg_bus_input,
|
||||
input logic cfg_bus_valid,
|
||||
input logic start,
|
||||
|
||||
// status signals
|
||||
output logic busy,
|
||||
|
||||
// dac_clk_in domain outputs
|
||||
output logic [31:0] dac_pulse_width,
|
||||
@ -24,6 +26,7 @@ module control #(
|
||||
// adc_clk_in domain outputs
|
||||
output logic [31:0] adc_pulse_period,
|
||||
output logic [15:0] adc_pulse_num,
|
||||
output logic [31:0] adc_window_size,
|
||||
|
||||
// pulse outputs
|
||||
output logic dac_start,
|
||||
@ -42,27 +45,22 @@ module control #(
|
||||
end
|
||||
end
|
||||
|
||||
// command constants
|
||||
localparam logic [7:0] CMD_SOFT_RESET = 8'h0F;
|
||||
localparam logic [7:0] CMD_START = 8'hF0;
|
||||
localparam logic [7:0] CMD_SET_DATA = 8'h88;
|
||||
|
||||
// reset synchronizers: async assert, sync deassert in each domain
|
||||
logic eth_rst_ff1, eth_rst_ff2;
|
||||
logic rst_ff1, rst_ff2;
|
||||
logic dac_rst_ff1, dac_rst_ff2;
|
||||
logic adc_rst_ff1, adc_rst_ff2;
|
||||
|
||||
logic eth_rst;
|
||||
logic ctrl_rst;
|
||||
logic dac_rst_int;
|
||||
logic adc_rst_int;
|
||||
|
||||
always_ff @(posedge eth_clk_in or negedge rst_n) begin
|
||||
always_ff @(posedge ctrl_clk or negedge rst_n) begin
|
||||
if (!rst_n) begin
|
||||
eth_rst_ff1 <= 1'b1;
|
||||
eth_rst_ff2 <= 1'b1;
|
||||
rst_ff1 <= 1'b1;
|
||||
rst_ff2 <= 1'b1;
|
||||
end else begin
|
||||
eth_rst_ff1 <= 1'b0;
|
||||
eth_rst_ff2 <= eth_rst_ff1;
|
||||
rst_ff1 <= 1'b0;
|
||||
rst_ff2 <= rst_ff1;
|
||||
end
|
||||
end
|
||||
|
||||
@ -86,74 +84,34 @@ module control #(
|
||||
end
|
||||
end
|
||||
|
||||
assign eth_rst = eth_rst_ff2;
|
||||
assign ctrl_rst = rst_ff2;
|
||||
assign dac_rst_int = dac_rst_ff2;
|
||||
assign adc_rst_int = adc_rst_ff2;
|
||||
|
||||
// axi stream is always accepted. If packet is not needed, it is discarded.
|
||||
assign s_axis_tready = 1'b1;
|
||||
|
||||
(* MARK_DEBUG="true" *) wire axis_hs = s_axis_tvalid & s_axis_tready;
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// Shared 96-bit config bus in ETH domain
|
||||
//
|
||||
// Byte order for SET_DATA payload, little-endian:
|
||||
// payload byte 0 -> cfg_bus_eth[7:0]
|
||||
// payload byte 1 -> cfg_bus_eth[15:8]
|
||||
// ...etc...
|
||||
// payload byte 11 -> cfg_bus_eth[95:88]
|
||||
//
|
||||
// Field layout inside cfg_bus_eth:
|
||||
// [31:0] pulse_width
|
||||
// [63:32] pulse_period
|
||||
// [79:64] pulse_num
|
||||
// [95:80] pulse_height_raw[15:0]
|
||||
// [127:96] pulse_period_ADC
|
||||
//
|
||||
// -------------------------------------------------------------------------
|
||||
(* MARK_DEBUG="true" *) logic [127:0] cfg_bus_eth;
|
||||
logic [127:0] cfg_shift_eth;
|
||||
|
||||
// ETH-domain parser and control
|
||||
typedef enum logic [2:0] {
|
||||
ST_IDLE = 3'd0,
|
||||
ST_RECV_CFG = 3'd1,
|
||||
ST_WAIT_CFG_ACK = 3'd2,
|
||||
ST_DISCARD = 3'd3
|
||||
} eth_state_t;
|
||||
|
||||
(* MARK_DEBUG="true" *) eth_state_t eth_state;
|
||||
|
||||
logic [3:0] cfg_byte_cnt;
|
||||
|
||||
// Busy flag: set by START command, cleared by finish event from ADC domain
|
||||
(* MARK_DEBUG="true" *) logic busy_flag_eth;
|
||||
|
||||
// Pending ACKs for config delivery
|
||||
logic cfg_wait_dac_ack;
|
||||
logic cfg_wait_adc_ack;
|
||||
|
||||
// Event toggles ETH -> DAC/ADC
|
||||
logic start_toggle_eth;
|
||||
logic rst_toggle_eth;
|
||||
// Event toggles cntrl -> DAC/ADC
|
||||
logic start_toggle;
|
||||
logic rst_toggle;
|
||||
|
||||
// Config request toggles ETH -> DAC/ADC
|
||||
logic cfg_req_toggle_dac_eth;
|
||||
logic cfg_req_toggle_adc_eth;
|
||||
// Config request toggles cntrl -> DAC/ADC
|
||||
logic cfg_req_toggle_dac;
|
||||
logic cfg_req_toggle_adc;
|
||||
|
||||
// ACK toggles DAC/ADC -> ETH
|
||||
// ACK toggles DAC/ADC -> cntrl
|
||||
logic cfg_ack_toggle_dac;
|
||||
logic cfg_ack_toggle_adc;
|
||||
|
||||
(* ASYNC_REG = "TRUE" *) logic cfg_ack_toggle_dac_meta, cfg_ack_toggle_dac_sync, cfg_ack_toggle_dac_sync_d;
|
||||
(* ASYNC_REG = "TRUE" *) logic cfg_ack_toggle_adc_meta, cfg_ack_toggle_adc_sync, cfg_ack_toggle_adc_sync_d;
|
||||
|
||||
wire cfg_ack_pulse_dac_eth = cfg_ack_toggle_dac_sync ^ cfg_ack_toggle_dac_sync_d;
|
||||
wire cfg_ack_pulse_adc_eth = cfg_ack_toggle_adc_sync ^ cfg_ack_toggle_adc_sync_d;
|
||||
wire cfg_ack_pulse_dac = cfg_ack_toggle_dac_sync ^ cfg_ack_toggle_dac_sync_d;
|
||||
wire cfg_ack_pulse_adc = cfg_ack_toggle_adc_sync ^ cfg_ack_toggle_adc_sync_d;
|
||||
|
||||
always_ff @(posedge eth_clk_in or posedge eth_rst) begin
|
||||
if (eth_rst) begin
|
||||
always_ff @(posedge ctrl_clk or posedge ctrl_rst) begin
|
||||
if (ctrl_rst) begin
|
||||
cfg_ack_toggle_dac_meta <= 1'b0;
|
||||
cfg_ack_toggle_dac_sync <= 1'b0;
|
||||
cfg_ack_toggle_dac_sync_d <= 1'b0;
|
||||
@ -172,11 +130,11 @@ module control #(
|
||||
end
|
||||
end
|
||||
|
||||
// finish event: ADC -> ETH via toggle CDC
|
||||
// finish event: ADC -> cntrl via toggle CDC
|
||||
logic finish_toggle_adc;
|
||||
logic finish_meta_eth, finish_sync_eth, finish_sync_eth_d;
|
||||
logic finish_meta, finish_sync, finish_sync_d;
|
||||
|
||||
wire finish_pulse_eth = finish_sync_eth ^ finish_sync_eth_d;
|
||||
wire finish_pulse = finish_sync ^ finish_sync_d;
|
||||
|
||||
always_ff @(posedge adc_clk_in or posedge adc_rst_int) begin
|
||||
if (adc_rst_int) begin
|
||||
@ -186,152 +144,66 @@ module control #(
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge eth_clk_in or posedge eth_rst) begin
|
||||
if (eth_rst) begin
|
||||
finish_meta_eth <= 1'b0;
|
||||
finish_sync_eth <= 1'b0;
|
||||
finish_sync_eth_d <= 1'b0;
|
||||
always_ff @(posedge ctrl_clk or posedge ctrl_rst) begin
|
||||
if (ctrl_rst) begin
|
||||
finish_meta <= 1'b0;
|
||||
finish_sync <= 1'b0;
|
||||
finish_sync_d <= 1'b0;
|
||||
end else begin
|
||||
finish_meta_eth <= finish_toggle_adc;
|
||||
finish_sync_eth <= finish_meta_eth;
|
||||
finish_sync_eth_d <= finish_sync_eth;
|
||||
finish_meta <= finish_toggle_adc;
|
||||
finish_sync <= finish_meta;
|
||||
finish_sync_d <= finish_sync;
|
||||
end
|
||||
end
|
||||
|
||||
// ETH FSM
|
||||
always_ff @(posedge eth_clk_in or posedge eth_rst) begin
|
||||
if (eth_rst) begin
|
||||
eth_state <= ST_IDLE;
|
||||
cfg_byte_cnt <= '0;
|
||||
cfg_shift_eth <= '0;
|
||||
cfg_bus_eth <= '0;
|
||||
logic [159:0] cfg_bus;
|
||||
|
||||
busy_flag_eth <= 1'b0;
|
||||
always_ff @(posedge ctrl_clk or posedge ctrl_rst) begin
|
||||
if (ctrl_rst) begin
|
||||
cfg_bus <= '0;
|
||||
busy <= 0;
|
||||
|
||||
start_toggle_eth <= 1'b0;
|
||||
rst_toggle_eth <= 1'b0;
|
||||
start_toggle <= 0;
|
||||
rst_toggle <= 0;
|
||||
|
||||
cfg_req_toggle_dac_eth <= 1'b0;
|
||||
cfg_req_toggle_adc_eth <= 1'b0;
|
||||
cfg_req_toggle_dac <= 0;
|
||||
cfg_req_toggle_adc <= 0;
|
||||
|
||||
cfg_wait_dac_ack <= 1'b0;
|
||||
cfg_wait_adc_ack <= 1'b0;
|
||||
cfg_wait_dac_ack <= 0;
|
||||
cfg_wait_adc_ack <= 0;
|
||||
end else begin
|
||||
// finish always clears busy
|
||||
if (finish_pulse_eth) begin
|
||||
busy_flag_eth <= 1'b0;
|
||||
if (finish_pulse) begin
|
||||
busy <= 0;
|
||||
end
|
||||
|
||||
// config acks
|
||||
if (cfg_ack_pulse_dac_eth) begin
|
||||
if (cfg_ack_pulse_dac) begin
|
||||
cfg_wait_dac_ack <= 1'b0;
|
||||
end
|
||||
if (cfg_ack_pulse_adc_eth) begin
|
||||
if (cfg_ack_pulse_adc) begin
|
||||
cfg_wait_adc_ack <= 1'b0;
|
||||
end
|
||||
|
||||
case (eth_state)
|
||||
ST_IDLE: begin
|
||||
cfg_byte_cnt <= '0;
|
||||
cfg_shift_eth <= cfg_shift_eth;
|
||||
if (cfg_bus_valid && !busy && !cfg_wait_dac_ack && !cfg_wait_adc_ack) begin
|
||||
cfg_bus <= cfg_bus_input;
|
||||
|
||||
if (axis_hs) begin
|
||||
// if busy, drop the whole packet
|
||||
if (busy_flag_eth) begin
|
||||
if (!s_axis_tlast) begin
|
||||
eth_state <= ST_DISCARD;
|
||||
end
|
||||
end else begin
|
||||
unique case (s_axis_tdata)
|
||||
CMD_SOFT_RESET: begin
|
||||
rst_toggle_eth <= ~rst_toggle_eth;
|
||||
end
|
||||
cfg_req_toggle_dac <= ~cfg_req_toggle_dac;
|
||||
cfg_req_toggle_adc <= ~cfg_req_toggle_adc;
|
||||
|
||||
CMD_START: begin
|
||||
start_toggle_eth <= ~start_toggle_eth;
|
||||
busy_flag_eth <= 1'b1;
|
||||
end
|
||||
cfg_wait_dac_ack <= 1;
|
||||
cfg_wait_adc_ack <= 1;
|
||||
end
|
||||
|
||||
CMD_SET_DATA: begin
|
||||
// expect exactly 12 bytes after command
|
||||
if (s_axis_tlast) begin
|
||||
// no payload, invalid packet
|
||||
eth_state <= ST_IDLE;
|
||||
end else begin
|
||||
cfg_byte_cnt <= 4'd0;
|
||||
cfg_shift_eth <= '0;
|
||||
eth_state <= ST_RECV_CFG;
|
||||
end
|
||||
end
|
||||
|
||||
default: begin
|
||||
// unknown command: discard packet remainder if any
|
||||
if (!s_axis_tlast) begin
|
||||
eth_state <= ST_DISCARD;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
ST_RECV_CFG: begin
|
||||
if (axis_hs) begin
|
||||
// little endian packing
|
||||
cfg_shift_eth[cfg_byte_cnt*8 +: 8] <= s_axis_tdata;
|
||||
|
||||
if (cfg_byte_cnt == 4'd15) begin
|
||||
// this must be the final payload byte
|
||||
if (s_axis_tlast) begin
|
||||
cfg_bus_eth <= {s_axis_tdata, cfg_shift_eth[119:0]};
|
||||
cfg_req_toggle_dac_eth <= ~cfg_req_toggle_dac_eth;
|
||||
cfg_req_toggle_adc_eth <= ~cfg_req_toggle_adc_eth;
|
||||
cfg_wait_dac_ack <= 1'b1;
|
||||
cfg_wait_adc_ack <= 1'b1;
|
||||
eth_state <= ST_WAIT_CFG_ACK;
|
||||
end else begin
|
||||
// too many bytes in packet
|
||||
eth_state <= ST_DISCARD;
|
||||
end
|
||||
end else begin
|
||||
// early tlast means packet too short!!
|
||||
if (s_axis_tlast) begin
|
||||
eth_state <= ST_IDLE;
|
||||
end else begin
|
||||
cfg_byte_cnt <= cfg_byte_cnt + 4'd1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
ST_WAIT_CFG_ACK: begin
|
||||
// any incoming packet while waiting ack is discarded
|
||||
if (cfg_ack_pulse_dac_eth || cfg_ack_pulse_adc_eth) begin
|
||||
if ((~cfg_wait_dac_ack || cfg_ack_pulse_dac_eth) &&
|
||||
(~cfg_wait_adc_ack || cfg_ack_pulse_adc_eth)) begin
|
||||
eth_state <= ST_IDLE;
|
||||
end
|
||||
end
|
||||
|
||||
if (axis_hs && !s_axis_tlast) begin
|
||||
eth_state <= ST_DISCARD;
|
||||
end
|
||||
end
|
||||
|
||||
ST_DISCARD: begin
|
||||
if (axis_hs && s_axis_tlast) begin
|
||||
eth_state <= ST_IDLE;
|
||||
end
|
||||
end
|
||||
|
||||
default: begin
|
||||
eth_state <= ST_IDLE;
|
||||
end
|
||||
endcase
|
||||
if (start && !busy && !cfg_wait_dac_ack && !cfg_wait_adc_ack) begin
|
||||
start_toggle <= ~start_toggle;
|
||||
busy <= 1;
|
||||
end
|
||||
if (rst_soft) begin
|
||||
rst_toggle <= ~rst_toggle;
|
||||
end
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
// ETH -> DAC: start/reset event sync
|
||||
// cntrl -> DAC: start/reset event sync
|
||||
(* ASYNC_REG = "TRUE" *) logic start_meta_dac, start_sync_dac;
|
||||
logic start_sync_dac_d;
|
||||
(* ASYNC_REG = "TRUE" *) logic rst_meta_dac, rst_sync_dac;
|
||||
@ -353,11 +225,11 @@ module control #(
|
||||
dac_start <= 1'b0;
|
||||
dac_rst <= 1'b0;
|
||||
end else begin
|
||||
start_meta_dac <= start_toggle_eth;
|
||||
start_meta_dac <= start_toggle;
|
||||
start_sync_dac <= start_meta_dac;
|
||||
start_sync_dac_d <= start_sync_dac;
|
||||
|
||||
rst_meta_dac <= rst_toggle_eth;
|
||||
rst_meta_dac <= rst_toggle;
|
||||
rst_sync_dac <= rst_meta_dac;
|
||||
rst_sync_dac_d <= rst_sync_dac;
|
||||
|
||||
@ -366,7 +238,7 @@ module control #(
|
||||
end
|
||||
end
|
||||
|
||||
// ETH -> ADC: start/reset event sync
|
||||
// cntrl -> ADC: start/reset event sync
|
||||
(* ASYNC_REG = "TRUE" *) logic start_meta_adc, start_sync_adc;
|
||||
logic start_sync_adc_d;
|
||||
(* ASYNC_REG = "TRUE" *) logic rst_meta_adc, rst_sync_adc;
|
||||
@ -388,11 +260,11 @@ module control #(
|
||||
adc_start <= 1'b0;
|
||||
adc_rst <= 1'b0;
|
||||
end else begin
|
||||
start_meta_adc <= start_toggle_eth;
|
||||
start_meta_adc <= start_toggle;
|
||||
start_sync_adc <= start_meta_adc;
|
||||
start_sync_adc_d <= start_sync_adc;
|
||||
|
||||
rst_meta_adc <= rst_toggle_eth;
|
||||
rst_meta_adc <= rst_toggle;
|
||||
rst_sync_adc <= rst_meta_adc;
|
||||
rst_sync_adc_d <= rst_sync_adc;
|
||||
|
||||
@ -401,8 +273,8 @@ module control #(
|
||||
end
|
||||
end
|
||||
|
||||
// ETH -> DAC config CDC
|
||||
// cfg_bus_eth is kept stable in ETH domain until DAC and ADC both ACK.
|
||||
// contrl -> DAC config CDC
|
||||
// cfg_bus is kept stable in contrl domain until DAC and ADC both ACK.
|
||||
(* ASYNC_REG = "TRUE" *) logic cfg_req_meta_dac, cfg_req_sync_dac;
|
||||
logic cfg_req_sync_dac_d;
|
||||
wire cfg_req_pulse_dac = cfg_req_sync_dac ^ cfg_req_sync_dac_d;
|
||||
@ -419,22 +291,22 @@ module control #(
|
||||
dac_pulse_num <= '0;
|
||||
dac_pulse_height <= '0;
|
||||
end else begin
|
||||
cfg_req_meta_dac <= cfg_req_toggle_dac_eth;
|
||||
cfg_req_meta_dac <= cfg_req_toggle_dac;
|
||||
cfg_req_sync_dac <= cfg_req_meta_dac;
|
||||
cfg_req_sync_dac_d <= cfg_req_sync_dac;
|
||||
|
||||
if (cfg_req_pulse_dac) begin
|
||||
dac_pulse_width <= cfg_bus_eth[31:0];
|
||||
dac_pulse_period <= cfg_bus_eth[63:32];
|
||||
dac_pulse_num <= cfg_bus_eth[79:64];
|
||||
dac_pulse_height <= cfg_bus_eth[80 +: DAC_DATA_WIDTH];
|
||||
dac_pulse_width <= cfg_bus[31:0];
|
||||
dac_pulse_period <= cfg_bus[63:32];
|
||||
dac_pulse_num <= cfg_bus[79:64];
|
||||
dac_pulse_height <= cfg_bus[80 +: DAC_DATA_WIDTH];
|
||||
|
||||
cfg_ack_toggle_dac <= ~cfg_ack_toggle_dac;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// ETH -> ADC config CDC
|
||||
// cntrl -> ADC config CDC
|
||||
logic cfg_req_meta_adc, cfg_req_sync_adc, cfg_req_sync_adc_d;
|
||||
wire cfg_req_pulse_adc = cfg_req_sync_adc ^ cfg_req_sync_adc_d;
|
||||
|
||||
@ -445,16 +317,18 @@ module control #(
|
||||
cfg_req_sync_adc_d <= 1'b0;
|
||||
cfg_ack_toggle_adc <= 1'b0;
|
||||
|
||||
adc_pulse_period <= '0;
|
||||
adc_pulse_num <= '0;
|
||||
adc_pulse_period <= '0;
|
||||
adc_pulse_num <= '0;
|
||||
adc_window_size <= '0;
|
||||
end else begin
|
||||
cfg_req_meta_adc <= cfg_req_toggle_adc_eth;
|
||||
cfg_req_meta_adc <= cfg_req_toggle_adc;
|
||||
cfg_req_sync_adc <= cfg_req_meta_adc;
|
||||
cfg_req_sync_adc_d <= cfg_req_sync_adc;
|
||||
|
||||
if (cfg_req_pulse_adc) begin
|
||||
adc_pulse_period <= cfg_bus_eth[127:96];
|
||||
adc_pulse_num <= cfg_bus_eth[79:64];
|
||||
adc_pulse_period <= cfg_bus[127:96];
|
||||
adc_pulse_num <= cfg_bus[79:64];
|
||||
adc_window_size <= cfg_bus[159:128];
|
||||
|
||||
cfg_ack_toggle_adc <= ~cfg_ack_toggle_adc;
|
||||
end
|
||||
|
||||
221
rtl/controller/src/controller_wrapper_axil.sv
Normal file
221
rtl/controller/src/controller_wrapper_axil.sv
Normal file
@ -0,0 +1,221 @@
|
||||
import dma_reg_pkg::*;
|
||||
|
||||
module controller_wrapper_axil #(
|
||||
|
||||
parameter int unsigned ADDR_W = 16,
|
||||
parameter int unsigned DATA_W = 32,
|
||||
parameter int unsigned USER_W = 1,
|
||||
|
||||
parameter int unsigned DAC_DATA_WIDTH = 12
|
||||
)
|
||||
(
|
||||
input logic ctrl_clk,
|
||||
input logic dac_clk_in,
|
||||
input logic adc_clk_in,
|
||||
input logic rst_n,
|
||||
axi4l_if.slave s_axil,
|
||||
|
||||
// adc_clk_in domain
|
||||
input logic finish,
|
||||
output logic [31:0] adc_window_size,
|
||||
|
||||
// dac_clk_in domain outputs
|
||||
output logic [31:0] dac_pulse_width,
|
||||
output logic [31:0] dac_pulse_period,
|
||||
output logic [DAC_DATA_WIDTH-1:0] dac_pulse_height,
|
||||
output logic [15:0] dac_pulse_num,
|
||||
|
||||
// adc_clk_in domain outputs
|
||||
output logic [31:0] adc_pulse_period,
|
||||
output logic [15:0] adc_pulse_num,
|
||||
|
||||
// pulse outputs
|
||||
output logic dac_start,
|
||||
output logic adc_start,
|
||||
output logic dac_rst,
|
||||
output logic adc_rst,
|
||||
|
||||
// AXIS DMA
|
||||
axis_if.slave s_axis_status_read,
|
||||
axis_if.slave s_axis_status_write,
|
||||
|
||||
axis_if.master m_axis_desc_read,
|
||||
axis_if.master m_axis_desc_write
|
||||
);
|
||||
|
||||
logic start, rst_soft, send_desc_read, send_desc_write, take_status_read, take_status_write, cfg_bus_valid, busy;
|
||||
logic [31:0] pulse_width, pulse_period, pulse_num, pulse_height_raw, pulse_period_ADC, window_size;
|
||||
logic [7:0] error_code;
|
||||
logic [31:0] desc_read_addr, desc_read_len, desc_read_config, status_read;
|
||||
logic [31:0] desc_write_addr, desc_write_len_and_tag, status_write_len, status_write_config;
|
||||
|
||||
logic desc_read_dma_busy, desc_write_dma_busy, status_read_dma_busy, status_write_dma_busy;
|
||||
logic desc_read_dma_hs, desc_write_dma_hs, status_read_dma_hs, status_write_dma_hs;
|
||||
|
||||
axi4l_reg_map_controller #(
|
||||
.ADDR_W(ADDR_W),
|
||||
.DATA_W(DATA_W),
|
||||
.USER_W(USER_W)
|
||||
) axi4l_reg_map_controller_inst (
|
||||
.clk(ctrl_clk),
|
||||
.rst_n(rst_n),
|
||||
.s_axil(s_axil),
|
||||
// CONTROLLER ADC/ DAC
|
||||
.start_o(start),
|
||||
.cfg_bus_valid_o(cfg_bus_valid),
|
||||
|
||||
.pulse_width_o(pulse_width),
|
||||
.pulse_period_o(pulse_period),
|
||||
.pulse_num_o(pulse_num),
|
||||
.pulse_height_raw_o(pulse_height_raw),
|
||||
.pulse_period_ADC_o(pulse_period_ADC),
|
||||
.window_size_o(window_size),
|
||||
|
||||
.rst_soft_o(rst_soft),
|
||||
.busy_i(busy),
|
||||
.error_code_i(error_code),
|
||||
|
||||
// CONTROLLER DMA
|
||||
.send_desc_read_o(send_desc_read),
|
||||
.send_desc_write_o(send_desc_write),
|
||||
.take_status_read_o(take_status_read),
|
||||
.take_status_write_o(take_status_write),
|
||||
|
||||
.desc_read_addr_o(desc_read_addr),
|
||||
.desc_read_len_o(desc_read_len),
|
||||
.desc_read_config_o(desc_read_config),
|
||||
|
||||
.status_read_i(status_read),
|
||||
|
||||
.desc_write_addr_o(desc_write_addr),
|
||||
.desc_write_len_and_tag_o(desc_write_len_and_tag),
|
||||
|
||||
.status_write_len_i(status_write_len),
|
||||
.status_write_config_i(status_write_config),
|
||||
|
||||
.desc_read_dma_busy_i(desc_read_dma_busy),
|
||||
.desc_write_dma_busy_i(desc_write_dma_busy),
|
||||
.status_read_dma_busy_i(status_read_dma_busy),
|
||||
.status_write_dma_busy_i(status_write_dma_busy),
|
||||
|
||||
.desc_read_dma_hs_i(desc_read_dma_hs),
|
||||
.desc_write_dma_hs_i(desc_write_dma_hs),
|
||||
.status_read_dma_hs_i(status_read_dma_hs),
|
||||
.status_write_dma_hs_i(status_write_dma_hs)
|
||||
);
|
||||
|
||||
// CONTROLLER DAC ADC
|
||||
// -------------------------------------------------------------------------
|
||||
// Field layout inside cfg_bus:
|
||||
// [31:0] pulse_width
|
||||
// [63:32] pulse_period
|
||||
// [79:64] pulse_num
|
||||
// [95:80] pulse_height_raw[15:0]
|
||||
// [127:96] pulse_period_ADC
|
||||
// [159:128] window_size
|
||||
// -------------------------------------------------------------------------
|
||||
(* MARK_DEBUG="true" *) logic [159:0] cfg_bus;
|
||||
assign cfg_bus = {window_size, pulse_period_ADC, pulse_height_raw[15:0], pulse_num[15:0], pulse_period, pulse_width};
|
||||
|
||||
control #(
|
||||
.DAC_DATA_WIDTH(DAC_DATA_WIDTH)
|
||||
)
|
||||
controller (
|
||||
.ctrl_clk(ctrl_clk),
|
||||
.dac_clk_in(dac_clk_in),
|
||||
.adc_clk_in(adc_clk_in),
|
||||
.rst_n(rst_n),
|
||||
.rst_soft(rst_soft),
|
||||
.finish(finish),
|
||||
.cfg_bus_input(cfg_bus),
|
||||
.cfg_bus_valid(cfg_bus_valid),
|
||||
.start(start),
|
||||
|
||||
.busy(busy),
|
||||
|
||||
.dac_pulse_width(dac_pulse_width),
|
||||
.dac_pulse_period(dac_pulse_period),
|
||||
.dac_pulse_height(dac_pulse_height),
|
||||
.dac_pulse_num(dac_pulse_num),
|
||||
.adc_pulse_period(adc_pulse_period),
|
||||
.adc_pulse_num(adc_pulse_num),
|
||||
.adc_window_size(adc_window_size),
|
||||
.dac_start(dac_start),
|
||||
.adc_start(adc_start),
|
||||
.dac_rst(dac_rst),
|
||||
.adc_rst(adc_rst)
|
||||
);
|
||||
|
||||
// CONTROLLER DMA
|
||||
|
||||
dma_read_desc_t desc_read_cmd, desc_read_cmd_out;
|
||||
assign desc_read_cmd.addr = desc_read_addr;
|
||||
assign desc_read_cmd.len = desc_read_len;
|
||||
assign desc_read_cmd.tag = desc_read_config[TAG_WIDTH-1:0];
|
||||
assign desc_read_cmd.id = desc_read_config[TAG_WIDTH +: AXIS_ID_WIDTH];
|
||||
assign desc_read_cmd.dest = desc_read_config[TAG_WIDTH+AXIS_ID_WIDTH +: AXIS_DEST_WIDTH];
|
||||
assign desc_read_cmd.user = desc_read_config[TAG_WIDTH+AXIS_ID_WIDTH+AXIS_DEST_WIDTH +: AXIS_USER_WIDTH];
|
||||
|
||||
dma_write_desc_t desc_write_cmd, desc_write_cmd_out;
|
||||
assign desc_write_cmd.addr = desc_write_addr;
|
||||
assign desc_write_cmd.len = desc_write_len_and_tag[LEN_WIDTH-1:0];
|
||||
assign desc_write_cmd.tag = desc_write_len_and_tag[LEN_WIDTH +: TAG_WIDTH];
|
||||
|
||||
dma_read_status_t status_read_cmd, status_read_cmd_in;
|
||||
assign status_read = { status_read_cmd.error, status_read_cmd.tag};
|
||||
|
||||
dma_write_status_t status_write_cmd, status_write_cmd_in;
|
||||
assign status_write_len = status_write_cmd.len;
|
||||
assign status_write_config = { status_write_cmd.error, status_write_cmd.user,
|
||||
status_write_cmd.dest, status_write_cmd.id, status_write_cmd.tag};
|
||||
|
||||
dma_controller dma_controller_inst
|
||||
(
|
||||
.dma_clk(ctrl_clk),
|
||||
.rst_n(rst_n),
|
||||
|
||||
.send_desc_read(send_desc_read),
|
||||
.send_desc_write(send_desc_write),
|
||||
.take_status_read(take_status_read),
|
||||
.take_status_write(take_status_write),
|
||||
|
||||
.desc_read_cmd(desc_read_cmd),
|
||||
.desc_write_cmd(desc_write_cmd),
|
||||
.status_read_cmd(status_read_cmd),
|
||||
.status_write_cmd(status_write_cmd),
|
||||
|
||||
.desc_read_cmd_out(desc_read_cmd_out),
|
||||
.desc_write_cmd_out(desc_write_cmd_out),
|
||||
.status_read_cmd_in(status_read_cmd_in),
|
||||
.status_write_cmd_in(status_write_cmd_in),
|
||||
|
||||
.ready_desc_read(m_axis_desc_read.resp.ready),
|
||||
.ready_desc_write(m_axis_desc_write.resp.ready),
|
||||
.ready_status_read(s_axis_status_read.resp.ready),
|
||||
.ready_status_write(s_axis_status_write.resp.ready),
|
||||
|
||||
.valid_desc_read(m_axis_desc_read.req.t.valid),
|
||||
.valid_desc_write(m_axis_desc_write.req.t.valid),
|
||||
.valid_status_read(s_axis_status_read.req.t.valid),
|
||||
.valid_status_write(s_axis_status_write.req.t.valid),
|
||||
|
||||
.desc_read_dma_busy(desc_read_dma_busy),
|
||||
.desc_write_dma_busy(desc_write_dma_busy),
|
||||
.status_read_dma_busy(status_read_dma_busy),
|
||||
.status_write_dma_busy(status_write_dma_busy),
|
||||
|
||||
.desc_read_dma_hs(desc_read_dma_hs),
|
||||
.desc_write_dma_hs(desc_write_dma_hs),
|
||||
.status_read_dma_hs(status_read_dma_hs),
|
||||
.status_write_dma_hs(status_write_dma_hs)
|
||||
);
|
||||
|
||||
axis_defaults_master defaults_rd (.axis(m_axis_desc_read));
|
||||
axis_defaults_master defaults_wr (.axis(m_axis_desc_write));
|
||||
|
||||
assign m_axis_desc_read.req.t.data = desc_read_cmd_out;
|
||||
assign m_axis_desc_write.req.t.data = desc_write_cmd_out;
|
||||
assign status_read_cmd_in = s_axis_status_read.req.t.data;
|
||||
assign status_write_cmd_in = s_axis_status_write.req.t.data;
|
||||
|
||||
endmodule
|
||||
111
rtl/controller/src/dma_controller.sv
Normal file
111
rtl/controller/src/dma_controller.sv
Normal file
@ -0,0 +1,111 @@
|
||||
import dma_reg_pkg::*;
|
||||
|
||||
module dma_controller
|
||||
(
|
||||
input dma_clk,
|
||||
input rst_n,
|
||||
input logic send_desc_read,
|
||||
input logic send_desc_write,
|
||||
input logic take_status_read,
|
||||
input logic take_status_write,
|
||||
|
||||
input logic ready_desc_read,
|
||||
input logic ready_desc_write,
|
||||
|
||||
output logic ready_status_read,
|
||||
output logic ready_status_write,
|
||||
|
||||
input dma_read_desc_t desc_read_cmd,
|
||||
input dma_write_desc_t desc_write_cmd,
|
||||
|
||||
output dma_read_status_t status_read_cmd,
|
||||
output dma_write_status_t status_write_cmd,
|
||||
|
||||
input dma_read_status_t status_read_cmd_in,
|
||||
input dma_write_status_t status_write_cmd_in,
|
||||
|
||||
output logic desc_read_dma_busy,
|
||||
output logic desc_write_dma_busy,
|
||||
output logic status_read_dma_busy,
|
||||
output logic status_write_dma_busy,
|
||||
|
||||
output logic desc_read_dma_hs,
|
||||
output logic desc_write_dma_hs,
|
||||
output logic status_read_dma_hs,
|
||||
output logic status_write_dma_hs,
|
||||
|
||||
output logic valid_desc_read,
|
||||
output logic valid_desc_write,
|
||||
|
||||
input logic valid_status_read,
|
||||
input logic valid_status_write,
|
||||
|
||||
output dma_read_desc_t desc_read_cmd_out,
|
||||
output dma_write_desc_t desc_write_cmd_out
|
||||
);
|
||||
|
||||
shaper_axis_desc
|
||||
#(
|
||||
.DATA_WIDTH($bits(dma_read_desc_t))
|
||||
) shaper_axis_desc_read
|
||||
(
|
||||
.clk(dma_clk),
|
||||
.rst_n(rst_n),
|
||||
.data_in(desc_read_cmd),
|
||||
.send(send_desc_read),
|
||||
.ready(ready_desc_read),
|
||||
.busy(desc_read_dma_busy),
|
||||
.handshake(desc_read_dma_hs),
|
||||
.data_out(desc_read_cmd_out),
|
||||
.valid(valid_desc_read)
|
||||
);
|
||||
|
||||
shaper_axis_desc
|
||||
#(
|
||||
.DATA_WIDTH($bits(dma_write_desc_t))
|
||||
) shaper_axis_desc_write
|
||||
(
|
||||
.clk(dma_clk),
|
||||
.rst_n(rst_n),
|
||||
.data_in(desc_write_cmd),
|
||||
.send(send_desc_write),
|
||||
.ready(ready_desc_write),
|
||||
.busy(desc_write_dma_busy),
|
||||
.handshake(desc_write_dma_hs),
|
||||
.data_out(desc_write_cmd_out),
|
||||
.valid(valid_desc_write)
|
||||
);
|
||||
|
||||
shaper_axis_status
|
||||
#(
|
||||
.DATA_WIDTH($bits(dma_read_status_t))
|
||||
) shaper_axis_status_read
|
||||
(
|
||||
.clk(dma_clk),
|
||||
.rst_n(rst_n),
|
||||
.data_in(status_read_cmd_in),
|
||||
.take(take_status_read),
|
||||
.valid(valid_status_read),
|
||||
.ready(ready_status_read),
|
||||
.busy(status_read_dma_busy),
|
||||
.handshake(status_read_dma_hs),
|
||||
.data_out(status_read_cmd)
|
||||
);
|
||||
|
||||
shaper_axis_status
|
||||
#(
|
||||
.DATA_WIDTH($bits(dma_write_status_t))
|
||||
) shaper_axis_status_write
|
||||
(
|
||||
.clk(dma_clk),
|
||||
.rst_n(rst_n),
|
||||
.data_in(status_write_cmd_in),
|
||||
.take(take_status_write),
|
||||
.valid(valid_status_write),
|
||||
.ready(ready_status_write),
|
||||
.busy(status_write_dma_busy),
|
||||
.handshake(status_write_dma_hs),
|
||||
.data_out(status_write_cmd)
|
||||
);
|
||||
|
||||
endmodule
|
||||
42
rtl/controller/src/dma_reg_pkg.sv
Normal file
42
rtl/controller/src/dma_reg_pkg.sv
Normal file
@ -0,0 +1,42 @@
|
||||
package dma_reg_pkg;
|
||||
parameter int unsigned AXI_ADDR_WIDTH = 16;
|
||||
parameter int unsigned LEN_WIDTH = 20;
|
||||
parameter int unsigned TAG_WIDTH = 8;
|
||||
parameter int unsigned AXIS_ID_WIDTH = 8;
|
||||
parameter int unsigned AXIS_DEST_WIDTH = 8;
|
||||
parameter int unsigned AXIS_USER_WIDTH = 1;
|
||||
|
||||
typedef struct packed {
|
||||
logic [AXIS_USER_WIDTH-1:0] user;
|
||||
logic [AXIS_DEST_WIDTH-1:0] dest;
|
||||
logic [AXIS_ID_WIDTH-1:0] id;
|
||||
logic [TAG_WIDTH-1:0] tag;
|
||||
logic [LEN_WIDTH-1:0] len;
|
||||
logic [AXI_ADDR_WIDTH-1:0] addr;
|
||||
|
||||
} dma_read_desc_t;
|
||||
|
||||
typedef struct packed {
|
||||
logic [TAG_WIDTH-1:0] tag;
|
||||
logic [LEN_WIDTH-1:0] len;
|
||||
logic [AXI_ADDR_WIDTH-1:0] addr;
|
||||
|
||||
} dma_write_desc_t;
|
||||
|
||||
typedef struct packed {
|
||||
logic [3:0] error;
|
||||
logic [TAG_WIDTH-1:0] tag;
|
||||
|
||||
} dma_read_status_t;
|
||||
|
||||
typedef struct packed {
|
||||
logic [3:0] error;
|
||||
logic [AXIS_USER_WIDTH-1:0] user;
|
||||
logic [AXIS_DEST_WIDTH-1:0] dest;
|
||||
logic [AXIS_ID_WIDTH-1:0] id;
|
||||
logic [TAG_WIDTH-1:0] tag;
|
||||
logic [LEN_WIDTH-1:0] len;
|
||||
|
||||
} dma_write_status_t;
|
||||
|
||||
endpackage
|
||||
54
rtl/controller/src/shaper_axis_desc.sv
Normal file
54
rtl/controller/src/shaper_axis_desc.sv
Normal file
@ -0,0 +1,54 @@
|
||||
module shaper_axis_desc #(
|
||||
parameter DATA_WIDTH = 128
|
||||
) (
|
||||
input clk,
|
||||
input rst_n,
|
||||
input logic [DATA_WIDTH-1:0] data_in,
|
||||
input logic send,
|
||||
input logic ready,
|
||||
|
||||
output logic busy,
|
||||
output logic handshake,
|
||||
output logic [DATA_WIDTH-1:0] data_out,
|
||||
output logic valid
|
||||
);
|
||||
|
||||
typedef enum logic [0:0] {
|
||||
IDLE,
|
||||
WAIT_READY
|
||||
} wr_state;
|
||||
|
||||
wr_state state;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (!rst_n) begin
|
||||
state <= IDLE;
|
||||
busy <= 1'b0;
|
||||
handshake <= 1'b0;
|
||||
data_out <= 1'b0;
|
||||
valid <= 1'b0;
|
||||
end else begin
|
||||
case (state)
|
||||
IDLE: begin
|
||||
handshake <= 1'b0;
|
||||
if (send) begin
|
||||
valid <= 1'b1;
|
||||
data_out <= data_in;
|
||||
busy <= 1'b1;
|
||||
state <= WAIT_READY;
|
||||
end
|
||||
end
|
||||
WAIT_READY: begin
|
||||
if (ready) begin
|
||||
valid <= 1'b0;
|
||||
handshake <= 1'b1;
|
||||
busy <= 1'b0;
|
||||
state <= IDLE;
|
||||
end
|
||||
end
|
||||
default: state <= IDLE;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
55
rtl/controller/src/shaper_axis_status.sv
Normal file
55
rtl/controller/src/shaper_axis_status.sv
Normal file
@ -0,0 +1,55 @@
|
||||
module shaper_axis_status #(
|
||||
parameter int unsigned DATA_WIDTH = 128
|
||||
)(
|
||||
input logic clk,
|
||||
input logic rst_n,
|
||||
|
||||
input logic [DATA_WIDTH-1:0] data_in,
|
||||
input logic take,
|
||||
input logic valid,
|
||||
output logic ready,
|
||||
|
||||
output logic busy,
|
||||
output logic handshake,
|
||||
output logic [DATA_WIDTH-1:0] data_out
|
||||
);
|
||||
|
||||
typedef enum logic [0:0] {
|
||||
IDLE,
|
||||
WAIT_VALID
|
||||
} wr_state;
|
||||
|
||||
wr_state state;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (!rst_n) begin
|
||||
state <= IDLE;
|
||||
ready <= 1'b0;
|
||||
busy <= 1'b0;
|
||||
handshake <= 1'b0;
|
||||
data_out <= '0;
|
||||
end else begin
|
||||
case (state)
|
||||
IDLE: begin
|
||||
handshake <= 1'b0;
|
||||
if (take) begin
|
||||
ready <= 1'b1;
|
||||
busy <= 1'b1;
|
||||
state <= WAIT_VALID;
|
||||
end
|
||||
end
|
||||
WAIT_VALID: begin
|
||||
if (valid) begin
|
||||
data_out <= data_in;
|
||||
ready <= 1'b0;
|
||||
handshake <= 1'b1;
|
||||
busy <= 1'b0;
|
||||
state <= IDLE;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
@ -1,52 +1,40 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
TOPLEVEL_LANG = verilog
|
||||
SIM ?= verilator
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xc7a35tfgg484-1
|
||||
FPGA_TOP = control
|
||||
FPGA_ARCH = artix7
|
||||
PWD := $(shell pwd)
|
||||
|
||||
RTL_DIR = ../src
|
||||
RTL_DIR = $(PWD)/../src
|
||||
LIBS_DIR = $(PWD)/../../../external/rtl_libs
|
||||
|
||||
VERILOG_SOURCES += $(LIBS_DIR)/axi/rtl/axi_pkg.sv
|
||||
VERILOG_SOURCES += $(LIBS_DIR)/axi/rtl/axi_if.sv
|
||||
VERILOG_SOURCES += $(LIBS_DIR)/axi/rtl/axi4l_flat_to_if.sv
|
||||
VERILOG_SOURCES += $(LIBS_DIR)/axi/rtl/axi4l_if_to_flat.sv
|
||||
VERILOG_SOURCES += $(LIBS_DIR)/axi/axi_reg/axi4l_reg_map.sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/controller.sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/dma_controller.sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/shaper_axis_desc.sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/shaper_axis_status.sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/controller_wrapper_axil.sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/axi4l_reg_map_controller_pkg.sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/axi4l_reg_map_controller.sv
|
||||
VERILOG_SOURCES += $(PWD)/tb_controller_wrapper_axil.sv
|
||||
|
||||
TOPLEVEL = tb_controller_wrapper_axil
|
||||
MODULE = test_controller
|
||||
|
||||
|
||||
include ../../../scripts/vivado.mk
|
||||
|
||||
SYN_FILES += $(sort $(shell find ../src -type f \( -name '*.v' -o -name '*.sv' \)))
|
||||
|
||||
XCI_FILES = $(sort $(shell find ../src -type f -name '*.xci'))
|
||||
|
||||
XDC_FILES += ../../../constraints/ax7a035b.xdc
|
||||
XDC_FILES += test_timing.xdc
|
||||
|
||||
SYN_FILES += controller_tb.sv
|
||||
SIM_TOP = control_tb
|
||||
ifeq ($(SIM),verilator)
|
||||
EXTRA_ARGS += --trace --trace-structs
|
||||
EXTRA_ARGS += -I$(LIBS_DIR)/axi/rtl/
|
||||
COMPILE_ARGS += -Wno-fatal
|
||||
COMPILE_ARGS += -I$(LIBS_DIR)/axi/rtl/
|
||||
EXTRA_ARGS += --trace
|
||||
EXTRA_ARGS += --trace-structs
|
||||
EXTRA_ARGS += --public-flat-rw
|
||||
EXTRA_ARGS += -Wno-fatal
|
||||
EXTRA_ARGS += --timing
|
||||
endif
|
||||
|
||||
|
||||
program: $(PROJECT).bit
|
||||
echo "open_hw_manager" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
|
||||
$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
|
||||
echo "write_cfgmem -force -format mcs -size 16 -interface SPIx4 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||
echo "exit" >> generate_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
|
||||
@ -4,72 +4,17 @@ module tb_control;
|
||||
|
||||
localparam int unsigned DAC_DATA_WIDTH = 12;
|
||||
|
||||
|
||||
//------------------------------------------------------------
|
||||
// Clocks / reset
|
||||
logic eth_clk_in;
|
||||
//------------------------------------------------------------
|
||||
logic ctrl_clk;
|
||||
logic dac_clk_in;
|
||||
logic adc_clk_in;
|
||||
logic rst_n;
|
||||
|
||||
// axi stream (input)
|
||||
logic [7:0] s_axis_tdata;
|
||||
logic s_axis_tvalid;
|
||||
logic s_axis_tready;
|
||||
logic s_axis_tlast;
|
||||
|
||||
// ADC side input
|
||||
logic finish;
|
||||
|
||||
// DUT outputs
|
||||
logic [31:0] dac_pulse_width;
|
||||
logic [31:0] dac_pulse_period;
|
||||
logic [DAC_DATA_WIDTH-1:0] dac_pulse_height;
|
||||
logic [15:0] dac_pulse_num;
|
||||
|
||||
logic [31:0] adc_pulse_period;
|
||||
logic [15:0] adc_pulse_num;
|
||||
|
||||
logic dac_start;
|
||||
logic adc_start;
|
||||
logic dac_rst;
|
||||
logic adc_rst;
|
||||
|
||||
|
||||
// DUT
|
||||
control #(
|
||||
.DAC_DATA_WIDTH(DAC_DATA_WIDTH)
|
||||
) dut (
|
||||
.eth_clk_in (eth_clk_in),
|
||||
.dac_clk_in (dac_clk_in),
|
||||
.adc_clk_in (adc_clk_in),
|
||||
.rst_n (rst_n),
|
||||
|
||||
.s_axis_tdata (s_axis_tdata),
|
||||
.s_axis_tvalid (s_axis_tvalid),
|
||||
.s_axis_tready (s_axis_tready),
|
||||
.s_axis_tlast (s_axis_tlast),
|
||||
|
||||
.finish (finish),
|
||||
|
||||
.dac_pulse_width (dac_pulse_width),
|
||||
.dac_pulse_period (dac_pulse_period),
|
||||
.dac_pulse_height (dac_pulse_height),
|
||||
.dac_pulse_num (dac_pulse_num),
|
||||
|
||||
.adc_pulse_period (adc_pulse_period),
|
||||
.adc_pulse_num (adc_pulse_num),
|
||||
|
||||
.dac_start (dac_start),
|
||||
.adc_start (adc_start),
|
||||
.dac_rst (dac_rst),
|
||||
.adc_rst (adc_rst)
|
||||
);
|
||||
|
||||
|
||||
// Clock generation
|
||||
initial begin
|
||||
eth_clk_in = 1'b0;
|
||||
forever #(1 * 4.000) eth_clk_in = ~eth_clk_in; // 125 MHz
|
||||
ctrl_clk = 1'b0;
|
||||
forever #(1 * 4.000) ctrl_clk = ~ctrl_clk; // 125 MHz
|
||||
end
|
||||
|
||||
initial begin
|
||||
@ -82,8 +27,81 @@ module tb_control;
|
||||
forever #(1 * 7.692307692) adc_clk_in = ~adc_clk_in; // ~65 MHz
|
||||
end
|
||||
|
||||
|
||||
//------------------------------------------------------------
|
||||
// DUT inputs
|
||||
//------------------------------------------------------------
|
||||
|
||||
logic rst_soft;
|
||||
|
||||
logic finish;
|
||||
|
||||
logic [159:0] cfg_bus_input;
|
||||
logic cfg_bus_valid;
|
||||
|
||||
logic start;
|
||||
|
||||
//------------------------------------------------------------
|
||||
// DUT outputs
|
||||
//------------------------------------------------------------
|
||||
|
||||
logic busy;
|
||||
|
||||
logic [31:0] dac_pulse_width;
|
||||
logic [31:0] dac_pulse_period;
|
||||
logic [DAC_DATA_WIDTH-1:0] dac_pulse_height;
|
||||
logic [15:0] dac_pulse_num;
|
||||
|
||||
logic [31:0] adc_pulse_period;
|
||||
logic [15:0] adc_pulse_num;
|
||||
logic [31:0] adc_window_size;
|
||||
|
||||
logic dac_start;
|
||||
logic adc_start;
|
||||
logic dac_rst;
|
||||
logic adc_rst;
|
||||
|
||||
//------------------------------------------------------------
|
||||
// DUT
|
||||
//------------------------------------------------------------
|
||||
|
||||
control #(
|
||||
.DAC_DATA_WIDTH(DAC_DATA_WIDTH)
|
||||
) dut (
|
||||
.ctrl_clk (ctrl_clk),
|
||||
.dac_clk_in (dac_clk_in),
|
||||
.adc_clk_in (adc_clk_in),
|
||||
|
||||
.rst_n (rst_n),
|
||||
.rst_soft (rst_soft),
|
||||
|
||||
.finish (finish),
|
||||
|
||||
.cfg_bus_input (cfg_bus_input),
|
||||
.cfg_bus_valid (cfg_bus_valid),
|
||||
|
||||
.start (start),
|
||||
|
||||
.busy (busy),
|
||||
|
||||
.dac_pulse_width (dac_pulse_width),
|
||||
.dac_pulse_period (dac_pulse_period),
|
||||
.dac_pulse_height (dac_pulse_height),
|
||||
.dac_pulse_num (dac_pulse_num),
|
||||
|
||||
.adc_pulse_period (adc_pulse_period),
|
||||
.adc_pulse_num (adc_pulse_num),
|
||||
.adc_window_size (adc_window_size),
|
||||
|
||||
.dac_start (dac_start),
|
||||
.adc_start (adc_start),
|
||||
.dac_rst (dac_rst),
|
||||
.adc_rst (adc_rst)
|
||||
);
|
||||
|
||||
//------------------------------------------------------------
|
||||
// pulse counters and monitors for testing
|
||||
//------------------------------------------------------------
|
||||
|
||||
int dac_rst_count;
|
||||
int adc_rst_count;
|
||||
int dac_start_count;
|
||||
@ -93,9 +111,13 @@ module tb_control;
|
||||
if (!rst_n) begin
|
||||
dac_rst_count <= 0;
|
||||
dac_start_count <= 0;
|
||||
end else begin
|
||||
if (dac_rst) dac_rst_count <= dac_rst_count + 1;
|
||||
if (dac_start) dac_start_count <= dac_start_count + 1;
|
||||
end
|
||||
else begin
|
||||
if (dac_rst)
|
||||
dac_rst_count <= dac_rst_count + 1;
|
||||
|
||||
if (dac_start)
|
||||
dac_start_count <= dac_start_count + 1;
|
||||
end
|
||||
end
|
||||
|
||||
@ -103,84 +125,113 @@ module tb_control;
|
||||
if (!rst_n) begin
|
||||
adc_rst_count <= 0;
|
||||
adc_start_count <= 0;
|
||||
end else begin
|
||||
if (adc_rst) adc_rst_count <= adc_rst_count + 1;
|
||||
if (adc_start) adc_start_count <= adc_start_count + 1;
|
||||
end
|
||||
else begin
|
||||
if (adc_rst)
|
||||
adc_rst_count <= adc_rst_count + 1;
|
||||
|
||||
if (adc_start)
|
||||
adc_start_count <= adc_start_count + 1;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// some helpers for axi
|
||||
task automatic axis_send_byte(input logic [7:0] data, input logic last);
|
||||
begin
|
||||
@(negedge eth_clk_in);
|
||||
s_axis_tdata <= data;
|
||||
s_axis_tvalid <= 1'b1;
|
||||
s_axis_tlast <= last;
|
||||
|
||||
@(posedge eth_clk_in);
|
||||
while (!s_axis_tready) begin
|
||||
@(posedge eth_clk_in);
|
||||
end
|
||||
|
||||
s_axis_tvalid <= 1'b0;
|
||||
s_axis_tlast <= 1'b0;
|
||||
s_axis_tdata <= '0;
|
||||
end
|
||||
endtask
|
||||
//------------------------------------------------------------
|
||||
// helpers
|
||||
//------------------------------------------------------------
|
||||
|
||||
task automatic send_cmd(input logic [7:0] cmd);
|
||||
begin
|
||||
axis_send_byte(cmd, 1'b1);
|
||||
end
|
||||
begin
|
||||
@(negedge ctrl_clk);
|
||||
|
||||
case (cmd)
|
||||
|
||||
8'h0F: begin
|
||||
rst_soft <= 1'b1;
|
||||
|
||||
@(posedge ctrl_clk);
|
||||
|
||||
rst_soft <= 1'b0;
|
||||
end
|
||||
|
||||
8'hF0: begin
|
||||
start <= 1'b1;
|
||||
|
||||
@(posedge ctrl_clk);
|
||||
|
||||
start <= 1'b0;
|
||||
end
|
||||
|
||||
default:
|
||||
$fatal(1, "Unsupported command %h", cmd);
|
||||
|
||||
endcase
|
||||
end
|
||||
endtask
|
||||
|
||||
task automatic send_set_data(
|
||||
input logic [31:0] pulse_width,
|
||||
input logic [31:0] pulse_period,
|
||||
input logic [15:0] pulse_num,
|
||||
input logic [15:0] pulse_height_raw,
|
||||
input logic [31:0] pulse_period_adc
|
||||
);
|
||||
logic [127:0] payload;
|
||||
int i;
|
||||
begin
|
||||
// little-endian payload layout:
|
||||
// [31:0] pulse_width
|
||||
// [63:32] pulse_period
|
||||
// [79:64] pulse_num
|
||||
// [95:80] pulse_height_raw
|
||||
// [127:96] pulse_period_ADC
|
||||
|
||||
payload = {pulse_period_adc, pulse_height_raw, pulse_num, pulse_period, pulse_width};
|
||||
input logic [31:0] pulse_width,
|
||||
input logic [31:0] pulse_period,
|
||||
input logic [15:0] pulse_num,
|
||||
input logic [15:0] pulse_height_raw,
|
||||
input logic [31:0] pulse_period_adc,
|
||||
input logic [31:0] window_size
|
||||
);
|
||||
|
||||
axis_send_byte(8'h88, 1'b0); // CMD_SET_DATA
|
||||
logic [159:0] payload;
|
||||
|
||||
for (i = 0; i < 16; i++) begin
|
||||
axis_send_byte(payload[i*8 +: 8], (i == 15));
|
||||
end
|
||||
end
|
||||
endtask
|
||||
begin
|
||||
|
||||
payload = {
|
||||
window_size,
|
||||
pulse_period_adc,
|
||||
pulse_height_raw,
|
||||
pulse_num,
|
||||
pulse_period,
|
||||
pulse_width
|
||||
};
|
||||
|
||||
@(negedge ctrl_clk);
|
||||
|
||||
cfg_bus_input <= payload;
|
||||
cfg_bus_valid <= 1'b1;
|
||||
|
||||
@(posedge ctrl_clk);
|
||||
|
||||
cfg_bus_valid <= 1'b0;
|
||||
cfg_bus_input <= '0;
|
||||
|
||||
end
|
||||
endtask
|
||||
|
||||
task automatic pulse_finish;
|
||||
begin
|
||||
@(posedge adc_clk_in);
|
||||
finish <= 1'b1;
|
||||
|
||||
@(posedge adc_clk_in);
|
||||
finish <= 1'b0;
|
||||
end
|
||||
endtask
|
||||
|
||||
|
||||
//------------------------------------------------------------
|
||||
// waiters
|
||||
//------------------------------------------------------------
|
||||
|
||||
task automatic wait_dac_rst_count(input int expected, input int max_cycles = 100);
|
||||
int i;
|
||||
begin
|
||||
for (i = 0; i < max_cycles; i++) begin
|
||||
@(posedge dac_clk_in);
|
||||
if (dac_rst_count >= expected) return;
|
||||
|
||||
if (dac_rst_count >= expected)
|
||||
return;
|
||||
end
|
||||
$fatal(1, "Timeout waiting for dac_rst_count >= %0d, current=%0d", expected, dac_rst_count);
|
||||
|
||||
$fatal(1,
|
||||
"Timeout waiting for dac_rst_count >= %0d, current=%0d",
|
||||
expected,
|
||||
dac_rst_count
|
||||
);
|
||||
end
|
||||
endtask
|
||||
|
||||
@ -189,9 +240,16 @@ module tb_control;
|
||||
begin
|
||||
for (i = 0; i < max_cycles; i++) begin
|
||||
@(posedge adc_clk_in);
|
||||
if (adc_rst_count >= expected) return;
|
||||
|
||||
if (adc_rst_count >= expected)
|
||||
return;
|
||||
end
|
||||
$fatal(1, "Timeout waiting for adc_rst_count >= %0d, current=%0d", expected, adc_rst_count);
|
||||
|
||||
$fatal(1,
|
||||
"Timeout waiting for adc_rst_count >= %0d, current=%0d",
|
||||
expected,
|
||||
adc_rst_count
|
||||
);
|
||||
end
|
||||
endtask
|
||||
|
||||
@ -200,9 +258,16 @@ module tb_control;
|
||||
begin
|
||||
for (i = 0; i < max_cycles; i++) begin
|
||||
@(posedge dac_clk_in);
|
||||
if (dac_start_count >= expected) return;
|
||||
|
||||
if (dac_start_count >= expected)
|
||||
return;
|
||||
end
|
||||
$fatal(1, "Timeout waiting for dac_start_count >= %0d, current=%0d", expected, dac_start_count);
|
||||
|
||||
$fatal(1,
|
||||
"Timeout waiting for dac_start_count >= %0d, current=%0d",
|
||||
expected,
|
||||
dac_start_count
|
||||
);
|
||||
end
|
||||
endtask
|
||||
|
||||
@ -211,165 +276,290 @@ module tb_control;
|
||||
begin
|
||||
for (i = 0; i < max_cycles; i++) begin
|
||||
@(posedge adc_clk_in);
|
||||
if (adc_start_count >= expected) return;
|
||||
end
|
||||
$fatal(1, "Timeout waiting for adc_start_count >= %0d, current=%0d", expected, adc_start_count);
|
||||
end
|
||||
endtask
|
||||
|
||||
task automatic wait_cfg_applied(
|
||||
input logic [31:0] exp_pulse_width,
|
||||
input logic [31:0] exp_pulse_period,
|
||||
input logic [15:0] exp_pulse_num,
|
||||
input logic [15:0] exp_pulse_height_raw,
|
||||
input logic [31:0] exp_pulse_period_adc,
|
||||
input int max_cycles = 200
|
||||
);
|
||||
logic [DAC_DATA_WIDTH-1:0] exp_dac_height;
|
||||
int i;
|
||||
begin
|
||||
exp_dac_height = exp_pulse_height_raw[DAC_DATA_WIDTH-1:0];
|
||||
|
||||
for (i = 0; i < max_cycles; i++) begin
|
||||
@(posedge eth_clk_in);
|
||||
if ((dac_pulse_width === exp_pulse_width ) &&
|
||||
(dac_pulse_period === exp_pulse_period) &&
|
||||
(dac_pulse_num === exp_pulse_num ) &&
|
||||
(dac_pulse_height === exp_dac_height ) &&
|
||||
(adc_pulse_period === exp_pulse_period_adc) &&
|
||||
(adc_pulse_num === exp_pulse_num )) begin
|
||||
if (adc_start_count >= expected)
|
||||
return;
|
||||
end
|
||||
end
|
||||
|
||||
$fatal(1,
|
||||
"Timeout waiting config outputs. Got: dac_width=%h dac_period=%h dac_num=%h dac_height=%h adc_period=%h adc_num=%h",
|
||||
dac_pulse_width, dac_pulse_period, dac_pulse_num, dac_pulse_height,
|
||||
adc_pulse_period, adc_pulse_num
|
||||
"Timeout waiting for adc_start_count >= %0d, current=%0d",
|
||||
expected,
|
||||
adc_start_count
|
||||
);
|
||||
end
|
||||
endtask
|
||||
|
||||
task automatic wait_cfg_applied(
|
||||
|
||||
input logic [31:0] exp_pulse_width,
|
||||
input logic [31:0] exp_pulse_period,
|
||||
input logic [15:0] exp_pulse_num,
|
||||
input logic [15:0] exp_pulse_height_raw,
|
||||
input logic [31:0] exp_pulse_period_adc,
|
||||
input logic [31:0] exp_window_size,
|
||||
input int max_cycles = 200
|
||||
);
|
||||
|
||||
logic [DAC_DATA_WIDTH-1:0] exp_height;
|
||||
|
||||
int i;
|
||||
|
||||
begin
|
||||
|
||||
exp_height = exp_pulse_height_raw[DAC_DATA_WIDTH-1:0];
|
||||
|
||||
for(i=0;i<max_cycles;i++) begin
|
||||
|
||||
@(posedge ctrl_clk);
|
||||
|
||||
if(
|
||||
|
||||
dac_pulse_width == exp_pulse_width &&
|
||||
dac_pulse_period == exp_pulse_period &&
|
||||
dac_pulse_num == exp_pulse_num &&
|
||||
dac_pulse_height == exp_height &&
|
||||
|
||||
adc_pulse_period == exp_pulse_period_adc &&
|
||||
adc_pulse_num == exp_pulse_num &&
|
||||
adc_window_size == exp_window_size
|
||||
|
||||
)
|
||||
return;
|
||||
|
||||
end
|
||||
|
||||
$fatal("Configuration timeout");
|
||||
|
||||
end
|
||||
endtask
|
||||
|
||||
//------------------------------------------------------------
|
||||
// Test sequence
|
||||
//------------------------------------------------------------
|
||||
|
||||
logic [31:0] test_pulse_width;
|
||||
logic [31:0] test_pulse_period;
|
||||
logic [15:0] test_pulse_num;
|
||||
logic [15:0] test_pulse_height_raw;
|
||||
logic [31:0] test_pulse_period_adc;
|
||||
logic [31:0] test_window_size;
|
||||
|
||||
initial begin
|
||||
// defaults
|
||||
rst_n = 1'b0;
|
||||
s_axis_tdata = '0;
|
||||
s_axis_tvalid = 1'b0;
|
||||
s_axis_tlast = 1'b0;
|
||||
rst_soft = 1'b0;
|
||||
|
||||
start = 1'b0;
|
||||
finish = 1'b0;
|
||||
|
||||
cfg_bus_input = '0;
|
||||
cfg_bus_valid = 1'b0;
|
||||
|
||||
test_pulse_width = 32'h11223344;
|
||||
test_pulse_period = 32'h55667788;
|
||||
test_pulse_num = 16'hA1B2;
|
||||
test_pulse_height_raw = 16'h0CDE; // for DAC_DATA_WIDTH=12 => 12'hCDE
|
||||
test_pulse_period_adc = 32'h50607080;
|
||||
test_window_size = 32'hABCDEF55;
|
||||
|
||||
repeat (10) @(posedge eth_clk_in);
|
||||
repeat (10) @(posedge ctrl_clk);
|
||||
rst_n = 1'b1;
|
||||
|
||||
repeat (10) @(posedge eth_clk_in);
|
||||
repeat (10) @(posedge ctrl_clk);
|
||||
|
||||
//--------------------------------------------------------
|
||||
// TEST 1: soft_reset
|
||||
//--------------------------------------------------------
|
||||
|
||||
$display("[%0t] TEST 1: soft_reset", $time);
|
||||
|
||||
send_cmd(8'h0F);
|
||||
|
||||
wait_dac_rst_count(1);
|
||||
wait_adc_rst_count(1);
|
||||
|
||||
if (dac_rst_count != 1) begin
|
||||
$fatal(1, "Expected exactly one dac_rst pulse after first soft_reset, got %0d", dac_rst_count);
|
||||
$fatal(1,
|
||||
"Expected exactly one dac_rst pulse after first soft_reset, got %0d",
|
||||
dac_rst_count
|
||||
);
|
||||
end
|
||||
|
||||
if (adc_rst_count != 1) begin
|
||||
$fatal(1, "Expected exactly one adc_rst pulse after first soft_reset, got %0d", adc_rst_count);
|
||||
$fatal(1,
|
||||
"Expected exactly one adc_rst pulse after first soft_reset, got %0d",
|
||||
adc_rst_count
|
||||
);
|
||||
end
|
||||
|
||||
$display("[%0t] TEST 1 passed", $time);
|
||||
|
||||
//--------------------------------------------------------
|
||||
// TEST 2: set_data
|
||||
//--------------------------------------------------------
|
||||
|
||||
$display("[%0t] TEST 2: set_data", $time);
|
||||
|
||||
send_set_data(
|
||||
test_pulse_width,
|
||||
test_pulse_period,
|
||||
test_pulse_num,
|
||||
test_pulse_height_raw,
|
||||
test_pulse_period_adc
|
||||
);
|
||||
|
||||
test_pulse_width,
|
||||
test_pulse_period,
|
||||
test_pulse_num,
|
||||
test_pulse_height_raw,
|
||||
test_pulse_period_adc,
|
||||
test_window_size
|
||||
|
||||
);
|
||||
|
||||
wait_cfg_applied(
|
||||
test_pulse_width,
|
||||
test_pulse_period,
|
||||
test_pulse_num,
|
||||
test_pulse_height_raw,
|
||||
test_pulse_period_adc
|
||||
);
|
||||
|
||||
test_pulse_width,
|
||||
test_pulse_period,
|
||||
test_pulse_num,
|
||||
test_pulse_height_raw,
|
||||
test_pulse_period_adc,
|
||||
test_window_size
|
||||
|
||||
);
|
||||
|
||||
if (dac_pulse_width !== 32'h11223344) begin
|
||||
$fatal(1, "dac_pulse_width mismatch: got %h expected %h", dac_pulse_width, 32'h11223344);
|
||||
$fatal(1,
|
||||
"dac_pulse_width mismatch: got %h expected %h",
|
||||
dac_pulse_width,
|
||||
32'h11223344
|
||||
);
|
||||
end
|
||||
|
||||
if (dac_pulse_period !== 32'h55667788) begin
|
||||
$fatal(1, "dac_pulse_period mismatch: got %h expected %h", dac_pulse_period, 32'h55667788);
|
||||
$fatal(1,
|
||||
"dac_pulse_period mismatch: got %h expected %h",
|
||||
dac_pulse_period,
|
||||
32'h55667788
|
||||
);
|
||||
end
|
||||
|
||||
if (dac_pulse_num !== 16'hA1B2) begin
|
||||
$fatal(1, "dac_pulse_num mismatch: got %h expected %h", dac_pulse_num, 16'hA1B2);
|
||||
$fatal(1,
|
||||
"dac_pulse_num mismatch: got %h expected %h",
|
||||
dac_pulse_num,
|
||||
16'hA1B2
|
||||
);
|
||||
end
|
||||
|
||||
if (dac_pulse_height !== 12'hCDE) begin
|
||||
$fatal(1, "dac_pulse_height mismatch: got %h expected %h", dac_pulse_height, 12'hCDE);
|
||||
$fatal(1,
|
||||
"dac_pulse_height mismatch: got %h expected %h",
|
||||
dac_pulse_height,
|
||||
12'hCDE
|
||||
);
|
||||
end
|
||||
|
||||
if (adc_pulse_period !== 32'h50607080) begin
|
||||
$fatal(1, "adc_pulse_period mismatch: got %h expected %h", adc_pulse_period, 32'h50607080);
|
||||
$fatal(1,
|
||||
"adc_pulse_period mismatch: got %h expected %h",
|
||||
adc_pulse_period,
|
||||
32'h50607080
|
||||
);
|
||||
end
|
||||
|
||||
if (adc_pulse_num !== 16'hA1B2) begin
|
||||
$fatal(1, "adc_pulse_num mismatch: got %h expected %h", adc_pulse_num, 16'hA1B2);
|
||||
$fatal(1,
|
||||
"adc_pulse_num mismatch: got %h expected %h",
|
||||
adc_pulse_num,
|
||||
16'hA1B2
|
||||
);
|
||||
end
|
||||
|
||||
if(adc_window_size != test_window_size)
|
||||
|
||||
$fatal(
|
||||
"adc_window_size mismatch. got=%h expected=%h",
|
||||
adc_window_size,
|
||||
test_window_size
|
||||
);
|
||||
|
||||
$display("[%0t] TEST 2 passed", $time);
|
||||
|
||||
repeat (20) @(posedge eth_clk_in);
|
||||
|
||||
repeat (20) @(posedge ctrl_clk);
|
||||
|
||||
//--------------------------------------------------------
|
||||
// TEST 3: start
|
||||
//--------------------------------------------------------
|
||||
|
||||
$display("[%0t] TEST 3: start", $time);
|
||||
|
||||
send_cmd(8'hF0);
|
||||
|
||||
wait_dac_start_count(1);
|
||||
wait_adc_start_count(1);
|
||||
|
||||
if (dac_start_count != 1) begin
|
||||
$fatal(1, "Expected exactly one dac_start pulse after first start, got %0d", dac_start_count);
|
||||
$fatal(1,
|
||||
"Expected exactly one dac_start pulse after first start, got %0d",
|
||||
dac_start_count
|
||||
);
|
||||
end
|
||||
|
||||
if (adc_start_count != 1) begin
|
||||
$fatal(1, "Expected exactly one adc_start pulse after first start, got %0d", adc_start_count);
|
||||
$fatal(1,
|
||||
"Expected exactly one adc_start pulse after first start, got %0d",
|
||||
adc_start_count
|
||||
);
|
||||
end
|
||||
|
||||
if (!busy) begin
|
||||
$fatal(1,
|
||||
"busy must be asserted after start"
|
||||
);
|
||||
end
|
||||
|
||||
$display("[%0t] TEST 3 start pulses passed", $time);
|
||||
|
||||
//--------------------------------------------------------
|
||||
// release busy by finish pulse from ADC domain
|
||||
//--------------------------------------------------------
|
||||
|
||||
$display("[%0t] Sending finish pulse", $time);
|
||||
|
||||
pulse_finish();
|
||||
|
||||
// a bit of wait for finish CDC back to ETH
|
||||
repeat (20) @(posedge eth_clk_in);
|
||||
repeat (20) @(posedge ctrl_clk);
|
||||
|
||||
if (busy) begin
|
||||
$fatal(1,
|
||||
"busy was not cleared after finish pulse"
|
||||
);
|
||||
end
|
||||
|
||||
//--------------------------------------------------------
|
||||
// sanity check that commands are accepted again after finish
|
||||
//--------------------------------------------------------
|
||||
|
||||
$display("[%0t] TEST 4: soft_reset after finish", $time);
|
||||
|
||||
send_cmd(8'h0F);
|
||||
|
||||
wait_dac_rst_count(2);
|
||||
wait_adc_rst_count(2);
|
||||
|
||||
if (dac_rst_count != 2) begin
|
||||
$fatal(1, "Expected exactly two dac_rst pulses total, got %0d", dac_rst_count);
|
||||
$fatal(1,
|
||||
"Expected exactly two dac_rst pulses total, got %0d",
|
||||
dac_rst_count
|
||||
);
|
||||
end
|
||||
|
||||
if (adc_rst_count != 2) begin
|
||||
$fatal(1, "Expected exactly two adc_rst pulses total, got %0d", adc_rst_count);
|
||||
$fatal(1,
|
||||
"Expected exactly two adc_rst pulses total, got %0d",
|
||||
adc_rst_count
|
||||
);
|
||||
end
|
||||
|
||||
$display("[%0t] TEST 4 passed", $time);
|
||||
|
||||
//--------------------------------------------------------
|
||||
|
||||
$display("==============================================");
|
||||
$display("ALL BASIC TESTS PASSED");
|
||||
$display("dac_rst_count = %0d", dac_rst_count);
|
||||
@ -378,8 +568,170 @@ module tb_control;
|
||||
$display("adc_start_count = %0d", adc_start_count);
|
||||
$display("==============================================");
|
||||
|
||||
#100;
|
||||
#50;
|
||||
|
||||
//--------------------------------------------------------
|
||||
// TEST 2.1: set_data
|
||||
//--------------------------------------------------------
|
||||
|
||||
test_pulse_width = 32'h12121212;
|
||||
test_pulse_period = 32'h34343434;
|
||||
test_pulse_num = 16'h1A2B;
|
||||
test_pulse_height_raw = 16'hC0ED; // for DAC_DATA_WIDTH=12 => 12'hCDE
|
||||
test_pulse_period_adc = 32'h56565656;
|
||||
test_window_size = 32'h01020304;
|
||||
|
||||
$display("[%0t] TEST 2.1: set_data", $time);
|
||||
|
||||
send_set_data(
|
||||
test_pulse_width,
|
||||
test_pulse_period,
|
||||
test_pulse_num,
|
||||
test_pulse_height_raw,
|
||||
test_pulse_period_adc,
|
||||
test_window_size
|
||||
);
|
||||
|
||||
wait_cfg_applied(
|
||||
test_pulse_width,
|
||||
test_pulse_period,
|
||||
test_pulse_num,
|
||||
test_pulse_height_raw,
|
||||
test_pulse_period_adc,
|
||||
test_window_size
|
||||
);
|
||||
|
||||
if (dac_pulse_width !== 32'h12121212) begin
|
||||
$fatal(1,
|
||||
"dac_pulse_width mismatch: got %h expected %h",
|
||||
dac_pulse_width,
|
||||
32'h12121212
|
||||
);
|
||||
end
|
||||
|
||||
if (dac_pulse_period !== 32'h34343434) begin
|
||||
$fatal(1,
|
||||
"dac_pulse_period mismatch: got %h expected %h",
|
||||
dac_pulse_period,
|
||||
32'h34343434
|
||||
);
|
||||
end
|
||||
|
||||
if (dac_pulse_num !== 16'h1A2B) begin
|
||||
$fatal(1,
|
||||
"dac_pulse_num mismatch: got %h expected %h",
|
||||
dac_pulse_num,
|
||||
16'h1A2B
|
||||
);
|
||||
end
|
||||
|
||||
if (dac_pulse_height !== 12'hC0ED) begin
|
||||
$fatal(1,
|
||||
"dac_pulse_height mismatch: got %h expected %h",
|
||||
dac_pulse_height,
|
||||
12'hC0ED
|
||||
);
|
||||
end
|
||||
|
||||
if (adc_pulse_period !== 32'h56565656) begin
|
||||
$fatal(1,
|
||||
"adc_pulse_period mismatch: got %h expected %h",
|
||||
adc_pulse_period,
|
||||
32'h56565656
|
||||
);
|
||||
end
|
||||
|
||||
$display("[%0t] TEST 2.1 passed", $time);
|
||||
|
||||
repeat (20) @(posedge ctrl_clk);
|
||||
|
||||
//--------------------------------------------------------
|
||||
// TEST 3.1: start
|
||||
//--------------------------------------------------------
|
||||
|
||||
$display("[%0t] TEST 3.1: start", $time);
|
||||
|
||||
send_cmd(8'hF0);
|
||||
|
||||
wait_dac_start_count(2);
|
||||
wait_adc_start_count(2);
|
||||
|
||||
if (dac_start_count != 2) begin
|
||||
$fatal(1,
|
||||
"Expected exactly one dac_start pulse after first start, got %0d",
|
||||
dac_start_count
|
||||
);
|
||||
end
|
||||
|
||||
if (adc_start_count != 2) begin
|
||||
$fatal(1,
|
||||
"Expected exactly one adc_start pulse after first start, got %0d",
|
||||
adc_start_count
|
||||
);
|
||||
end
|
||||
|
||||
if (!busy) begin
|
||||
$fatal(1,
|
||||
"busy must be asserted after start"
|
||||
);
|
||||
end
|
||||
|
||||
$display("[%0t] TEST 3.1 start pulses passed", $time);
|
||||
|
||||
//--------------------------------------------------------
|
||||
// release busy by finish pulse from ADC domain
|
||||
//--------------------------------------------------------
|
||||
|
||||
$display("[%0t] Sending finish pulse", $time);
|
||||
|
||||
pulse_finish();
|
||||
|
||||
repeat (20) @(posedge ctrl_clk);
|
||||
|
||||
if (busy) begin
|
||||
$fatal(1,
|
||||
"busy was not cleared after finish pulse"
|
||||
);
|
||||
end
|
||||
|
||||
//--------------------------------------------------------
|
||||
// sanity check that commands are accepted again after finish
|
||||
//--------------------------------------------------------
|
||||
|
||||
$display("[%0t] TEST 4.1: soft_reset after finish", $time);
|
||||
|
||||
send_cmd(8'h0F);
|
||||
|
||||
wait_dac_rst_count(2);
|
||||
wait_adc_rst_count(2);
|
||||
|
||||
if (dac_rst_count != 2) begin
|
||||
$fatal(1,
|
||||
"Expected exactly two dac_rst pulses total, got %0d",
|
||||
dac_rst_count
|
||||
);
|
||||
end
|
||||
|
||||
if (adc_rst_count != 2) begin
|
||||
$fatal(1,
|
||||
"Expected exactly two adc_rst pulses total, got %0d",
|
||||
adc_rst_count
|
||||
);
|
||||
end
|
||||
|
||||
$display("[%0t] TEST 4.1 passed", $time);
|
||||
|
||||
//--------------------------------------------------------
|
||||
|
||||
$display("==============================================");
|
||||
$display("ALL BASIC TESTS PASSED");
|
||||
$display("dac_rst_count = %0d", dac_rst_count);
|
||||
$display("adc_rst_count = %0d", adc_rst_count);
|
||||
$display("dac_start_count = %0d", dac_start_count);
|
||||
$display("adc_start_count = %0d", adc_start_count);
|
||||
$display("==============================================");
|
||||
$finish;
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
@ -11,187 +11,226 @@
|
||||
</db_ref>
|
||||
</db_ref_list>
|
||||
<zoom_setting>
|
||||
<ZoomStartTime time="0.676 ns"></ZoomStartTime>
|
||||
<ZoomEndTime time="645.677 ns"></ZoomEndTime>
|
||||
<Cursor1Time time="349.676 ns"></Cursor1Time>
|
||||
<ZoomStartTime time="160.614 ns"></ZoomStartTime>
|
||||
<ZoomEndTime time="1,564.737 ns"></ZoomEndTime>
|
||||
<Cursor1Time time="1,330.716 ns"></Cursor1Time>
|
||||
</zoom_setting>
|
||||
<column_width_setting>
|
||||
<NameColumnWidth column_width="558"></NameColumnWidth>
|
||||
<ValueColumnWidth column_width="61"></ValueColumnWidth>
|
||||
<NameColumnWidth column_width="479"></NameColumnWidth>
|
||||
<ValueColumnWidth column_width="116"></ValueColumnWidth>
|
||||
</column_width_setting>
|
||||
<WVObjectSize size="23" />
|
||||
<wvobject type="logic" fp_name="/tb_control/eth_clk_in">
|
||||
<obj_property name="ElementShortName">eth_clk_in</obj_property>
|
||||
<obj_property name="ObjectShortName">eth_clk_in</obj_property>
|
||||
<obj_property name="CustomSignalColor">#008080</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/tb_control/dac_clk_in">
|
||||
<WVObjectSize size="34" />
|
||||
<wvobject fp_name="/tb_control/dac_clk_in" type="logic">
|
||||
<obj_property name="ElementShortName">dac_clk_in</obj_property>
|
||||
<obj_property name="ObjectShortName">dac_clk_in</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FFA500</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/tb_control/adc_clk_in">
|
||||
<wvobject fp_name="/tb_control/adc_clk_in" type="logic">
|
||||
<obj_property name="ElementShortName">adc_clk_in</obj_property>
|
||||
<obj_property name="ObjectShortName">adc_clk_in</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/tb_control/rst_n">
|
||||
<wvobject fp_name="/tb_control/rst_n" type="logic">
|
||||
<obj_property name="ElementShortName">rst_n</obj_property>
|
||||
<obj_property name="ObjectShortName">rst_n</obj_property>
|
||||
<obj_property name="CustomSignalColor">#800080</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/tb_control/s_axis_tdata">
|
||||
<obj_property name="ElementShortName">s_axis_tdata[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">s_axis_tdata[7:0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#008080</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
<obj_property name="Radix">BINARYRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/tb_control/s_axis_tvalid">
|
||||
<obj_property name="ElementShortName">s_axis_tvalid</obj_property>
|
||||
<obj_property name="ObjectShortName">s_axis_tvalid</obj_property>
|
||||
<wvobject fp_name="/tb_control/rst_soft" type="logic">
|
||||
<obj_property name="ElementShortName">rst_soft</obj_property>
|
||||
<obj_property name="ObjectShortName">rst_soft</obj_property>
|
||||
<obj_property name="CustomSignalColor">#008080</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/tb_control/s_axis_tready">
|
||||
<obj_property name="ElementShortName">s_axis_tready</obj_property>
|
||||
<obj_property name="ObjectShortName">s_axis_tready</obj_property>
|
||||
<obj_property name="CustomSignalColor">#008080</obj_property>
|
||||
<wvobject fp_name="/tb_control/start" type="logic">
|
||||
<obj_property name="ElementShortName">start</obj_property>
|
||||
<obj_property name="ObjectShortName">start</obj_property>
|
||||
<obj_property name="CustomSignalColor">#E0FFFF</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/tb_control/s_axis_tlast">
|
||||
<obj_property name="ElementShortName">s_axis_tlast</obj_property>
|
||||
<obj_property name="ObjectShortName">s_axis_tlast</obj_property>
|
||||
<obj_property name="CustomSignalColor">#008080</obj_property>
|
||||
<wvobject fp_name="/tb_control/dut/adc_start_pulse" type="logic">
|
||||
<obj_property name="ElementShortName">adc_start_pulse</obj_property>
|
||||
<obj_property name="ObjectShortName">adc_start_pulse</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/dut/dac_start_pulse" type="logic">
|
||||
<obj_property name="ElementShortName">dac_start_pulse</obj_property>
|
||||
<obj_property name="ObjectShortName">dac_start_pulse</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/busy" type="logic">
|
||||
<obj_property name="ElementShortName">busy</obj_property>
|
||||
<obj_property name="ObjectShortName">busy</obj_property>
|
||||
<obj_property name="CustomSignalColor">#E0FFFF</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/tb_control/finish">
|
||||
<wvobject fp_name="/tb_control/finish" type="logic">
|
||||
<obj_property name="ElementShortName">finish</obj_property>
|
||||
<obj_property name="ObjectShortName">finish</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FAAFBE</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/tb_control/dac_pulse_width">
|
||||
<wvobject fp_name="/tb_control/dut/finish_pulse" type="logic">
|
||||
<obj_property name="ElementShortName">finish_pulse</obj_property>
|
||||
<obj_property name="ObjectShortName">finish_pulse</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/cfg_bus_valid" type="logic">
|
||||
<obj_property name="ElementShortName">cfg_bus_valid</obj_property>
|
||||
<obj_property name="ObjectShortName">cfg_bus_valid</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FF0080</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/cfg_bus_input" type="array">
|
||||
<obj_property name="ElementShortName">cfg_bus_input[159:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">cfg_bus_input[159:0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FF0080</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/dac_pulse_width" type="array">
|
||||
<obj_property name="ElementShortName">dac_pulse_width[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">dac_pulse_width[31:0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FFA500</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/tb_control/dac_pulse_period">
|
||||
<wvobject fp_name="/tb_control/dac_pulse_period" type="array">
|
||||
<obj_property name="ElementShortName">dac_pulse_period[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">dac_pulse_period[31:0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FFA500</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/tb_control/dac_pulse_height">
|
||||
<wvobject fp_name="/tb_control/dac_pulse_height" type="array">
|
||||
<obj_property name="ElementShortName">dac_pulse_height[11:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">dac_pulse_height[11:0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FFA500</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/tb_control/dac_pulse_num">
|
||||
<wvobject fp_name="/tb_control/dac_pulse_num" type="array">
|
||||
<obj_property name="ElementShortName">dac_pulse_num[15:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">dac_pulse_num[15:0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FFA500</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/tb_control/adc_pulse_period">
|
||||
<wvobject fp_name="/tb_control/adc_pulse_period" type="array">
|
||||
<obj_property name="ElementShortName">adc_pulse_period[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">adc_pulse_period[31:0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FFA500</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/tb_control/adc_pulse_num">
|
||||
<wvobject fp_name="/tb_control/adc_pulse_num" type="array">
|
||||
<obj_property name="ElementShortName">adc_pulse_num[15:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">adc_pulse_num[15:0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FFA500</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/tb_control/dac_start">
|
||||
<wvobject fp_name="/tb_control/adc_window_size" type="array">
|
||||
<obj_property name="ElementShortName">adc_window_size[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">adc_window_size[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/dac_start" type="logic">
|
||||
<obj_property name="ElementShortName">dac_start</obj_property>
|
||||
<obj_property name="ObjectShortName">dac_start</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FFA500</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/tb_control/adc_start">
|
||||
<wvobject fp_name="/tb_control/adc_start" type="logic">
|
||||
<obj_property name="ElementShortName">adc_start</obj_property>
|
||||
<obj_property name="ObjectShortName">adc_start</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/tb_control/dac_rst">
|
||||
<wvobject fp_name="/tb_control/dac_rst" type="logic">
|
||||
<obj_property name="ElementShortName">dac_rst</obj_property>
|
||||
<obj_property name="ObjectShortName">dac_rst</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FFA500</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/tb_control/adc_rst">
|
||||
<wvobject fp_name="/tb_control/adc_rst" type="logic">
|
||||
<obj_property name="ElementShortName">adc_rst</obj_property>
|
||||
<obj_property name="ObjectShortName">adc_rst</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="group" fp_name="group499">
|
||||
<wvobject fp_name="group499" type="group">
|
||||
<obj_property name="label">tb signals</obj_property>
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
<wvobject type="array" fp_name="/tb_control/dac_rst_count">
|
||||
<wvobject fp_name="/tb_control/dac_rst_count" type="array">
|
||||
<obj_property name="ElementShortName">dac_rst_count[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">dac_rst_count[31:0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#F0E68C</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/tb_control/adc_rst_count">
|
||||
<wvobject fp_name="/tb_control/adc_rst_count" type="array">
|
||||
<obj_property name="ElementShortName">adc_rst_count[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">adc_rst_count[31:0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#F0E68C</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/tb_control/dac_start_count">
|
||||
<wvobject fp_name="/tb_control/dac_start_count" type="array">
|
||||
<obj_property name="ElementShortName">dac_start_count[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">dac_start_count[31:0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#F0E68C</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/tb_control/adc_start_count">
|
||||
<wvobject fp_name="/tb_control/adc_start_count" type="array">
|
||||
<obj_property name="ElementShortName">adc_start_count[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">adc_start_count[31:0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#F0E68C</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/tb_control/test_pulse_width">
|
||||
<obj_property name="ElementShortName">test_pulse_width[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">test_pulse_width[31:0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#F0E68C</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/tb_control/test_pulse_period">
|
||||
<obj_property name="ElementShortName">test_pulse_period[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">test_pulse_period[31:0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#F0E68C</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/tb_control/test_pulse_num">
|
||||
<obj_property name="ElementShortName">test_pulse_num[15:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">test_pulse_num[15:0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#F0E68C</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/tb_control/test_pulse_height_raw">
|
||||
<obj_property name="ElementShortName">test_pulse_height_raw[15:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">test_pulse_height_raw[15:0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#F0E68C</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/tb_control/DAC_DATA_WIDTH">
|
||||
<obj_property name="ElementShortName">DAC_DATA_WIDTH[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">DAC_DATA_WIDTH[31:0]</obj_property>
|
||||
<wvobject fp_name="/tb_control/dut/cfg_req_toggle_adc" type="logic">
|
||||
<obj_property name="ElementShortName">cfg_req_toggle_adc</obj_property>
|
||||
<obj_property name="ObjectShortName">cfg_req_toggle_adc</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FFFF00</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/tb_control/dut/cfg_ack_toggle_adc">
|
||||
<wvobject fp_name="/tb_control/dut/cfg_req_toggle_dac" type="logic">
|
||||
<obj_property name="ElementShortName">cfg_req_toggle_dac</obj_property>
|
||||
<obj_property name="ObjectShortName">cfg_req_toggle_dac</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FFFF00</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/dut/cfg_ack_toggle_adc" type="logic">
|
||||
<obj_property name="ElementShortName">cfg_ack_toggle_adc</obj_property>
|
||||
<obj_property name="ObjectShortName">cfg_ack_toggle_adc</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FF00FF</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/tb_control/dut/cfg_ack_toggle_dac">
|
||||
<wvobject fp_name="/tb_control/dut/cfg_ack_toggle_dac" type="logic">
|
||||
<obj_property name="ElementShortName">cfg_ack_toggle_dac</obj_property>
|
||||
<obj_property name="ObjectShortName">cfg_ack_toggle_dac</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FF00FF</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/dut/cfg_wait_adc_ack" type="logic">
|
||||
<obj_property name="ElementShortName">cfg_wait_adc_ack</obj_property>
|
||||
<obj_property name="ObjectShortName">cfg_wait_adc_ack</obj_property>
|
||||
<obj_property name="CustomSignalColor">#0000FF</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/dut/cfg_wait_dac_ack" type="logic">
|
||||
<obj_property name="ElementShortName">cfg_wait_dac_ack</obj_property>
|
||||
<obj_property name="ObjectShortName">cfg_wait_dac_ack</obj_property>
|
||||
<obj_property name="CustomSignalColor">#0000FF</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/dut/cfg_req_pulse_adc" type="logic">
|
||||
<obj_property name="ElementShortName">cfg_req_pulse_adc</obj_property>
|
||||
<obj_property name="ObjectShortName">cfg_req_pulse_adc</obj_property>
|
||||
<obj_property name="CustomSignalColor">#808000</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/dut/cfg_req_pulse_dac" type="logic">
|
||||
<obj_property name="ElementShortName">cfg_req_pulse_dac</obj_property>
|
||||
<obj_property name="ObjectShortName">cfg_req_pulse_dac</obj_property>
|
||||
<obj_property name="CustomSignalColor">#808000</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/dut/cfg_ack_pulse_adc" type="logic">
|
||||
<obj_property name="ElementShortName">cfg_ack_pulse_adc</obj_property>
|
||||
<obj_property name="ObjectShortName">cfg_ack_pulse_adc</obj_property>
|
||||
<obj_property name="CustomSignalColor">#DCDCDC</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_control/dut/cfg_ack_pulse_dac" type="logic">
|
||||
<obj_property name="ElementShortName">cfg_ack_pulse_dac</obj_property>
|
||||
<obj_property name="ObjectShortName">cfg_ack_pulse_dac</obj_property>
|
||||
<obj_property name="CustomSignalColor">#DCDCDC</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
</wave_config>
|
||||
|
||||
338
rtl/controller/tests/tb_controller_wrapper_axil.sv
Normal file
338
rtl/controller/tests/tb_controller_wrapper_axil.sv
Normal file
@ -0,0 +1,338 @@
|
||||
module tb_controller_wrapper_axil #(
|
||||
parameter int unsigned ADDR_W = 16,
|
||||
parameter int unsigned DATA_W = 32,
|
||||
parameter int unsigned USER_W = 1,
|
||||
|
||||
parameter int unsigned DAC_DATA_WIDTH = 12,
|
||||
|
||||
parameter int unsigned AXI_ADDR_WIDTH = 16,
|
||||
parameter int unsigned AXIS_ID_WIDTH = 8,
|
||||
parameter int unsigned LEN_WIDTH = 20,
|
||||
parameter int unsigned AXIS_USER_WIDTH = 1,
|
||||
parameter int unsigned AXIS_DEST_WIDTH = 8,
|
||||
parameter int unsigned TAG_WIDTH = 8,
|
||||
|
||||
parameter int unsigned READ_DESC_WIDTH = AXI_ADDR_WIDTH + LEN_WIDTH + TAG_WIDTH + AXIS_ID_WIDTH + AXIS_DEST_WIDTH + AXIS_USER_WIDTH,
|
||||
parameter int unsigned WRITE_DESC_WIDTH = AXI_ADDR_WIDTH + LEN_WIDTH + TAG_WIDTH,
|
||||
|
||||
parameter int unsigned READ_STATUS_WIDTH = TAG_WIDTH + 4,
|
||||
parameter int unsigned WRITE_STATUS_WIDTH = LEN_WIDTH + TAG_WIDTH + AXIS_ID_WIDTH + AXIS_DEST_WIDTH + AXIS_USER_WIDTH + 4,
|
||||
|
||||
// ceil(width / 8), чтобы keep/strb не стали слишком узкими для нестандартных ширин типа 12/49/61.
|
||||
parameter int unsigned READ_DESC_KEEP_W = (READ_DESC_WIDTH + 7) / 8,
|
||||
parameter int unsigned WRITE_DESC_KEEP_W = (WRITE_DESC_WIDTH + 7) / 8,
|
||||
parameter int unsigned READ_STATUS_KEEP_W = (READ_STATUS_WIDTH + 7) / 8,
|
||||
parameter int unsigned WRITE_STATUS_KEEP_W = (WRITE_STATUS_WIDTH + 7) / 8
|
||||
)(
|
||||
input logic ctrl_clk,
|
||||
input logic rst,
|
||||
|
||||
input logic [ADDR_W-1:0] s_axil_awaddr,
|
||||
input logic [2:0] s_axil_awprot,
|
||||
input logic s_axil_awvalid,
|
||||
output logic s_axil_awready,
|
||||
|
||||
input logic [DATA_W-1:0] s_axil_wdata,
|
||||
input logic [DATA_W/8-1:0] s_axil_wstrb,
|
||||
input logic s_axil_wvalid,
|
||||
output logic s_axil_wready,
|
||||
|
||||
output logic [1:0] s_axil_bresp,
|
||||
output logic s_axil_bvalid,
|
||||
input logic s_axil_bready,
|
||||
|
||||
input logic [ADDR_W-1:0] s_axil_araddr,
|
||||
input logic [2:0] s_axil_arprot,
|
||||
input logic s_axil_arvalid,
|
||||
output logic s_axil_arready,
|
||||
|
||||
output logic [DATA_W-1:0] s_axil_rdata,
|
||||
output logic [1:0] s_axil_rresp,
|
||||
output logic s_axil_rvalid,
|
||||
input logic s_axil_rready,
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
// Минимальный flat-view для DMA AXIS портов.
|
||||
// Наружу оставлены только tdata/tvalid/tready в старом стиле.
|
||||
// Все остальные AXIS поля внутри обёртки завязаны на безопасные значения.
|
||||
// ---------------------------------------------------------------------------
|
||||
|
||||
// DUT master -> testbench: descriptor commands.
|
||||
output logic [READ_DESC_WIDTH-1:0] desc_read_cmd_out,
|
||||
output logic valid_desc_read,
|
||||
input logic ready_desc_read,
|
||||
|
||||
output logic [WRITE_DESC_WIDTH-1:0] desc_write_cmd_out,
|
||||
output logic valid_desc_write,
|
||||
input logic ready_desc_write,
|
||||
|
||||
// testbench -> DUT slave: status commands.
|
||||
input logic [READ_STATUS_WIDTH-1:0] status_read_cmd_in,
|
||||
input logic valid_status_read,
|
||||
output logic ready_status_read,
|
||||
|
||||
input logic [WRITE_STATUS_WIDTH-1:0] status_write_cmd_in,
|
||||
input logic valid_status_write,
|
||||
output logic ready_status_write
|
||||
);
|
||||
|
||||
logic rst_n;
|
||||
assign rst_n = ~rst;
|
||||
|
||||
// Для минимального теста держим все clock domain-ы на одном clock.
|
||||
logic dac_clk_in;
|
||||
logic adc_clk_in;
|
||||
assign dac_clk_in = ctrl_clk;
|
||||
assign adc_clk_in = ctrl_clk;
|
||||
|
||||
logic finish;
|
||||
assign finish = 1'b0;
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
// AXI-Lite flat -> axi4l_if
|
||||
// ---------------------------------------------------------------------------
|
||||
|
||||
axi4l_if #(
|
||||
.ADDR_W(ADDR_W),
|
||||
.DATA_W(DATA_W),
|
||||
.USER_W(USER_W)
|
||||
) axil_bus (
|
||||
.aclk(ctrl_clk),
|
||||
.aresetn(rst_n)
|
||||
);
|
||||
|
||||
axi4l_flat_to_if #(
|
||||
.ADDR_W(ADDR_W),
|
||||
.DATA_W(DATA_W),
|
||||
.USER_W(USER_W)
|
||||
) u_axil_flat_to_if (
|
||||
.s_axil_awaddr (s_axil_awaddr),
|
||||
.s_axil_awprot (s_axil_awprot),
|
||||
.s_axil_awvalid(s_axil_awvalid),
|
||||
.s_axil_awready(s_axil_awready),
|
||||
|
||||
.s_axil_wdata (s_axil_wdata),
|
||||
.s_axil_wstrb (s_axil_wstrb),
|
||||
.s_axil_wvalid (s_axil_wvalid),
|
||||
.s_axil_wready (s_axil_wready),
|
||||
|
||||
.s_axil_bresp (s_axil_bresp),
|
||||
.s_axil_bvalid (s_axil_bvalid),
|
||||
.s_axil_bready (s_axil_bready),
|
||||
|
||||
.s_axil_araddr (s_axil_araddr),
|
||||
.s_axil_arprot (s_axil_arprot),
|
||||
.s_axil_arvalid(s_axil_arvalid),
|
||||
.s_axil_arready(s_axil_arready),
|
||||
|
||||
.s_axil_rdata (s_axil_rdata),
|
||||
.s_axil_rresp (s_axil_rresp),
|
||||
.s_axil_rvalid (s_axil_rvalid),
|
||||
.s_axil_rready (s_axil_rready),
|
||||
|
||||
.m_axil(axil_bus)
|
||||
);
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
// AXIS interfaces for the updated controller_wrapper_axil
|
||||
// ---------------------------------------------------------------------------
|
||||
|
||||
axis_if #(
|
||||
.DATA_W(READ_STATUS_WIDTH),
|
||||
.KEEP_W(READ_STATUS_KEEP_W),
|
||||
.ID_W(AXIS_ID_WIDTH),
|
||||
.DEST_W(AXIS_DEST_WIDTH),
|
||||
.USER_W(AXIS_USER_WIDTH)
|
||||
) axis_status_read (
|
||||
.aclk(ctrl_clk),
|
||||
.aresetn(rst_n)
|
||||
);
|
||||
|
||||
axis_if #(
|
||||
.DATA_W(WRITE_STATUS_WIDTH),
|
||||
.KEEP_W(WRITE_STATUS_KEEP_W),
|
||||
.ID_W(AXIS_ID_WIDTH),
|
||||
.DEST_W(AXIS_DEST_WIDTH),
|
||||
.USER_W(AXIS_USER_WIDTH)
|
||||
) axis_status_write (
|
||||
.aclk(ctrl_clk),
|
||||
.aresetn(rst_n)
|
||||
);
|
||||
|
||||
axis_if #(
|
||||
.DATA_W(READ_DESC_WIDTH),
|
||||
.KEEP_W(READ_DESC_KEEP_W),
|
||||
.ID_W(AXIS_ID_WIDTH),
|
||||
.DEST_W(AXIS_DEST_WIDTH),
|
||||
.USER_W(AXIS_USER_WIDTH)
|
||||
) axis_desc_read (
|
||||
.aclk(ctrl_clk),
|
||||
.aresetn(rst_n)
|
||||
);
|
||||
|
||||
axis_if #(
|
||||
.DATA_W(WRITE_DESC_WIDTH),
|
||||
.KEEP_W(WRITE_DESC_KEEP_W),
|
||||
.ID_W(AXIS_ID_WIDTH),
|
||||
.DEST_W(AXIS_DEST_WIDTH),
|
||||
.USER_W(AXIS_USER_WIDTH)
|
||||
) axis_desc_write (
|
||||
.aclk(ctrl_clk),
|
||||
.aresetn(rst_n)
|
||||
);
|
||||
|
||||
// testbench flat status -> DUT AXIS slave ports
|
||||
axis_flat_to_if #(
|
||||
.DATA_W(READ_STATUS_WIDTH),
|
||||
.KEEP_W(READ_STATUS_KEEP_W),
|
||||
.ID_W(AXIS_ID_WIDTH),
|
||||
.DEST_W(AXIS_DEST_WIDTH),
|
||||
.USER_W(AXIS_USER_WIDTH)
|
||||
) u_status_read_flat_to_if (
|
||||
.s_axis_tdata (status_read_cmd_in),
|
||||
.s_axis_tkeep ({READ_STATUS_KEEP_W{1'b1}}),
|
||||
.s_axis_tstrb ({READ_STATUS_KEEP_W{1'b1}}),
|
||||
.s_axis_tlast (1'b1),
|
||||
.s_axis_tid ('0),
|
||||
.s_axis_tdest ('0),
|
||||
.s_axis_tuser ('0),
|
||||
.s_axis_tvalid(valid_status_read),
|
||||
.s_axis_tready(ready_status_read),
|
||||
|
||||
.m_axis(axis_status_read)
|
||||
);
|
||||
|
||||
axis_flat_to_if #(
|
||||
.DATA_W(WRITE_STATUS_WIDTH),
|
||||
.KEEP_W(WRITE_STATUS_KEEP_W),
|
||||
.ID_W(AXIS_ID_WIDTH),
|
||||
.DEST_W(AXIS_DEST_WIDTH),
|
||||
.USER_W(AXIS_USER_WIDTH)
|
||||
) u_status_write_flat_to_if (
|
||||
.s_axis_tdata (status_write_cmd_in),
|
||||
.s_axis_tkeep ({WRITE_STATUS_KEEP_W{1'b1}}),
|
||||
.s_axis_tstrb ({WRITE_STATUS_KEEP_W{1'b1}}),
|
||||
.s_axis_tlast (1'b1),
|
||||
.s_axis_tid ('0),
|
||||
.s_axis_tdest ('0),
|
||||
.s_axis_tuser ('0),
|
||||
.s_axis_tvalid(valid_status_write),
|
||||
.s_axis_tready(ready_status_write),
|
||||
|
||||
.m_axis(axis_status_write)
|
||||
);
|
||||
|
||||
// DUT AXIS master ports -> testbench flat descriptor outputs
|
||||
logic [READ_DESC_KEEP_W-1:0] unused_desc_read_tkeep;
|
||||
logic [READ_DESC_KEEP_W-1:0] unused_desc_read_tstrb;
|
||||
logic unused_desc_read_tlast;
|
||||
logic [AXIS_ID_WIDTH-1:0] unused_desc_read_tid;
|
||||
logic [AXIS_DEST_WIDTH-1:0] unused_desc_read_tdest;
|
||||
logic [AXIS_USER_WIDTH-1:0] unused_desc_read_tuser;
|
||||
|
||||
axis_if_to_flat #(
|
||||
.DATA_W(READ_DESC_WIDTH),
|
||||
.KEEP_W(READ_DESC_KEEP_W),
|
||||
.ID_W(AXIS_ID_WIDTH),
|
||||
.DEST_W(AXIS_DEST_WIDTH),
|
||||
.USER_W(AXIS_USER_WIDTH)
|
||||
) u_desc_read_if_to_flat (
|
||||
.s_axis(axis_desc_read),
|
||||
|
||||
.m_axis_tdata (desc_read_cmd_out),
|
||||
.m_axis_tkeep (unused_desc_read_tkeep),
|
||||
.m_axis_tstrb (unused_desc_read_tstrb),
|
||||
.m_axis_tlast (unused_desc_read_tlast),
|
||||
.m_axis_tid (unused_desc_read_tid),
|
||||
.m_axis_tdest (unused_desc_read_tdest),
|
||||
.m_axis_tuser (unused_desc_read_tuser),
|
||||
.m_axis_tvalid(valid_desc_read),
|
||||
.m_axis_tready(ready_desc_read)
|
||||
);
|
||||
|
||||
logic [WRITE_DESC_KEEP_W-1:0] unused_desc_write_tkeep;
|
||||
logic [WRITE_DESC_KEEP_W-1:0] unused_desc_write_tstrb;
|
||||
logic unused_desc_write_tlast;
|
||||
logic [AXIS_ID_WIDTH-1:0] unused_desc_write_tid;
|
||||
logic [AXIS_DEST_WIDTH-1:0] unused_desc_write_tdest;
|
||||
logic [AXIS_USER_WIDTH-1:0] unused_desc_write_tuser;
|
||||
|
||||
axis_if_to_flat #(
|
||||
.DATA_W(WRITE_DESC_WIDTH),
|
||||
.KEEP_W(WRITE_DESC_KEEP_W),
|
||||
.ID_W(AXIS_ID_WIDTH),
|
||||
.DEST_W(AXIS_DEST_WIDTH),
|
||||
.USER_W(AXIS_USER_WIDTH)
|
||||
) u_desc_write_if_to_flat (
|
||||
.s_axis(axis_desc_write),
|
||||
|
||||
.m_axis_tdata (desc_write_cmd_out),
|
||||
.m_axis_tkeep (unused_desc_write_tkeep),
|
||||
.m_axis_tstrb (unused_desc_write_tstrb),
|
||||
.m_axis_tlast (unused_desc_write_tlast),
|
||||
.m_axis_tid (unused_desc_write_tid),
|
||||
.m_axis_tdest (unused_desc_write_tdest),
|
||||
.m_axis_tuser (unused_desc_write_tuser),
|
||||
.m_axis_tvalid(valid_desc_write),
|
||||
.m_axis_tready(ready_desc_write)
|
||||
);
|
||||
|
||||
// Controller ADC/DAC outputs.
|
||||
logic [31:0] adc_window_size;
|
||||
logic [31:0] dac_pulse_width;
|
||||
logic [31:0] dac_pulse_period;
|
||||
logic [DAC_DATA_WIDTH-1:0] dac_pulse_height;
|
||||
logic [15:0] dac_pulse_num;
|
||||
logic [31:0] adc_pulse_period;
|
||||
logic [15:0] adc_pulse_num;
|
||||
logic dac_start;
|
||||
logic adc_start;
|
||||
logic dac_rst;
|
||||
logic adc_rst;
|
||||
|
||||
controller_wrapper_axil #(
|
||||
.ADDR_W(ADDR_W),
|
||||
.DATA_W(DATA_W),
|
||||
.USER_W(USER_W),
|
||||
.DAC_DATA_WIDTH(DAC_DATA_WIDTH),
|
||||
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
|
||||
.AXIS_ID_WIDTH(AXIS_ID_WIDTH),
|
||||
.LEN_WIDTH(LEN_WIDTH),
|
||||
.AXIS_USER_WIDTH(AXIS_USER_WIDTH),
|
||||
.AXIS_DEST_WIDTH(AXIS_DEST_WIDTH),
|
||||
.TAG_WIDTH(TAG_WIDTH),
|
||||
.READ_DESC_WIDTH(READ_DESC_WIDTH),
|
||||
.WRITE_DESC_WIDTH(WRITE_DESC_WIDTH),
|
||||
.READ_STATUS_WIDTH(READ_STATUS_WIDTH),
|
||||
.WRITE_STATUS_WIDTH(WRITE_STATUS_WIDTH)
|
||||
) dut (
|
||||
.ctrl_clk(ctrl_clk),
|
||||
.dac_clk_in(dac_clk_in),
|
||||
.adc_clk_in(adc_clk_in),
|
||||
.rst_n(rst_n),
|
||||
.s_axil(axil_bus),
|
||||
|
||||
.finish(finish),
|
||||
.adc_window_size(adc_window_size),
|
||||
|
||||
.dac_pulse_width(dac_pulse_width),
|
||||
.dac_pulse_period(dac_pulse_period),
|
||||
.dac_pulse_height(dac_pulse_height),
|
||||
.dac_pulse_num(dac_pulse_num),
|
||||
|
||||
.adc_pulse_period(adc_pulse_period),
|
||||
.adc_pulse_num(adc_pulse_num),
|
||||
|
||||
.dac_start(dac_start),
|
||||
.adc_start(adc_start),
|
||||
.dac_rst(dac_rst),
|
||||
.adc_rst(adc_rst),
|
||||
|
||||
.s_axis_status_read(axis_status_read),
|
||||
.s_axis_status_write(axis_status_write),
|
||||
|
||||
.m_axis_desc_read(axis_desc_read),
|
||||
.m_axis_desc_write(axis_desc_write)
|
||||
);
|
||||
|
||||
endmodule : tb_controller_wrapper_axil
|
||||
170
rtl/controller/tests/test_controller.py
Normal file
170
rtl/controller/tests/test_controller.py
Normal file
@ -0,0 +1,170 @@
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.handle import Immediate
|
||||
from cocotb.triggers import RisingEdge
|
||||
from cocotbext.axi import AxiLiteBus, AxiLiteMaster
|
||||
|
||||
|
||||
# Register indexes from axi4l_reg_map_controller_pkg.sv
|
||||
REG_CONTROL = 0
|
||||
REG_STATUS = 1
|
||||
REG_DAC_WIDTH = 2
|
||||
REG_DAC_PERIOD = 3
|
||||
REG_DAC_PULSE_NUM = 4
|
||||
REG_DAC_PULSE_HEIGHT = 5
|
||||
REG_ADC_PERIOD = 6
|
||||
REG_WINDOW_SIZE = 7
|
||||
REG_ERROR = 8
|
||||
REG_DESC_READ_ADDR = 9
|
||||
REG_DESC_READ_LEN = 10
|
||||
REG_DESC_READ_CONFIG = 11
|
||||
REG_READ_STATUS = 12
|
||||
REG_DESC_WRITE_ADDR = 13
|
||||
REG_DESC_WRITE_LEN_AND_TAG = 14
|
||||
REG_STATUS_WRITE_LEN = 15
|
||||
REG_STATUS_WRITE_CONFIG = 16
|
||||
|
||||
|
||||
# REG_CONTROL pulse bits
|
||||
CTRL_START = 0
|
||||
CTRL_RST_SOFT = 1
|
||||
CTRL_CFG_BUS_VALID = 2
|
||||
CTRL_SEND_DESC_READ = 3
|
||||
CTRL_SEND_DESC_WRITE = 4
|
||||
CTRL_TAKE_STATUS_READ = 5
|
||||
CTRL_TAKE_STATUS_WRITE = 6
|
||||
|
||||
|
||||
def reg_addr(reg_index: int) -> int:
|
||||
# AXI-Lite uses byte addresses, 32-bit registers are spaced by 4 bytes.
|
||||
return reg_index * 4
|
||||
|
||||
|
||||
def u32(value: int) -> bytes:
|
||||
return int(value & 0xFFFFFFFF).to_bytes(4, "little")
|
||||
|
||||
|
||||
class TB:
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
cocotb.start_soon(Clock(dut.ctrl_clk, 10, units="ns").start())
|
||||
|
||||
self.axil = AxiLiteMaster(
|
||||
AxiLiteBus.from_prefix(dut, "s_axil"),
|
||||
dut.ctrl_clk,
|
||||
dut.rst,
|
||||
)
|
||||
|
||||
async def reset(self):
|
||||
self.dut.rst.value = 1
|
||||
for _ in range(5):
|
||||
await RisingEdge(self.dut.ctrl_clk)
|
||||
|
||||
self.dut.rst.value = 0
|
||||
for _ in range(5):
|
||||
await RisingEdge(self.dut.ctrl_clk)
|
||||
|
||||
async def write_reg(self, reg_index: int, value: int):
|
||||
await self.axil.write(reg_addr(reg_index), u32(value))
|
||||
|
||||
async def read_reg(self, reg_index: int) -> int:
|
||||
resp = await self.axil.read(reg_addr(reg_index), 4)
|
||||
return int.from_bytes(bytes(resp.data), "little")
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def simple_axil_write_read(dut):
|
||||
tb = TB(dut)
|
||||
await tb.reset()
|
||||
|
||||
await tb.write_reg(REG_DAC_WIDTH, 0x0000_0123)
|
||||
|
||||
value = await tb.read_reg(REG_DAC_WIDTH)
|
||||
assert value == 0x0000_0123
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def simple_controller_config_write(dut):
|
||||
tb = TB(dut)
|
||||
await tb.reset()
|
||||
|
||||
await tb.write_reg(REG_DAC_WIDTH, 0x10)
|
||||
await tb.write_reg(REG_DAC_PERIOD, 0x40)
|
||||
await tb.write_reg(REG_DAC_PULSE_NUM, 3)
|
||||
await tb.write_reg(REG_DAC_PULSE_HEIGHT, 0x7FF)
|
||||
await tb.write_reg(REG_ADC_PERIOD, 0x80)
|
||||
await tb.write_reg(REG_WINDOW_SIZE, 16)
|
||||
|
||||
assert await tb.read_reg(REG_DAC_WIDTH) == 0x10
|
||||
assert await tb.read_reg(REG_WINDOW_SIZE) == 16
|
||||
|
||||
# write data: set cfg_bus_valid signal
|
||||
await tb.write_reg(REG_CONTROL, 1 << CTRL_CFG_BUS_VALID)
|
||||
|
||||
# wait
|
||||
for _ in range(30):
|
||||
await RisingEdge(dut.ctrl_clk)
|
||||
|
||||
# check config
|
||||
assert int(dut.dac_pulse_width) == 0x10
|
||||
assert int(dut.dac_pulse_period) == 0x40
|
||||
assert int(dut.dac_pulse_num) == 3
|
||||
assert int(dut.dac_pulse_height) == 0x7FF
|
||||
assert int(dut.adc_pulse_period) == 0x80
|
||||
assert int(dut.adc_window_size) == 16
|
||||
|
||||
await RisingEdge(dut.ctrl_clk)
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def simple_controller_start_check(dut):
|
||||
tb = TB(dut)
|
||||
await tb.reset()
|
||||
await tb.write_reg(REG_CONTROL, 1 << CTRL_START)
|
||||
|
||||
await RisingEdge(dut.dac_start)
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def simple_dma_desc_status(dut):
|
||||
tb = TB(dut)
|
||||
await tb.reset()
|
||||
|
||||
await tb.write_reg(REG_DESC_READ_ADDR, 0xdead)
|
||||
await tb.write_reg(REG_DESC_READ_LEN, 64)
|
||||
await tb.write_reg(REG_DESC_READ_CONFIG, 0x0000_0001)
|
||||
|
||||
await tb.write_reg(REG_DESC_WRITE_ADDR, 0xbeef)
|
||||
await tb.write_reg(REG_DESC_WRITE_LEN_AND_TAG, 0x0005555)
|
||||
|
||||
# W1S pulse: bit 3 = send_desc_read_o.
|
||||
await tb.write_reg(REG_CONTROL, 1 << CTRL_SEND_DESC_READ)
|
||||
|
||||
await tb.write_reg(REG_CONTROL, 1 << CTRL_SEND_DESC_WRITE)
|
||||
|
||||
for _ in range(20):
|
||||
await RisingEdge(dut.ctrl_clk)
|
||||
|
||||
assert int(dut.desc_read_cmd_out.value) == 0x000000100040DEAD
|
||||
assert int(dut.desc_write_cmd_out.value) == 0x0005555BEEF
|
||||
|
||||
# test status
|
||||
dut.status_read_cmd_in.value = Immediate(123)
|
||||
dut.status_write_cmd_in.value = Immediate(0xabcd90012345)
|
||||
dut.valid_status_read.value = Immediate(1)
|
||||
dut.valid_status_write.value = Immediate(1)
|
||||
|
||||
for _ in range(10):
|
||||
await RisingEdge(dut.ctrl_clk)
|
||||
|
||||
# read status
|
||||
await tb.write_reg(REG_CONTROL, 1 << CTRL_TAKE_STATUS_READ)
|
||||
await tb.write_reg(REG_CONTROL, 1 << CTRL_TAKE_STATUS_WRITE)
|
||||
|
||||
for _ in range(10):
|
||||
await RisingEdge(dut.ctrl_clk)
|
||||
|
||||
assert await tb.read_reg(REG_READ_STATUS) == 123
|
||||
assert await tb.read_reg(REG_STATUS_WRITE_CONFIG) == 0xABCD900
|
||||
assert await tb.read_reg(REG_STATUS_WRITE_LEN) == 0x12345
|
||||
Reference in New Issue
Block a user