docs: add controller READMEs

.gitignore

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+**build**
+
+# vivado project exclude
+**.hw
+**.ip_user_files
+**.cache
+**.gen
+**.runs
+**.sim
+**.srcs
+*.jou
+*.log
+*.rpt
+*.dcp
+*.xpr
+.Xil
+xvlog.pb
+*vivado_pid*
+
+# some generated files (they annoy me)
+update_config.tcl
+create_project.tcl
+gen_ip.tcl
+defines.v
+run_sim.tcl

constraints/ax7a035b.xdc

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+# === iostandard ===
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+
+# === SPI flash config ===
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
+set_property CONFIG_MODE SPIx4 [current_design]
+set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
+
+# === clock config ===
+create_clock -period 5.000 [get_ports sys_clk_p]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_p]
+set_property PACKAGE_PIN R4 [get_ports sys_clk_p]
+set_property PACKAGE_PIN T4 [get_ports sys_clk_n]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_n]
+
+
+# === reset button ===
+set_property PACKAGE_PIN F15 [get_ports rst_n]
+set_property IOSTANDARD LVCMOS33 [get_ports rst_n]
+
+# === status leds ===
+set_property PACKAGE_PIN L13 [get_ports {led[0]}]
+set_property PACKAGE_PIN M13 [get_ports {led[1]}]
+set_property PACKAGE_PIN K14 [get_ports {led[2]}]
+set_property PACKAGE_PIN K13 [get_ports {led[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[*]}]
+
+# === 1Gb ethernet PHY ===
+set_property PACKAGE_PIN P15 [get_ports rgmii_txc]
+set_property PACKAGE_PIN N14 [get_ports {rgmii_txd[0]}]
+set_property PACKAGE_PIN P16 [get_ports {rgmii_txd[1]}]
+set_property PACKAGE_PIN R17 [get_ports {rgmii_txd[2]}]
+set_property PACKAGE_PIN R16 [get_ports {rgmii_txd[3]}]
+set_property PACKAGE_PIN N17 [get_ports rgmii_txctl]
+set_property PACKAGE_PIN V18 [get_ports rgmii_rxc]
+set_property PACKAGE_PIN P19 [get_ports {rgmii_rxd[0]}]
+set_property PACKAGE_PIN U18 [get_ports {rgmii_rxd[1]}]
+set_property PACKAGE_PIN U17 [get_ports {rgmii_rxd[2]}]
+set_property PACKAGE_PIN P17 [get_ports {rgmii_rxd[3]}]
+set_property PACKAGE_PIN R19 [get_ports rgmii_rxctl]
+set_property PACKAGE_PIN N13 [get_ports e_mdc]
+set_property PACKAGE_PIN P14 [get_ports e_mdio]
+set_property PACKAGE_PIN R14 [get_ports e_reset]
+
+set_property IOSTANDARD LVCMOS33 [get_ports rgmii_txc]
+set_property IOSTANDARD LVCMOS33 [get_ports {rgmii_txd[*]}]
+set_property IOSTANDARD LVCMOS33 [get_ports rgmii_txctl]
+set_property IOSTANDARD LVCMOS33 [get_ports rgmii_rxc]
+set_property IOSTANDARD LVCMOS33 [get_ports {rgmii_rxd[*]}]
+set_property IOSTANDARD LVCMOS33 [get_ports rgmii_rxctl]
+set_property IOSTANDARD LVCMOS33 [get_ports e_mdc]
+set_property IOSTANDARD LVCMOS33 [get_ports e_mdio]
+set_property IOSTANDARD LVCMOS33 [get_ports e_reset]
+
+set_property SLEW FAST [get_ports rgmii_txc]
+set_property SLEW FAST [get_ports rgmii_txctl]
+set_property SLEW FAST [get_ports {rgmii_txd[*]}]
+create_clock -period 8.000 [get_ports rgmii_rxc]
+
+# === ADC an9238 (J11 header) ===
+set_property PACKAGE_PIN G21 [get_ports ch2_clk]
+set_property PACKAGE_PIN G22 [get_ports ch2_data[0]]
+set_property PACKAGE_PIN C22 [get_ports ch2_data[1]]
+set_property PACKAGE_PIN B22 [get_ports ch2_data[2]]
+set_property PACKAGE_PIN F19 [get_ports ch2_data[3]]
+set_property PACKAGE_PIN F20 [get_ports ch2_data[4]]
+set_property PACKAGE_PIN D20 [get_ports ch2_data[5]]
+set_property PACKAGE_PIN C20 [get_ports ch2_data[6]]
+set_property PACKAGE_PIN A18 [get_ports ch2_data[7]]
+set_property PACKAGE_PIN A19 [get_ports ch2_data[8]]
+set_property PACKAGE_PIN B20 [get_ports ch2_data[9]]
+set_property PACKAGE_PIN A20 [get_ports ch2_data[10]]
+set_property PACKAGE_PIN F18 [get_ports ch2_data[11]]
+set_property PACKAGE_PIN E18 [get_ports ch2_otr]
+set_property PACKAGE_PIN C18 [get_ports ch1_data[1]]
+set_property PACKAGE_PIN C19 [get_ports ch1_data[0]]
+set_property PACKAGE_PIN B17 [get_ports ch1_data[3]]
+set_property PACKAGE_PIN B18 [get_ports ch1_data[2]]
+set_property PACKAGE_PIN D17 [get_ports ch1_data[5]]
+set_property PACKAGE_PIN C17 [get_ports ch1_data[4]]
+set_property PACKAGE_PIN A15 [get_ports ch1_data[7]]
+set_property PACKAGE_PIN A16 [get_ports ch1_data[6]]
+set_property PACKAGE_PIN B15 [get_ports ch1_data[9]]
+set_property PACKAGE_PIN B16 [get_ports ch1_data[8]]
+set_property PACKAGE_PIN A13 [get_ports ch1_data[11]]
+set_property PACKAGE_PIN A14 [get_ports ch1_data[10]]
+set_property PACKAGE_PIN E16 [get_ports ch1_clk]
+set_property PACKAGE_PIN D16 [get_ports ch1_otr]
+
+set_property IOSTANDARD LVCMOS33 [get_ports ch2_clk]
+set_property IOSTANDARD LVCMOS33 [get_ports {ch2_data[*]}]
+set_property IOSTANDARD LVCMOS33 [get_ports ch2_otr]
+set_property IOSTANDARD LVCMOS33 [get_ports {ch1_data[*]}]
+set_property IOSTANDARD LVCMOS33 [get_ports ch1_clk]
+set_property IOSTANDARD LVCMOS33 [get_ports ch1_otr]
+
+set_property SLEW FAST [get_ports {ch2_clk ch1_clk}]
+
+# === DAC an9767 (J13 header) ===
+set_property PACKAGE_PIN AA9 [get_ports p2_clk]
+set_property PACKAGE_PIN AB10 [get_ports p2_wrt]
+set_property PACKAGE_PIN U16 [get_ports p2_data[13]]
+set_property PACKAGE_PIN T16 [get_ports p2_data[12]]
+set_property PACKAGE_PIN AA13 [get_ports p2_data[11]]
+set_property PACKAGE_PIN AB13 [get_ports p2_data[10]]
+set_property PACKAGE_PIN AB11 [get_ports p2_data[9]]
+set_property PACKAGE_PIN AB12 [get_ports p2_data[8]]
+set_property PACKAGE_PIN Y13 [get_ports p2_data[7]]
+set_property PACKAGE_PIN AA14 [get_ports p2_data[6]]
+set_property PACKAGE_PIN W14 [get_ports p2_data[5]]
+set_property PACKAGE_PIN Y14 [get_ports p2_data[4]]
+set_property PACKAGE_PIN Y16 [get_ports p2_data[3]]
+set_property PACKAGE_PIN AA16 [get_ports p2_data[2]]
+set_property PACKAGE_PIN AB16 [get_ports p2_data[1]]
+set_property PACKAGE_PIN AB17 [get_ports p2_data[0]]
+
+set_property IOSTANDARD LVCMOS33 [get_ports p2_clk]
+set_property IOSTANDARD LVCMOS33 [get_ports p2_wrt]
+set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[*]}]
+
+set_property SLEW FAST [get_ports {p2_clk}]
+
+

designs/README.md

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+# Директория с тестовыми проектами под ПЛИСу
+
+- eth_ctrl_debug: проект с ethernet и контроллером. Позволяет через ILA проверить, что пакет правильно принимается и что значения правильно выставляются.

designs/eth_ctrl_debug/Makefile

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+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# FPGA settings
+FPGA_PART = xc7a35tfgg484-1
+FPGA_TOP = eth_ctrl_debug_top
+FPGA_ARCH = artix7
+
+RTL_DIR = ../../rtl
+
+
+include ../../scripts/vivado.mk
+
+SYN_FILES += eth_ctrl_debug.sv
+SYN_FILES += $(sort $(shell find ../../rtl -type f \( -name '*.v' -o -name '*.sv' \)))
+
+XCI_FILES = $(sort $(shell find ../../rtl/ethernet-udp/src -type f -name '*.xci'))
+XCI_FILES += $(sort $(shell find ip/ -type f -name '*.xci'))
+
+XDC_FILES += ../../constraints/ax7a035b.xdc
+XDC_FILES += debug.xdc
+
+
+
+program: $(PROJECT).bit
+	echo "open_hw_manager" > program.tcl
+	echo "connect_hw_server" >> program.tcl
+	echo "open_hw_target" >> program.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+	echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
+	echo "program_hw_devices [current_hw_device]" >> program.tcl
+	echo "exit" >> program.tcl
+	vivado -nojournal -nolog -mode batch -source program.tcl
+
+$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
+	echo "write_cfgmem -force -format mcs -size 16 -interface SPIx4 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
+	echo "exit" >> generate_mcs.tcl
+	vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	for x in .mcs .prm; \
+	do cp $*$$x rev/$*_rev$$COUNT$$x; \
+	echo "Output: rev/$*_rev$$COUNT$$x"; done;

designs/eth_ctrl_debug/README.md

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+# Тестовый проект Eth + CTRL
+Проект состоит из AXIS Ethernet и контроллера. Для тестирования сделано три разных частотных домена: ethernet 125MHz, DAC 130MHz, ADC 65MHz для тестирования сихронизации. Есть ILA на все выходы контроллера и на шину AXIS eth -> ctrl. Для отправки пакетов используйте скрипт ```console.py --debug```.
+
+## Сборка
+```make all``` - собрать все до битстрима
+
+```make vivado``` - открыть проект в Vivado

designs/eth_ctrl_debug/debug.xdc

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+set_clock_groups -name ASYNC_UDP_CTRL -asynchronous -group [get_clocks rgmii_rxc] -group [get_clocks clk_out1_clk_wiz_ctrl_inst] -group [get_clocks clk_out2_clk_wiz_ctrl_inst]
+
+
+
+
+create_debug_core u_ila_0 ila
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
+set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
+set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
+set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
+set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
+set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
+set_property port_width 1 [get_debug_ports u_ila_0/clk]
+connect_debug_port u_ila_0/clk [get_nets [list clk_wiz_ctrl_inst/inst/clk_out2]]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
+set_property port_width 32 [get_debug_ports u_ila_0/probe0]
+connect_debug_port u_ila_0/probe0 [get_nets [list {adc_pulse_period_dbg[0]} {adc_pulse_period_dbg[1]} {adc_pulse_period_dbg[2]} {adc_pulse_period_dbg[3]} {adc_pulse_period_dbg[4]} {adc_pulse_period_dbg[5]} {adc_pulse_period_dbg[6]} {adc_pulse_period_dbg[7]} {adc_pulse_period_dbg[8]} {adc_pulse_period_dbg[9]} {adc_pulse_period_dbg[10]} {adc_pulse_period_dbg[11]} {adc_pulse_period_dbg[12]} {adc_pulse_period_dbg[13]} {adc_pulse_period_dbg[14]} {adc_pulse_period_dbg[15]} {adc_pulse_period_dbg[16]} {adc_pulse_period_dbg[17]} {adc_pulse_period_dbg[18]} {adc_pulse_period_dbg[19]} {adc_pulse_period_dbg[20]} {adc_pulse_period_dbg[21]} {adc_pulse_period_dbg[22]} {adc_pulse_period_dbg[23]} {adc_pulse_period_dbg[24]} {adc_pulse_period_dbg[25]} {adc_pulse_period_dbg[26]} {adc_pulse_period_dbg[27]} {adc_pulse_period_dbg[28]} {adc_pulse_period_dbg[29]} {adc_pulse_period_dbg[30]} {adc_pulse_period_dbg[31]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
+set_property port_width 8 [get_debug_ports u_ila_0/probe1]
+connect_debug_port u_ila_0/probe1 [get_nets [list {finish_cnt[0]} {finish_cnt[1]} {finish_cnt[2]} {finish_cnt[3]} {finish_cnt[4]} {finish_cnt[5]} {finish_cnt[6]} {finish_cnt[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
+set_property port_width 16 [get_debug_ports u_ila_0/probe2]
+connect_debug_port u_ila_0/probe2 [get_nets [list {adc_pulse_num_dbg[0]} {adc_pulse_num_dbg[1]} {adc_pulse_num_dbg[2]} {adc_pulse_num_dbg[3]} {adc_pulse_num_dbg[4]} {adc_pulse_num_dbg[5]} {adc_pulse_num_dbg[6]} {adc_pulse_num_dbg[7]} {adc_pulse_num_dbg[8]} {adc_pulse_num_dbg[9]} {adc_pulse_num_dbg[10]} {adc_pulse_num_dbg[11]} {adc_pulse_num_dbg[12]} {adc_pulse_num_dbg[13]} {adc_pulse_num_dbg[14]} {adc_pulse_num_dbg[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
+set_property port_width 1 [get_debug_ports u_ila_0/probe3]
+connect_debug_port u_ila_0/probe3 [get_nets [list adc_rst_dbg]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
+set_property port_width 1 [get_debug_ports u_ila_0/probe4]
+connect_debug_port u_ila_0/probe4 [get_nets [list adc_start_dbg]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
+set_property port_width 1 [get_debug_ports u_ila_0/probe5]
+connect_debug_port u_ila_0/probe5 [get_nets [list finish_dbg]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
+set_property port_width 1 [get_debug_ports u_ila_0/probe6]
+connect_debug_port u_ila_0/probe6 [get_nets [list finish_pending]]
+create_debug_core u_ila_1 ila
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_1]
+set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_1]
+set_property C_ADV_TRIGGER false [get_debug_cores u_ila_1]
+set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_1]
+set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_1]
+set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_1]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_1]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_1]
+set_property port_width 1 [get_debug_ports u_ila_1/clk]
+connect_debug_port u_ila_1/clk [get_nets [list rgmii_rxc_IBUF_BUFG]]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe0]
+set_property port_width 2 [get_debug_ports u_ila_1/probe0]
+connect_debug_port u_ila_1/probe0 [get_nets [list {axis_mac0/rx_state[0]} {axis_mac0/rx_state[1]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe1]
+set_property port_width 16 [get_debug_ports u_ila_1/probe1]
+connect_debug_port u_ila_1/probe1 [get_nets [list {axis_mac0/udp_rec_data_length[0]} {axis_mac0/udp_rec_data_length[1]} {axis_mac0/udp_rec_data_length[2]} {axis_mac0/udp_rec_data_length[3]} {axis_mac0/udp_rec_data_length[4]} {axis_mac0/udp_rec_data_length[5]} {axis_mac0/udp_rec_data_length[6]} {axis_mac0/udp_rec_data_length[7]} {axis_mac0/udp_rec_data_length[8]} {axis_mac0/udp_rec_data_length[9]} {axis_mac0/udp_rec_data_length[10]} {axis_mac0/udp_rec_data_length[11]} {axis_mac0/udp_rec_data_length[12]} {axis_mac0/udp_rec_data_length[13]} {axis_mac0/udp_rec_data_length[14]} {axis_mac0/udp_rec_data_length[15]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe2]
+set_property port_width 96 [get_debug_ports u_ila_1/probe2]
+connect_debug_port u_ila_1/probe2 [get_nets [list {udp_ctrl_inst/cfg_bus_eth[0]} {udp_ctrl_inst/cfg_bus_eth[1]} {udp_ctrl_inst/cfg_bus_eth[2]} {udp_ctrl_inst/cfg_bus_eth[3]} {udp_ctrl_inst/cfg_bus_eth[4]} {udp_ctrl_inst/cfg_bus_eth[5]} {udp_ctrl_inst/cfg_bus_eth[6]} {udp_ctrl_inst/cfg_bus_eth[7]} {udp_ctrl_inst/cfg_bus_eth[8]} {udp_ctrl_inst/cfg_bus_eth[9]} {udp_ctrl_inst/cfg_bus_eth[10]} {udp_ctrl_inst/cfg_bus_eth[11]} {udp_ctrl_inst/cfg_bus_eth[12]} {udp_ctrl_inst/cfg_bus_eth[13]} {udp_ctrl_inst/cfg_bus_eth[14]} {udp_ctrl_inst/cfg_bus_eth[15]} {udp_ctrl_inst/cfg_bus_eth[16]} {udp_ctrl_inst/cfg_bus_eth[17]} {udp_ctrl_inst/cfg_bus_eth[18]} {udp_ctrl_inst/cfg_bus_eth[19]} {udp_ctrl_inst/cfg_bus_eth[20]} {udp_ctrl_inst/cfg_bus_eth[21]} {udp_ctrl_inst/cfg_bus_eth[22]} {udp_ctrl_inst/cfg_bus_eth[23]} {udp_ctrl_inst/cfg_bus_eth[24]} {udp_ctrl_inst/cfg_bus_eth[25]} {udp_ctrl_inst/cfg_bus_eth[26]} {udp_ctrl_inst/cfg_bus_eth[27]} {udp_ctrl_inst/cfg_bus_eth[28]} {udp_ctrl_inst/cfg_bus_eth[29]} {udp_ctrl_inst/cfg_bus_eth[30]} {udp_ctrl_inst/cfg_bus_eth[31]} {udp_ctrl_inst/cfg_bus_eth[32]} {udp_ctrl_inst/cfg_bus_eth[33]} {udp_ctrl_inst/cfg_bus_eth[34]} {udp_ctrl_inst/cfg_bus_eth[35]} {udp_ctrl_inst/cfg_bus_eth[36]} {udp_ctrl_inst/cfg_bus_eth[37]} {udp_ctrl_inst/cfg_bus_eth[38]} {udp_ctrl_inst/cfg_bus_eth[39]} {udp_ctrl_inst/cfg_bus_eth[40]} {udp_ctrl_inst/cfg_bus_eth[41]} {udp_ctrl_inst/cfg_bus_eth[42]} {udp_ctrl_inst/cfg_bus_eth[43]} {udp_ctrl_inst/cfg_bus_eth[44]} {udp_ctrl_inst/cfg_bus_eth[45]} {udp_ctrl_inst/cfg_bus_eth[46]} {udp_ctrl_inst/cfg_bus_eth[47]} {udp_ctrl_inst/cfg_bus_eth[48]} {udp_ctrl_inst/cfg_bus_eth[49]} {udp_ctrl_inst/cfg_bus_eth[50]} {udp_ctrl_inst/cfg_bus_eth[51]} {udp_ctrl_inst/cfg_bus_eth[52]} {udp_ctrl_inst/cfg_bus_eth[53]} {udp_ctrl_inst/cfg_bus_eth[54]} {udp_ctrl_inst/cfg_bus_eth[55]} {udp_ctrl_inst/cfg_bus_eth[56]} {udp_ctrl_inst/cfg_bus_eth[57]} {udp_ctrl_inst/cfg_bus_eth[58]} {udp_ctrl_inst/cfg_bus_eth[59]} {udp_ctrl_inst/cfg_bus_eth[60]} {udp_ctrl_inst/cfg_bus_eth[61]} {udp_ctrl_inst/cfg_bus_eth[62]} {udp_ctrl_inst/cfg_bus_eth[63]} {udp_ctrl_inst/cfg_bus_eth[64]} {udp_ctrl_inst/cfg_bus_eth[65]} {udp_ctrl_inst/cfg_bus_eth[66]} {udp_ctrl_inst/cfg_bus_eth[67]} {udp_ctrl_inst/cfg_bus_eth[68]} {udp_ctrl_inst/cfg_bus_eth[69]} {udp_ctrl_inst/cfg_bus_eth[70]} {udp_ctrl_inst/cfg_bus_eth[71]} {udp_ctrl_inst/cfg_bus_eth[72]} {udp_ctrl_inst/cfg_bus_eth[73]} {udp_ctrl_inst/cfg_bus_eth[74]} {udp_ctrl_inst/cfg_bus_eth[75]} {udp_ctrl_inst/cfg_bus_eth[76]} {udp_ctrl_inst/cfg_bus_eth[77]} {udp_ctrl_inst/cfg_bus_eth[78]} {udp_ctrl_inst/cfg_bus_eth[79]} {udp_ctrl_inst/cfg_bus_eth[80]} {udp_ctrl_inst/cfg_bus_eth[81]} {udp_ctrl_inst/cfg_bus_eth[82]} {udp_ctrl_inst/cfg_bus_eth[83]} {udp_ctrl_inst/cfg_bus_eth[84]} {udp_ctrl_inst/cfg_bus_eth[85]} {udp_ctrl_inst/cfg_bus_eth[86]} {udp_ctrl_inst/cfg_bus_eth[87]} {udp_ctrl_inst/cfg_bus_eth[88]} {udp_ctrl_inst/cfg_bus_eth[89]} {udp_ctrl_inst/cfg_bus_eth[90]} {udp_ctrl_inst/cfg_bus_eth[91]} {udp_ctrl_inst/cfg_bus_eth[92]} {udp_ctrl_inst/cfg_bus_eth[93]} {udp_ctrl_inst/cfg_bus_eth[94]} {udp_ctrl_inst/cfg_bus_eth[95]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe3]
+set_property port_width 16 [get_debug_ports u_ila_1/probe3]
+connect_debug_port u_ila_1/probe3 [get_nets [list {axis_mac0/rx_payload_len[0]} {axis_mac0/rx_payload_len[1]} {axis_mac0/rx_payload_len[2]} {axis_mac0/rx_payload_len[3]} {axis_mac0/rx_payload_len[4]} {axis_mac0/rx_payload_len[5]} {axis_mac0/rx_payload_len[6]} {axis_mac0/rx_payload_len[7]} {axis_mac0/rx_payload_len[8]} {axis_mac0/rx_payload_len[9]} {axis_mac0/rx_payload_len[10]} {axis_mac0/rx_payload_len[11]} {axis_mac0/rx_payload_len[12]} {axis_mac0/rx_payload_len[13]} {axis_mac0/rx_payload_len[14]} {axis_mac0/rx_payload_len[15]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe4]
+set_property port_width 8 [get_debug_ports u_ila_1/probe4]
+connect_debug_port u_ila_1/probe4 [get_nets [list {m_axis_rx_tdata[0]} {m_axis_rx_tdata[1]} {m_axis_rx_tdata[2]} {m_axis_rx_tdata[3]} {m_axis_rx_tdata[4]} {m_axis_rx_tdata[5]} {m_axis_rx_tdata[6]} {m_axis_rx_tdata[7]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe5]
+set_property port_width 3 [get_debug_ports u_ila_1/probe5]
+connect_debug_port u_ila_1/probe5 [get_nets [list {udp_ctrl_inst/eth_state[0]} {udp_ctrl_inst/eth_state[1]} {udp_ctrl_inst/eth_state[2]}]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe6]
+set_property port_width 1 [get_debug_ports u_ila_1/probe6]
+connect_debug_port u_ila_1/probe6 [get_nets [list axis_mac0/arp_found]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe7]
+set_property port_width 1 [get_debug_ports u_ila_1/probe7]
+connect_debug_port u_ila_1/probe7 [get_nets [list udp_ctrl_inst/axis_hs]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe8]
+set_property port_width 1 [get_debug_ports u_ila_1/probe8]
+connect_debug_port u_ila_1/probe8 [get_nets [list udp_ctrl_inst/busy_flag_eth]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe9]
+set_property port_width 1 [get_debug_ports u_ila_1/probe9]
+connect_debug_port u_ila_1/probe9 [get_nets [list axis_mac0/m_axis_rx_tlast]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe10]
+set_property port_width 1 [get_debug_ports u_ila_1/probe10]
+connect_debug_port u_ila_1/probe10 [get_nets [list m_axis_rx_tlast]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe11]
+set_property port_width 1 [get_debug_ports u_ila_1/probe11]
+connect_debug_port u_ila_1/probe11 [get_nets [list axis_mac0/m_axis_rx_tready]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe12]
+set_property port_width 1 [get_debug_ports u_ila_1/probe12]
+connect_debug_port u_ila_1/probe12 [get_nets [list m_axis_rx_tready]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe13]
+set_property port_width 1 [get_debug_ports u_ila_1/probe13]
+connect_debug_port u_ila_1/probe13 [get_nets [list axis_mac0/req_ready]]
+create_debug_core u_ila_2 ila
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_2]
+set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_2]
+set_property C_ADV_TRIGGER false [get_debug_cores u_ila_2]
+set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_2]
+set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_2]
+set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_2]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_2]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_2]
+set_property port_width 1 [get_debug_ports u_ila_2/clk]
+connect_debug_port u_ila_2/clk [get_nets [list clk_wiz_ctrl_inst/inst/clk_out1]]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe0]
+set_property port_width 12 [get_debug_ports u_ila_2/probe0]
+connect_debug_port u_ila_2/probe0 [get_nets [list {dac_pulse_height_dbg[0]} {dac_pulse_height_dbg[1]} {dac_pulse_height_dbg[2]} {dac_pulse_height_dbg[3]} {dac_pulse_height_dbg[4]} {dac_pulse_height_dbg[5]} {dac_pulse_height_dbg[6]} {dac_pulse_height_dbg[7]} {dac_pulse_height_dbg[8]} {dac_pulse_height_dbg[9]} {dac_pulse_height_dbg[10]} {dac_pulse_height_dbg[11]}]]
+create_debug_port u_ila_2 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe1]
+set_property port_width 16 [get_debug_ports u_ila_2/probe1]
+connect_debug_port u_ila_2/probe1 [get_nets [list {dac_pulse_num_dbg[0]} {dac_pulse_num_dbg[1]} {dac_pulse_num_dbg[2]} {dac_pulse_num_dbg[3]} {dac_pulse_num_dbg[4]} {dac_pulse_num_dbg[5]} {dac_pulse_num_dbg[6]} {dac_pulse_num_dbg[7]} {dac_pulse_num_dbg[8]} {dac_pulse_num_dbg[9]} {dac_pulse_num_dbg[10]} {dac_pulse_num_dbg[11]} {dac_pulse_num_dbg[12]} {dac_pulse_num_dbg[13]} {dac_pulse_num_dbg[14]} {dac_pulse_num_dbg[15]}]]
+create_debug_port u_ila_2 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe2]
+set_property port_width 32 [get_debug_ports u_ila_2/probe2]
+connect_debug_port u_ila_2/probe2 [get_nets [list {dac_pulse_period_dbg[0]} {dac_pulse_period_dbg[1]} {dac_pulse_period_dbg[2]} {dac_pulse_period_dbg[3]} {dac_pulse_period_dbg[4]} {dac_pulse_period_dbg[5]} {dac_pulse_period_dbg[6]} {dac_pulse_period_dbg[7]} {dac_pulse_period_dbg[8]} {dac_pulse_period_dbg[9]} {dac_pulse_period_dbg[10]} {dac_pulse_period_dbg[11]} {dac_pulse_period_dbg[12]} {dac_pulse_period_dbg[13]} {dac_pulse_period_dbg[14]} {dac_pulse_period_dbg[15]} {dac_pulse_period_dbg[16]} {dac_pulse_period_dbg[17]} {dac_pulse_period_dbg[18]} {dac_pulse_period_dbg[19]} {dac_pulse_period_dbg[20]} {dac_pulse_period_dbg[21]} {dac_pulse_period_dbg[22]} {dac_pulse_period_dbg[23]} {dac_pulse_period_dbg[24]} {dac_pulse_period_dbg[25]} {dac_pulse_period_dbg[26]} {dac_pulse_period_dbg[27]} {dac_pulse_period_dbg[28]} {dac_pulse_period_dbg[29]} {dac_pulse_period_dbg[30]} {dac_pulse_period_dbg[31]}]]
+create_debug_port u_ila_2 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe3]
+set_property port_width 32 [get_debug_ports u_ila_2/probe3]
+connect_debug_port u_ila_2/probe3 [get_nets [list {dac_pulse_width_dbg[0]} {dac_pulse_width_dbg[1]} {dac_pulse_width_dbg[2]} {dac_pulse_width_dbg[3]} {dac_pulse_width_dbg[4]} {dac_pulse_width_dbg[5]} {dac_pulse_width_dbg[6]} {dac_pulse_width_dbg[7]} {dac_pulse_width_dbg[8]} {dac_pulse_width_dbg[9]} {dac_pulse_width_dbg[10]} {dac_pulse_width_dbg[11]} {dac_pulse_width_dbg[12]} {dac_pulse_width_dbg[13]} {dac_pulse_width_dbg[14]} {dac_pulse_width_dbg[15]} {dac_pulse_width_dbg[16]} {dac_pulse_width_dbg[17]} {dac_pulse_width_dbg[18]} {dac_pulse_width_dbg[19]} {dac_pulse_width_dbg[20]} {dac_pulse_width_dbg[21]} {dac_pulse_width_dbg[22]} {dac_pulse_width_dbg[23]} {dac_pulse_width_dbg[24]} {dac_pulse_width_dbg[25]} {dac_pulse_width_dbg[26]} {dac_pulse_width_dbg[27]} {dac_pulse_width_dbg[28]} {dac_pulse_width_dbg[29]} {dac_pulse_width_dbg[30]} {dac_pulse_width_dbg[31]}]]
+create_debug_port u_ila_2 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe4]
+set_property port_width 1 [get_debug_ports u_ila_2/probe4]
+connect_debug_port u_ila_2/probe4 [get_nets [list dac_rst_dbg]]
+create_debug_port u_ila_2 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe5]
+set_property port_width 1 [get_debug_ports u_ila_2/probe5]
+connect_debug_port u_ila_2/probe5 [get_nets [list dac_start_dbg]]
+set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
+set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+connect_debug_port dbg_hub/clk [get_nets dac_clk]

designs/eth_ctrl_debug/eth_ctrl_debug.sv

@@ -0,0 +1,298 @@
+`timescale 1 ns / 1 ns
+
+module eth_ctrl_debug_top #(
+    parameter int unsigned DAC_DATA_WIDTH = 12
+)(
+    input               sys_clk_p,
+    input               sys_clk_n,
+    input               rst_n,
+
+    output [3:0]        led,
+
+    output              e_reset,
+    output              e_mdc,
+    inout               e_mdio,
+
+    output [3:0]        rgmii_txd,
+    output              rgmii_txctl,
+    output              rgmii_txc,
+    input  [3:0]        rgmii_rxd,
+    input               rgmii_rxctl,
+    input               rgmii_rxc
+);
+
+    // -------------------------------------------------------------------------
+    // Internal GMII-side signals
+    // -------------------------------------------------------------------------
+    wire  [7:0] gmii_txd;
+    wire        gmii_tx_en;
+    wire        gmii_tx_er;
+    wire        gmii_tx_clk;
+    wire        gmii_crs;
+    wire        gmii_col;
+    wire  [7:0] gmii_rxd_i;
+    wire        gmii_rx_dv;
+    wire        gmii_rx_er;
+    wire        gmii_rx_clk;
+
+    wire [31:0] pack_total_len;
+
+    wire        e_rx_dv;
+    wire [7:0]  e_rxd;
+    wire        e_tx_en;
+    wire [7:0]  e_txd;
+    wire        e_rst_n;
+    wire        sys_clk;
+
+    wire        duplex_mode;
+
+    assign duplex_mode = 1'b1;
+
+    // -------------------------------------------------------------------------
+    // System clock buffer (200 MHz differential input)
+    // -------------------------------------------------------------------------
+    IBUFDS sys_clk_ibufgds (
+        .O  (sys_clk),
+        .I  (sys_clk_p),
+        .IB (sys_clk_n)
+    );
+
+    // -------------------------------------------------------------------------
+    // IDELAYCTRL
+    // -------------------------------------------------------------------------
+    (* IODELAY_GROUP = "rgmii_idelay_group" *)
+    IDELAYCTRL IDELAYCTRL_inst (
+        .RDY    (),
+        .REFCLK (sys_clk),
+        .RST    (1'b0)
+    );
+
+    // -------------------------------------------------------------------------
+    // Generated clocks for controller
+    // Need to create this IP in Vivado:
+    //  input : 200 MHz
+    //  output0: 130 MHz
+    //  output1: 65 MHz
+    // -------------------------------------------------------------------------
+    wire dac_clk;
+    wire adc_clk;
+    wire clk_wiz_locked;
+
+    clk_wiz_ctrl_inst clk_wiz_ctrl_inst (
+        .clk_in1   (sys_clk),
+        .reset    (~rst_n),
+        .clk_out1  (dac_clk),   // 130 MHz
+        .clk_out2  (adc_clk),   // 65 MHz
+        .locked    (clk_wiz_locked)
+    );
+
+    // -------------------------------------------------------------------------
+    // GMII <-> RGMII conversion
+    // -------------------------------------------------------------------------
+    util_gmii_to_rgmii util_gmii_to_rgmii_m0 (
+        .reset           (1'b0),
+        .rgmii_td        (rgmii_txd),
+        .rgmii_tx_ctl    (rgmii_txctl),
+        .rgmii_txc       (rgmii_txc),
+        .rgmii_rd        (rgmii_rxd),
+        .rgmii_rx_ctl    (rgmii_rxctl),
+        .gmii_rx_clk     (gmii_rx_clk),
+        .gmii_txd        (e_txd),
+        .gmii_tx_en      (e_tx_en),
+        .gmii_tx_er      (1'b0),
+        .gmii_tx_clk     (gmii_tx_clk),
+        .gmii_crs        (gmii_crs),
+        .gmii_col        (gmii_col),
+        .gmii_rxd        (gmii_rxd_i),
+        .rgmii_rxc       (rgmii_rxc),
+        .gmii_rx_dv      (gmii_rx_dv),
+        .gmii_rx_er      (gmii_rx_er),
+        .speed_selection (2'b10),
+        .duplex_mode     (duplex_mode)
+    );
+
+    // -------------------------------------------------------------------------
+    // GMII arbitration / adaptation
+    // -------------------------------------------------------------------------
+    gmii_arbi arbi_inst (
+        .clk            (gmii_tx_clk),
+        .rst_n          (rst_n),
+        .speed          (2'b10),
+        .link           (1'b1),
+        .pack_total_len (pack_total_len),
+        .e_rst_n        (e_rst_n),
+        .gmii_rx_dv     (gmii_rx_dv),
+        .gmii_rxd       (gmii_rxd_i),
+        .gmii_tx_en     (gmii_tx_en),
+        .gmii_txd       (gmii_txd),
+        .e_rx_dv        (e_rx_dv),
+        .e_rxd          (e_rxd),
+        .e_tx_en        (e_tx_en),
+        .e_txd          (e_txd)
+    );
+
+    // -------------------------------------------------------------------------
+    // axis_mac interface
+    // RX stream from Ethernet goes into controller
+    // TX stream is unused for now
+    // -------------------------------------------------------------------------
+    wire        req_ready;
+
+    reg         send_req;
+    reg  [15:0] data_length;
+
+    reg  [7:0]  s_axis_tx_tdata;
+    reg         s_axis_tx_tvalid;
+    wire        s_axis_tx_tready;
+    reg         s_axis_tx_tlast;
+
+    (* MARK_DEBUG="true" *) wire [7:0]  m_axis_rx_tdata;
+    (* MARK_DEBUG="true" *) wire        m_axis_rx_tvalid;
+    (* MARK_DEBUG="true" *) wire        m_axis_rx_tlast;
+    (* MARK_DEBUG="true" *) wire        m_axis_rx_tready;
+
+    // Always ready to accept RX payload bytes
+    assign m_axis_rx_tready = 1'b1;
+
+    // TX disabled
+    always @(*) begin
+        send_req        = 1'b0;
+        data_length     = 16'd0;
+        s_axis_tx_tdata = 8'd0;
+        s_axis_tx_tvalid= 1'b0;
+        s_axis_tx_tlast = 1'b0;
+    end
+
+    axis_mac axis_mac0 (
+        .gmii_tx_clk       (gmii_tx_clk),
+        .gmii_rx_clk       (gmii_rx_clk),
+        .rst_n             (e_rst_n),
+
+        .gmii_rx_dv        (e_rx_dv),
+        .gmii_rxd          (e_rxd),
+        .gmii_tx_en        (gmii_tx_en),
+        .gmii_txd          (gmii_txd),
+
+        .send_req          (send_req),
+        .data_length       (data_length),
+        .req_ready         (req_ready),
+
+        .s_axis_tx_tdata   (s_axis_tx_tdata),
+        .s_axis_tx_tvalid  (s_axis_tx_tvalid),
+        .s_axis_tx_tready  (s_axis_tx_tready),
+        .s_axis_tx_tlast   (s_axis_tx_tlast),
+
+        .m_axis_rx_tdata   (m_axis_rx_tdata),
+        .m_axis_rx_tvalid  (m_axis_rx_tvalid),
+        .m_axis_rx_tready  (m_axis_rx_tready),
+        .m_axis_rx_tlast   (m_axis_rx_tlast)
+    );
+
+    // PHY reset helper from your original example
+    reset reset_m0 (
+        .clk   (sys_clk),
+        .key1  (rst_n),
+        .rst_n (e_reset)
+    );
+
+    // MDIO lines are not driven here yet
+    assign e_mdc  = 1'b0;
+    assign e_mdio = 1'bz;
+
+    // -------------------------------------------------------------------------
+    // Controller reset
+    // Use both external reset and clk_wiz lock
+    // -------------------------------------------------------------------------
+    wire ctrl_rst_n = rst_n & clk_wiz_locked;
+
+    // -------------------------------------------------------------------------
+    // Debug finish generator
+    //
+    // After each adc_start pulse generates one finish pulse after some delay.
+    // This is just for first bring-up so the controller can leave busy state
+    // If you don't want this, replace with:
+    // wire finish_dbg = 1'b0;
+    // -------------------------------------------------------------------------
+    (* MARK_DEBUG="true" *) logic        finish_dbg;
+    (* MARK_DEBUG="true" *) logic [7:0]  finish_cnt;
+    (* MARK_DEBUG="true" *) logic        finish_pending;
+
+    // Controller outputs to debug
+    (* MARK_DEBUG="true" *) wire [31:0]               dac_pulse_width_dbg;
+    (* MARK_DEBUG="true" *) wire [31:0]               dac_pulse_period_dbg;
+    (* MARK_DEBUG="true" *) wire [DAC_DATA_WIDTH-1:0] dac_pulse_height_dbg;
+    (* MARK_DEBUG="true" *) wire [15:0]               dac_pulse_num_dbg;
+
+    (* MARK_DEBUG="true" *) wire [31:0]               adc_pulse_period_dbg;
+    (* MARK_DEBUG="true" *) wire [15:0]               adc_pulse_num_dbg;
+
+    (* MARK_DEBUG="true" *) wire                      dac_start_dbg;
+    (* MARK_DEBUG="true" *) wire                      adc_start_dbg;
+    (* MARK_DEBUG="true" *) wire                      dac_rst_dbg;
+    (* MARK_DEBUG="true" *) wire                      adc_rst_dbg;
+
+    always_ff @(posedge adc_clk or negedge ctrl_rst_n) begin
+        if (!ctrl_rst_n) begin
+            finish_dbg     <= 1'b0;
+            finish_cnt     <= 8'd0;
+            finish_pending <= 1'b0;
+        end else begin
+            finish_dbg <= 1'b0;
+
+            if (adc_start_dbg) begin
+                finish_pending <= 1'b1;
+                finish_cnt     <= 8'd80;
+            end else if (finish_pending) begin
+                if (finish_cnt == 8'd0) begin
+                    finish_dbg     <= 1'b1;
+                    finish_pending <= 1'b0;
+                end else begin
+                    finish_cnt <= finish_cnt - 8'd1;
+                end
+            end
+        end
+    end
+
+    // -------------------------------------------------------------------------
+    // Controller
+    // ETH domain = gmii_rx_clk, because RX AXI master comes from axis_mac RX side
+    // -------------------------------------------------------------------------
+    control #(
+        .DAC_DATA_WIDTH(DAC_DATA_WIDTH)
+    ) udp_ctrl_inst (
+        .eth_clk_in        (gmii_rx_clk),
+        .dac_clk_in        (dac_clk),
+        .adc_clk_in        (adc_clk),
+        .rst_n             (ctrl_rst_n),
+
+        .s_axis_tdata      (m_axis_rx_tdata),
+        .s_axis_tvalid     (m_axis_rx_tvalid),
+        .s_axis_tready     (), // controller internally always ready in current version
+        .s_axis_tlast      (m_axis_rx_tlast),
+
+        .finish            (finish_dbg),
+
+        .dac_pulse_width   (dac_pulse_width_dbg),
+        .dac_pulse_period  (dac_pulse_period_dbg),
+        .dac_pulse_height  (dac_pulse_height_dbg),
+        .dac_pulse_num     (dac_pulse_num_dbg),
+
+        .adc_pulse_period  (adc_pulse_period_dbg),
+        .adc_pulse_num     (adc_pulse_num_dbg),
+
+        .dac_start         (dac_start_dbg),
+        .adc_start         (adc_start_dbg),
+
+        .dac_rst           (dac_rst_dbg),
+        .adc_rst           (adc_rst_dbg)
+    );
+
+    // -------------------------------------------------------------------------
+    // Simple LED status
+    // -------------------------------------------------------------------------
+    assign led[0] = clk_wiz_locked;
+    assign led[1] = m_axis_rx_tvalid;
+    assign led[2] = dac_start_dbg;
+    assign led[3] = adc_rst_dbg;
+
+endmodule

designs/eth_ctrl_debug/ip/clk_wiz_ctrl_inst.xci

@@ -0,0 +1,689 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "clk_wiz_ctrl_inst",
+    "component_reference": "xilinx.com:ip:clk_wiz:6.0",
+    "ip_revision": "16",
+    "gen_directory": "../../../../eth_ctrl_debug_top.gen/sources_1/ip/clk_wiz_ctrl_inst",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "clk_wiz_ctrl_inst", "resolve_type": "user", "usage": "all" } ],
+        "USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "ENABLE_CLOCK_MONITOR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ENABLE_USER_CLOCK0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ENABLE_USER_CLOCK1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ENABLE_USER_CLOCK2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ENABLE_USER_CLOCK3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Enable_PLL0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Enable_PLL1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PRECISION": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
+        "PRIMTYPE_SEL": [ { "value": "mmcm_adv", "resolve_type": "user", "usage": "all" } ],
+        "CLOCK_MGR_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
+        "USE_FREQ_SYNTH": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_SPREAD_SPECTRUM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_PHASE_ALIGNMENT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_MIN_POWER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "user", "usage": "all" } ],
+        "PRIM_IN_FREQ": [ { "value": "200.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "user", "usage": "all" } ],
+        "PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "user", "usage": "all" } ],
+        "IN_JITTER_UNITS": [ { "value": "Units_UI", "resolve_type": "user", "usage": "all" } ],
+        "RELATIVE_INCLK": [ { "value": "REL_PRIMARY", "resolve_type": "user", "usage": "all" } ],
+        "USE_INCLK_SWITCHOVER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "user", "usage": "all" } ],
+        "SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
+        "JITTER_OPTIONS": [ { "value": "UI", "resolve_type": "user", "usage": "all" } ],
+        "CLKIN1_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKIN2_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKIN1_JITTER_PS": [ { "value": "50.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT2_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT3_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT4_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "NUM_OUT_CLKS": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT4_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "user", "usage": "all" } ],
+        "DADDR_PORT": [ { "value": "daddr", "resolve_type": "user", "usage": "all" } ],
+        "DCLK_PORT": [ { "value": "dclk", "resolve_type": "user", "usage": "all" } ],
+        "DRDY_PORT": [ { "value": "drdy", "resolve_type": "user", "usage": "all" } ],
+        "DWE_PORT": [ { "value": "dwe", "resolve_type": "user", "usage": "all" } ],
+        "DIN_PORT": [ { "value": "din", "resolve_type": "user", "usage": "all" } ],
+        "DOUT_PORT": [ { "value": "dout", "resolve_type": "user", "usage": "all" } ],
+        "DEN_PORT": [ { "value": "den", "resolve_type": "user", "usage": "all" } ],
+        "PSCLK_PORT": [ { "value": "psclk", "resolve_type": "user", "usage": "all" } ],
+        "PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ],
+        "PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ],
+        "PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "130.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "65.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "USE_MAX_I_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_MIN_O_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+        "FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ],
+        "PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ],
+        "SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
+        "USE_LOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
+        "USE_RESET": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "RESET_PORT": [ { "value": "reset", "resolve_type": "user", "usage": "all" } ],
+        "LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ],
+        "POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ],
+        "CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ],
+        "STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ],
+        "CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ],
+        "INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ],
+        "SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ],
+        "SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
+        "MMCM_DIVCLK_DIVIDE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
+        "MMCM_CLKFBOUT_MULT_F": [ { "value": "4.875", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKIN1_PERIOD": [ { "value": "5.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "user", "usage": "all" } ],
+        "MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT0_DIVIDE_F": [ { "value": "7.500", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT1_DIVIDE": [ { "value": "15", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "OVERRIDE_PLL": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "PLL_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
+        "PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
+        "PLL_CLKFBOUT_MULT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "user", "usage": "all" } ],
+        "PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKIN_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "user", "usage": "all" } ],
+        "PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "RESET_TYPE": [ { "value": "ACTIVE_HIGH", "resolve_type": "user", "usage": "all" } ],
+        "USE_SAFE_CLOCK_STARTUP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_CLOCK_SEQUENCING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "DIFF_CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "DIFF_CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
+        "RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "ENABLE_CDDC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "user", "usage": "all" } ],
+        "CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "user", "usage": "all" } ],
+        "ENABLE_CLKOUTPHY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_JITTER": [ { "value": "102.676", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_PHASE_ERROR": [ { "value": "87.159", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_JITTER": [ { "value": "117.878", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_PHASE_ERROR": [ { "value": "87.159", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "INPUT_MODE": [ { "value": "frequency", "resolve_type": "user", "usage": "all" } ],
+        "INTERFACE_SELECTION": [ { "value": "Enable_AXI", "resolve_type": "user", "usage": "all" } ],
+        "AXI_DRP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "PHASE_DUTY_CONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_CLKOUT2_USED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
+        "C_USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_ENABLE_CLOCK_MONITOR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_USER_CLOCK0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_USER_CLOCK1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_USER_CLOCK2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_USER_CLOCK3": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_Enable_PLL0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_Enable_PLL1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PRECISION": [ { "value": "1", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT4_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT5_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT6_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT7_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKOUT1_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKOUT2_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKOUT3_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKOUT4_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "c_component_name": [ { "value": "clk_wiz_ctrl_inst", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_FREQ_SYNTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_PHASE_ALIGNMENT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_MIN_POWER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_MIN_O_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_MAX_I_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_DYN_PHASE_SHIFT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_INCLK_SWITCHOVER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_DYN_RECONFIG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_SPREAD_SPECTRUM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_FAST_SIMULATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIMTYPE_SEL": [ { "value": "AUTO", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_CLK_VALID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIM_IN_FREQ": [ { "value": "200.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "generated", "usage": "all" } ],
+        "C_SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "generated", "usage": "all" } ],
+        "C_PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
+        "C_PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "generated", "usage": "all" } ],
+        "C_SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_RESET": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RESET_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_LOCKED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_INCLK_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKFB_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_POWER_DOWN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_STATUS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_FREEZE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NUM_OUT_CLKS": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_INCLK_SUM_ROW0": [ { "value": "Input Clock   Freq (MHz)    Input Jitter (UI)", "resolve_type": "generated", "usage": "all" } ],
+        "C_INCLK_SUM_ROW1": [ { "value": "__primary_________200.000____________0.010", "resolve_type": "generated", "usage": "all" } ],
+        "C_INCLK_SUM_ROW2": [ { "value": "no_secondary_input_clock ", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW0A": [ { "value": " Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW0B": [ { "value": "  Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__130.00000______0.000______50.0______102.676_____87.159", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW2": [ { "value": "clk_out2__65.00000______0.000______50.0______117.878_____87.159", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW3": [ { "value": "no_CLK_OUT3_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW4": [ { "value": "no_CLK_OUT4_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW5": [ { "value": "no_CLK_OUT5_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW6": [ { "value": "no_CLK_OUT6_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW7": [ { "value": "no_CLK_OUT7_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "130.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "65.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_OUT_FREQ": [ { "value": "130.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_OUT_FREQ": [ { "value": "65.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_USE_SAFE_CLOCK_STARTUP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLOCK_SEQUENCING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_NOTES": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKFBOUT_MULT_F": [ { "value": "4.875", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKIN1_PERIOD": [ { "value": "5.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_CASCADE": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
+        "C_MMCM_CLOCK_HOLD": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
+        "C_MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_STARTUP_WAIT": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "7.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT1_DIVIDE": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_NOTES": [ { "value": "No notes", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_CLKFBOUT_MULT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKIN_PERIOD": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLOCK_MGR_TYPE": [ { "value": "NA", "resolve_type": "generated", "usage": "all" } ],
+        "C_OVERRIDE_MMCM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OVERRIDE_PLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "generated", "usage": "all" } ],
+        "C_SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "generated", "usage": "all" } ],
+        "C_RESET_PORT": [ { "value": "reset", "resolve_type": "generated", "usage": "all" } ],
+        "C_LOCKED_PORT": [ { "value": "locked", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "generated", "usage": "all" } ],
+        "C_POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "generated", "usage": "all" } ],
+        "C_DADDR_PORT": [ { "value": "daddr", "resolve_type": "generated", "usage": "all" } ],
+        "C_DCLK_PORT": [ { "value": "dclk", "resolve_type": "generated", "usage": "all" } ],
+        "C_DRDY_PORT": [ { "value": "drdy", "resolve_type": "generated", "usage": "all" } ],
+        "C_DWE_PORT": [ { "value": "dwe", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIN_PORT": [ { "value": "din", "resolve_type": "generated", "usage": "all" } ],
+        "C_DOUT_PORT": [ { "value": "dout", "resolve_type": "generated", "usage": "all" } ],
+        "C_DEN_PORT": [ { "value": "den", "resolve_type": "generated", "usage": "all" } ],
+        "C_PSCLK_PORT": [ { "value": "psclk", "resolve_type": "generated", "usage": "all" } ],
+        "C_PSEN_PORT": [ { "value": "psen", "resolve_type": "generated", "usage": "all" } ],
+        "C_PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "generated", "usage": "all" } ],
+        "C_PSDONE_PORT": [ { "value": "psdone", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "generated", "usage": "all" } ],
+        "C_STATUS_PORT": [ { "value": "STATUS", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "generated", "usage": "all" } ],
+        "C_INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKIN1_JITTER_PS": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
+        "C_SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "generated", "usage": "all" } ],
+        "C_SS_MOD_PERIOD": [ { "value": "4000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_HAS_CDDC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "generated", "usage": "all" } ],
+        "C_CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUTPHY_MODE": [ { "value": "VCO", "resolve_type": "generated", "usage": "all" } ],
+        "C_ENABLE_CLKOUTPHY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INTERFACE_SELECTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_ADDR_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_POWER_REG": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT0_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT0_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT1_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT1_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT2_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT2_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT3_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT3_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT4_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT4_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT5_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT5_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT6_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT6_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFBOUT_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFBOUT_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVCLK": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_LOCK_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_LOCK_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_LOCK_3": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_FILTER_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_FILTER_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE1_AUTO": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE2_AUTO": [ { "value": "2.0", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE3_AUTO": [ { "value": "0.13333333333333333", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE4_AUTO": [ { "value": "0.13333333333333333", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE5_AUTO": [ { "value": "0.13333333333333333", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE6_AUTO": [ { "value": "0.13333333333333333", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE7_AUTO": [ { "value": "0.13333333333333333", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLLBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLLBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLLBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLLBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLLBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV5": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV6": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV7": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT0_ACTUAL_FREQ": [ { "value": "130.00000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT1_ACTUAL_FREQ": [ { "value": "65.00000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT2_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT3_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT4_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT5_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT6_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+        "C_M_MAX": [ { "value": "64.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_M_MIN": [ { "value": "2.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_D_MAX": [ { "value": "80.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_D_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_O_MAX": [ { "value": "128.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_O_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_VCO_MIN": [ { "value": "600.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_VCO_MAX": [ { "value": "1200.000", "resolve_type": "generated", "format": "float", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "artix7" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7a35t" } ],
+        "PACKAGE": [ { "value": "fgg484" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-1" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Flow" } ],
+        "IPREVISION": [ { "value": "16" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../eth_ctrl_debug_top.gen/sources_1/ip/clk_wiz_ctrl_inst" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "." } ],
+        "SWVERSION": [ { "value": "2025.1" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "reset": [ { "direction": "in", "driver_value": "0" } ],
+        "clk_in1": [ { "direction": "in" } ],
+        "clk_out1": [ { "direction": "out" } ],
+        "clk_out2": [ { "direction": "out" } ],
+        "locked": [ { "direction": "out" } ]
+      },
+      "interfaces": {
+        "reset": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ],
+            "BOARD.ASSOCIATED_PARAM": [ { "value": "RESET_BOARD_INTERFACE", "value_src": "constant", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "reset" } ]
+          }
+        },
+        "clock_CLK_IN1": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
+            "BOARD.ASSOCIATED_PARAM": [ { "value": "CLK_IN1_BOARD_INTERFACE", "usage": "all", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK_IN1": [ { "physical_name": "clk_in1" } ]
+          }
+        },
+        "clock_CLK_OUT1": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK_OUT1": [ { "physical_name": "clk_out1" } ]
+          }
+        },
+        "clock_CLK_OUT2": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK_OUT2": [ { "physical_name": "clk_out2" } ]
+          }
+        }
+      }
+    }
+  }
+}

rtl/controller/README.md

@@ -0,0 +1,62 @@
+# Системный контроллер
+
+Контроллер принимает входные пакеты udp с ethernet, передаваемые по axi stream, и выполняет настройку выходных регистров в соотвествии с содержимым этого пакета, а также синхронизирует сигналы между тремя clock domains - есть clk от ethernet, clk для ЦАП и clk для АЦП
+
+## Список параметров:
+- dac_data_width - битность данных ЦАП, <= 16bit
+
+## Список входных портов:
+- eth_clk_in - базовая входная частота
+- dac_clk_in - входная частота ЦАП
+- adc_clk_in - входная частота АЦП
+- rst_n - общий reset 
+- s_axis [8 bit] - AXI stream slave для приема данных от ethernet udp (уже разобранный payload по байтам) - домен eth_clk
+- finish - сигнал окончания приема данных с АЦП, домен adc_clk !
+
+## Список выходных портов:
+- dac_pulse_width[31:0] - выход pulse_width в домене dac_clk
+- dac_pulse_period[31:0] - выход pulse_period в домене dac_clk
+- dac_pulse_height[dac_data_width-1:0] - выход pulse_height в домене dac_clk
+- dac_pulse_num[15:0] - выход pulse_num в домене dac_clk
+---
+- adc_pulse_period[31:0] - выход pulse_period в домене adc_clk
+- adc_pulse_num[15:0] - выход pulse_num в домене adc_clk
+---
+- dac_start - start в домене dac_clk
+- adc_start - start в домене adc_clk
+---
+- dac_rst - rst в домене dac_clk
+- adc_rst - rst в домене adc_clk
+
+## Логика работы:
+по умолчанию после инициализации блок встает в состояние ожидания (*idle*), и становится *ready* для приема данных по axis.
+далее ждет контрольный пакет. всего есть 3 вариации контрольных пакетов (в любом порядке), получаемых по axi stream:
+```
+8'b00001111 - soft reset
+8'b11110000 - start
+8'b10001000 - set_data
+```
+
+*soft reset* значит, что нужно отправить пульс rst на dac_rst и adc_rst, синхронизировав пульсы в их доменах. при этом сброс самого контроллера делать не нужно!
+
+*start* значит, что нужно отправить пульс start на dac_start и adc_start в их доменах, желательно как можно "одновременее". при этом после этого блок перестает быть ready и ждет, пока не придет пульс finish, после этого он возвращается снова в  idle состояние
+
+set_data** значит, что следующие 96 бит = 12*8 байт, пришедшии по axis - это конфигурационная информация и ее нужно записать в внутренний регистр на 96 бит.
+
+конфигурационный регистр на 96 бит делится так:
+```
+reg[31:0] - pulse_width
+reg[63:32] - pulse_period
+reg[79:64] - pulse_num
+reg[79+dac_data_width:80] - pulse_height
+```
+
+соотвественно эти записанные значения должны выставляются на соотвествующие выходные сигналы в доменах dac_clk и adc_clk. выходы обновляются каждый раз, когда происходит set_data, и сигналы сохраняют своё значение до следующего set_data.
+
+## Симуляция
+Тесты запускаются автоматически через make.
+```
+cd tests
+make sim
+```
+Должно выдать "All tests done" в конце симуляции.

rtl/controller/src/controller.sv

@@ -0,0 +1,462 @@
+module control #(
+    parameter int unsigned DAC_DATA_WIDTH = 12
+) (
+    input  logic                       eth_clk_in,
+    input  logic                       dac_clk_in,
+    input  logic                       adc_clk_in,
+    input  logic                       rst_n,
+
+    // AXI stream slave, eth_clk_in domain
+    input  logic [7:0]                 s_axis_tdata,
+    input  logic                       s_axis_tvalid,
+    output logic                       s_axis_tready,
+    input  logic                       s_axis_tlast,
+
+    // adc_clk_in domain
+    input  logic                       finish,
+
+    // dac_clk_in domain outputs
+    output logic [31:0]                dac_pulse_width,
+    output logic [31:0]                dac_pulse_period,
+    output logic [DAC_DATA_WIDTH-1:0]  dac_pulse_height,
+    output logic [15:0]                dac_pulse_num,
+
+    // adc_clk_in domain outputs
+    output logic [31:0]                adc_pulse_period,
+    output logic [15:0]                adc_pulse_num,
+
+    // pulse outputs
+    output logic                       dac_start,
+    output logic                       adc_start,
+    output logic                       dac_rst,
+    output logic                       adc_rst
+);
+
+    // static checks
+    initial begin
+        if (DAC_DATA_WIDTH > 16) begin
+            $error("DAC_DATA_WIDTH must be <= 16");
+        end
+        if (DAC_DATA_WIDTH == 0) begin
+            $error("DAC_DATA_WIDTH must be > 0");
+        end
+    end
+
+    // command constants
+    localparam logic [7:0] CMD_SOFT_RESET = 8'h0F;
+    localparam logic [7:0] CMD_START      = 8'hF0;
+    localparam logic [7:0] CMD_SET_DATA   = 8'h88;
+
+    // reset synchronizers: async assert, sync deassert in each domain
+    logic eth_rst_ff1, eth_rst_ff2;
+    logic dac_rst_ff1, dac_rst_ff2;
+    logic adc_rst_ff1, adc_rst_ff2;
+
+    logic eth_rst;
+    logic dac_rst_int;
+    logic adc_rst_int;
+
+    always_ff @(posedge eth_clk_in or negedge rst_n) begin
+        if (!rst_n) begin
+            eth_rst_ff1 <= 1'b1;
+            eth_rst_ff2 <= 1'b1;
+        end else begin
+            eth_rst_ff1 <= 1'b0;
+            eth_rst_ff2 <= eth_rst_ff1;
+        end
+    end
+
+    always_ff @(posedge dac_clk_in or negedge rst_n) begin
+        if (!rst_n) begin
+            dac_rst_ff1 <= 1'b1;
+            dac_rst_ff2 <= 1'b1;
+        end else begin
+            dac_rst_ff1 <= 1'b0;
+            dac_rst_ff2 <= dac_rst_ff1;
+        end
+    end
+
+    always_ff @(posedge adc_clk_in or negedge rst_n) begin
+        if (!rst_n) begin
+            adc_rst_ff1 <= 1'b1;
+            adc_rst_ff2 <= 1'b1;
+        end else begin
+            adc_rst_ff1 <= 1'b0;
+            adc_rst_ff2 <= adc_rst_ff1;
+        end
+    end
+
+    assign eth_rst     = eth_rst_ff2;
+    assign dac_rst_int = dac_rst_ff2;
+    assign adc_rst_int = adc_rst_ff2;
+
+    // axi stream is always accepted. If packet is not needed, it is discarded.
+    assign s_axis_tready = 1'b1;
+
+    (* MARK_DEBUG="true" *) wire axis_hs = s_axis_tvalid & s_axis_tready;
+
+    // -------------------------------------------------------------------------
+    // Shared 96-bit config bus in ETH domain
+    //
+    // Byte order for SET_DATA payload, little-endian:
+    // payload byte 0  -> cfg_bus_eth[7:0]
+    // payload byte 1  -> cfg_bus_eth[15:8]
+    // ...etc...
+    // payload byte 11 -> cfg_bus_eth[95:88]
+    //
+    // Field layout inside cfg_bus_eth:
+    // [31:0]   pulse_width
+    // [63:32]  pulse_period
+    // [79:64]  pulse_num
+    // [95:80]  pulse_height_raw[15:0]
+    // -------------------------------------------------------------------------
+    (* MARK_DEBUG="true" *) logic [95:0] cfg_bus_eth;
+    logic [95:0] cfg_shift_eth;
+
+    // ETH-domain parser and control
+    typedef enum logic [2:0] {
+        ST_IDLE         = 3'd0,
+        ST_RECV_CFG     = 3'd1,
+        ST_WAIT_CFG_ACK = 3'd2,
+        ST_DISCARD      = 3'd3
+    } eth_state_t;
+
+    (* MARK_DEBUG="true" *) eth_state_t eth_state;
+
+    logic [3:0] cfg_byte_cnt;
+
+    // Busy flag: set by START command, cleared by finish event from ADC domain
+    (* MARK_DEBUG="true" *) logic busy_flag_eth;
+
+    // Pending ACKs for config delivery
+    logic cfg_wait_dac_ack;
+    logic cfg_wait_adc_ack;
+
+    // Event toggles ETH -> DAC/ADC
+    logic start_toggle_eth;
+    logic rst_toggle_eth;
+
+    // Config request toggles ETH -> DAC/ADC
+    logic cfg_req_toggle_dac_eth;
+    logic cfg_req_toggle_adc_eth;
+
+    // ACK toggles DAC/ADC -> ETH
+    logic cfg_ack_toggle_dac;
+    logic cfg_ack_toggle_adc;
+
+    (* ASYNC_REG = "TRUE" *) logic cfg_ack_toggle_dac_meta, cfg_ack_toggle_dac_sync, cfg_ack_toggle_dac_sync_d;
+    (* ASYNC_REG = "TRUE" *) logic cfg_ack_toggle_adc_meta, cfg_ack_toggle_adc_sync, cfg_ack_toggle_adc_sync_d;
+
+    wire cfg_ack_pulse_dac_eth = cfg_ack_toggle_dac_sync ^ cfg_ack_toggle_dac_sync_d;
+    wire cfg_ack_pulse_adc_eth = cfg_ack_toggle_adc_sync ^ cfg_ack_toggle_adc_sync_d;
+
+    always_ff @(posedge eth_clk_in or posedge eth_rst) begin
+        if (eth_rst) begin
+            cfg_ack_toggle_dac_meta   <= 1'b0;
+            cfg_ack_toggle_dac_sync   <= 1'b0;
+            cfg_ack_toggle_dac_sync_d <= 1'b0;
+
+            cfg_ack_toggle_adc_meta   <= 1'b0;
+            cfg_ack_toggle_adc_sync   <= 1'b0;
+            cfg_ack_toggle_adc_sync_d <= 1'b0;
+        end else begin
+            cfg_ack_toggle_dac_meta   <= cfg_ack_toggle_dac;
+            cfg_ack_toggle_dac_sync   <= cfg_ack_toggle_dac_meta;
+            cfg_ack_toggle_dac_sync_d <= cfg_ack_toggle_dac_sync;
+
+            cfg_ack_toggle_adc_meta   <= cfg_ack_toggle_adc;
+            cfg_ack_toggle_adc_sync   <= cfg_ack_toggle_adc_meta;
+            cfg_ack_toggle_adc_sync_d <= cfg_ack_toggle_adc_sync;
+        end
+    end
+
+    // finish event: ADC -> ETH via toggle CDC
+    logic finish_toggle_adc;
+    logic finish_meta_eth, finish_sync_eth, finish_sync_eth_d;
+
+    wire finish_pulse_eth = finish_sync_eth ^ finish_sync_eth_d;
+
+    always_ff @(posedge adc_clk_in or posedge adc_rst_int) begin
+        if (adc_rst_int) begin
+            finish_toggle_adc <= 1'b0;
+        end else if (finish) begin
+            finish_toggle_adc <= ~finish_toggle_adc;
+        end
+    end
+
+    always_ff @(posedge eth_clk_in or posedge eth_rst) begin
+        if (eth_rst) begin
+            finish_meta_eth   <= 1'b0;
+            finish_sync_eth   <= 1'b0;
+            finish_sync_eth_d <= 1'b0;
+        end else begin
+            finish_meta_eth   <= finish_toggle_adc;
+            finish_sync_eth   <= finish_meta_eth;
+            finish_sync_eth_d <= finish_sync_eth;
+        end
+    end
+
+    // ETH FSM
+    always_ff @(posedge eth_clk_in or posedge eth_rst) begin
+        if (eth_rst) begin
+            eth_state              <= ST_IDLE;
+            cfg_byte_cnt           <= '0;
+            cfg_shift_eth          <= '0;
+            cfg_bus_eth            <= '0;
+
+            busy_flag_eth          <= 1'b0;
+
+            start_toggle_eth       <= 1'b0;
+            rst_toggle_eth         <= 1'b0;
+
+            cfg_req_toggle_dac_eth <= 1'b0;
+            cfg_req_toggle_adc_eth <= 1'b0;
+
+            cfg_wait_dac_ack       <= 1'b0;
+            cfg_wait_adc_ack       <= 1'b0;
+        end else begin
+            // finish always clears busy
+            if (finish_pulse_eth) begin
+                busy_flag_eth <= 1'b0;
+            end
+
+            // config acks
+            if (cfg_ack_pulse_dac_eth) begin
+                cfg_wait_dac_ack <= 1'b0;
+            end
+            if (cfg_ack_pulse_adc_eth) begin
+                cfg_wait_adc_ack <= 1'b0;
+            end
+
+            case (eth_state)
+                ST_IDLE: begin
+                    cfg_byte_cnt  <= '0;
+                    cfg_shift_eth <= cfg_shift_eth;
+
+                    if (axis_hs) begin
+                        // if busy, drop the whole packet
+                        if (busy_flag_eth) begin
+                            if (!s_axis_tlast) begin
+                                eth_state <= ST_DISCARD;
+                            end
+                        end else begin
+                            unique case (s_axis_tdata)
+                                CMD_SOFT_RESET: begin
+                                    rst_toggle_eth <= ~rst_toggle_eth;
+                                end
+
+                                CMD_START: begin
+                                    start_toggle_eth <= ~start_toggle_eth;
+                                    busy_flag_eth    <= 1'b1;
+                                end
+
+                                CMD_SET_DATA: begin
+                                    // expect exactly 12 bytes after command
+                                    if (s_axis_tlast) begin
+                                        // no payload, invalid packet
+                                        eth_state <= ST_IDLE;
+                                    end else begin
+                                        cfg_byte_cnt  <= 4'd0;
+                                        cfg_shift_eth <= '0;
+                                        eth_state     <= ST_RECV_CFG;
+                                    end
+                                end
+
+                                default: begin
+                                    // unknown command: discard packet remainder if any
+                                    if (!s_axis_tlast) begin
+                                        eth_state <= ST_DISCARD;
+                                    end
+                                end
+                            endcase
+                        end
+                    end
+                end
+
+                ST_RECV_CFG: begin
+                    if (axis_hs) begin
+                        // little endian packing
+                        cfg_shift_eth[cfg_byte_cnt*8 +: 8] <= s_axis_tdata;
+
+                        if (cfg_byte_cnt == 4'd11) begin
+                            // this must be the final payload byte
+                            if (s_axis_tlast) begin
+                                cfg_bus_eth            <= {s_axis_tdata, cfg_shift_eth[87:0]};
+                                cfg_req_toggle_dac_eth <= ~cfg_req_toggle_dac_eth;
+                                cfg_req_toggle_adc_eth <= ~cfg_req_toggle_adc_eth;
+                                cfg_wait_dac_ack       <= 1'b1;
+                                cfg_wait_adc_ack       <= 1'b1;
+                                eth_state              <= ST_WAIT_CFG_ACK;
+                            end else begin
+                                // too many bytes in packet
+                                eth_state <= ST_DISCARD;
+                            end
+                        end else begin
+                            // early tlast means packet too short!!
+                            if (s_axis_tlast) begin
+                                eth_state <= ST_IDLE;
+                            end else begin
+                                cfg_byte_cnt <= cfg_byte_cnt + 4'd1;
+                            end
+                        end
+                    end
+                end
+
+                ST_WAIT_CFG_ACK: begin
+                    // any incoming packet while waiting ack is discarded
+                    if (cfg_ack_pulse_dac_eth || cfg_ack_pulse_adc_eth) begin
+                        if ((~cfg_wait_dac_ack || cfg_ack_pulse_dac_eth) &&
+                            (~cfg_wait_adc_ack || cfg_ack_pulse_adc_eth)) begin
+                            eth_state <= ST_IDLE;
+                        end
+                    end
+
+                    if (axis_hs && !s_axis_tlast) begin
+                        eth_state <= ST_DISCARD;
+                    end
+                end
+
+                ST_DISCARD: begin
+                    if (axis_hs && s_axis_tlast) begin
+                        eth_state <= ST_IDLE;
+                    end
+                end
+
+                default: begin
+                    eth_state <= ST_IDLE;
+                end
+            endcase
+        end
+    end
+
+    // ETH -> DAC: start/reset event sync
+    (* ASYNC_REG = "TRUE" *) logic start_meta_dac, start_sync_dac;
+    logic start_sync_dac_d;
+    (* ASYNC_REG = "TRUE" *) logic rst_meta_dac,   rst_sync_dac;
+    logic rst_sync_dac_d;
+
+    wire dac_start_pulse = start_sync_dac ^ start_sync_dac_d;
+    wire dac_rst_pulse   = rst_sync_dac   ^ rst_sync_dac_d;
+
+    always_ff @(posedge dac_clk_in or posedge dac_rst_int) begin
+        if (dac_rst_int) begin
+            start_meta_dac   <= 1'b0;
+            start_sync_dac   <= 1'b0;
+            start_sync_dac_d <= 1'b0;
+
+            rst_meta_dac     <= 1'b0;
+            rst_sync_dac     <= 1'b0;
+            rst_sync_dac_d   <= 1'b0;
+
+            dac_start        <= 1'b0;
+            dac_rst          <= 1'b0;
+        end else begin
+            start_meta_dac   <= start_toggle_eth;
+            start_sync_dac   <= start_meta_dac;
+            start_sync_dac_d <= start_sync_dac;
+
+            rst_meta_dac     <= rst_toggle_eth;
+            rst_sync_dac     <= rst_meta_dac;
+            rst_sync_dac_d   <= rst_sync_dac;
+
+            dac_start        <= dac_start_pulse;
+            dac_rst          <= dac_rst_pulse;
+        end
+    end
+
+    // ETH -> ADC: start/reset event sync
+    (* ASYNC_REG = "TRUE" *) logic start_meta_adc, start_sync_adc;
+    logic start_sync_adc_d;
+    (* ASYNC_REG = "TRUE" *) logic rst_meta_adc,   rst_sync_adc;
+    logic rst_sync_adc_d;
+
+    wire adc_start_pulse = start_sync_adc ^ start_sync_adc_d;
+    wire adc_rst_pulse   = rst_sync_adc   ^ rst_sync_adc_d;
+
+    always_ff @(posedge adc_clk_in or posedge adc_rst_int) begin
+        if (adc_rst_int) begin
+            start_meta_adc   <= 1'b0;
+            start_sync_adc   <= 1'b0;
+            start_sync_adc_d <= 1'b0;
+
+            rst_meta_adc     <= 1'b0;
+            rst_sync_adc     <= 1'b0;
+            rst_sync_adc_d   <= 1'b0;
+
+            adc_start        <= 1'b0;
+            adc_rst          <= 1'b0;
+        end else begin
+            start_meta_adc   <= start_toggle_eth;
+            start_sync_adc   <= start_meta_adc;
+            start_sync_adc_d <= start_sync_adc;
+
+            rst_meta_adc     <= rst_toggle_eth;
+            rst_sync_adc     <= rst_meta_adc;
+            rst_sync_adc_d   <= rst_sync_adc;
+
+            adc_start        <= adc_start_pulse;
+            adc_rst          <= adc_rst_pulse;
+        end
+    end
+
+    // ETH -> DAC config CDC
+    // cfg_bus_eth is kept stable in ETH domain until DAC and ADC both ACK.
+    (* ASYNC_REG = "TRUE" *) logic cfg_req_meta_dac, cfg_req_sync_dac;
+    logic cfg_req_sync_dac_d;
+    wire  cfg_req_pulse_dac = cfg_req_sync_dac ^ cfg_req_sync_dac_d;
+
+    always_ff @(posedge dac_clk_in or posedge dac_rst_int) begin
+        if (dac_rst_int) begin
+            cfg_req_meta_dac  <= 1'b0;
+            cfg_req_sync_dac  <= 1'b0;
+            cfg_req_sync_dac_d<= 1'b0;
+            cfg_ack_toggle_dac<= 1'b0;
+
+            dac_pulse_width   <= '0;
+            dac_pulse_period  <= '0;
+            dac_pulse_num     <= '0;
+            dac_pulse_height  <= '0;
+        end else begin
+            cfg_req_meta_dac   <= cfg_req_toggle_dac_eth;
+            cfg_req_sync_dac   <= cfg_req_meta_dac;
+            cfg_req_sync_dac_d <= cfg_req_sync_dac;
+
+            if (cfg_req_pulse_dac) begin
+                dac_pulse_width  <= cfg_bus_eth[31:0];
+                dac_pulse_period <= cfg_bus_eth[63:32];
+                dac_pulse_num    <= cfg_bus_eth[79:64];
+                dac_pulse_height <= cfg_bus_eth[80 +: DAC_DATA_WIDTH];
+
+                cfg_ack_toggle_dac <= ~cfg_ack_toggle_dac;
+            end
+        end
+    end
+
+    // ETH -> ADC config CDC
+    logic cfg_req_meta_adc, cfg_req_sync_adc, cfg_req_sync_adc_d;
+    wire  cfg_req_pulse_adc = cfg_req_sync_adc ^ cfg_req_sync_adc_d;
+
+    always_ff @(posedge adc_clk_in or posedge adc_rst_int) begin
+        if (adc_rst_int) begin
+            cfg_req_meta_adc   <= 1'b0;
+            cfg_req_sync_adc   <= 1'b0;
+            cfg_req_sync_adc_d <= 1'b0;
+            cfg_ack_toggle_adc <= 1'b0;
+
+            adc_pulse_period   <= '0;
+            adc_pulse_num      <= '0;
+        end else begin
+            cfg_req_meta_adc   <= cfg_req_toggle_adc_eth;
+            cfg_req_sync_adc   <= cfg_req_meta_adc;
+            cfg_req_sync_adc_d <= cfg_req_sync_adc;
+
+            if (cfg_req_pulse_adc) begin
+                adc_pulse_period <= cfg_bus_eth[63:32];
+                adc_pulse_num    <= cfg_bus_eth[79:64];
+
+                cfg_ack_toggle_adc <= ~cfg_ack_toggle_adc;
+            end
+        end
+    end
+
+endmodule

rtl/controller/tests/Makefile

@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# FPGA settings
+FPGA_PART = xc7a35tfgg484-1
+FPGA_TOP = control
+FPGA_ARCH = artix7
+
+RTL_DIR = ../src
+
+
+include ../../../scripts/vivado.mk
+
+SYN_FILES += $(sort $(shell find ../src -type f \( -name '*.v' -o -name '*.sv' \)))
+
+XCI_FILES = $(sort $(shell find ../src -type f -name '*.xci'))
+
+XDC_FILES += ../../../constraints/ax7a035b.xdc
+XDC_FILES += test_timing.xdc
+
+SYN_FILES += controller_tb.sv
+SIM_TOP = control_tb
+
+
+program: $(PROJECT).bit
+	echo "open_hw_manager" > program.tcl
+	echo "connect_hw_server" >> program.tcl
+	echo "open_hw_target" >> program.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+	echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
+	echo "program_hw_devices [current_hw_device]" >> program.tcl
+	echo "exit" >> program.tcl
+	vivado -nojournal -nolog -mode batch -source program.tcl
+
+$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
+	echo "write_cfgmem -force -format mcs -size 16 -interface SPIx4 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
+	echo "exit" >> generate_mcs.tcl
+	vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	for x in .mcs .prm; \
+	do cp $*$$x rev/$*_rev$$COUNT$$x; \
+	echo "Output: rev/$*_rev$$COUNT$$x"; done;

rtl/controller/tests/controller_tb.sv

@@ -0,0 +1,377 @@
+`timescale 1ns/1ps
+
+module tb_control;
+
+    localparam int unsigned DAC_DATA_WIDTH = 12;
+
+    
+    // Clocks / reset
+    logic eth_clk_in;
+    logic dac_clk_in;
+    logic adc_clk_in;
+    logic rst_n;
+
+    // axi stream (input)
+    logic [7:0] s_axis_tdata;
+    logic       s_axis_tvalid;
+    logic       s_axis_tready;
+    logic       s_axis_tlast;
+
+    // ADC side input
+    logic finish;
+
+    // DUT outputs
+    logic [31:0]                dac_pulse_width;
+    logic [31:0]                dac_pulse_period;
+    logic [DAC_DATA_WIDTH-1:0]  dac_pulse_height;
+    logic [15:0]                dac_pulse_num;
+
+    logic [31:0]                adc_pulse_period;
+    logic [15:0]                adc_pulse_num;
+
+    logic dac_start;
+    logic adc_start;
+    logic dac_rst;
+    logic adc_rst;
+
+    
+    // DUT
+    control #(
+        .DAC_DATA_WIDTH(DAC_DATA_WIDTH)
+    ) dut (
+        .eth_clk_in        (eth_clk_in),
+        .dac_clk_in        (dac_clk_in),
+        .adc_clk_in        (adc_clk_in),
+        .rst_n             (rst_n),
+
+        .s_axis_tdata      (s_axis_tdata),
+        .s_axis_tvalid     (s_axis_tvalid),
+        .s_axis_tready     (s_axis_tready),
+        .s_axis_tlast      (s_axis_tlast),
+
+        .finish            (finish),
+
+        .dac_pulse_width   (dac_pulse_width),
+        .dac_pulse_period  (dac_pulse_period),
+        .dac_pulse_height  (dac_pulse_height),
+        .dac_pulse_num     (dac_pulse_num),
+
+        .adc_pulse_period  (adc_pulse_period),
+        .adc_pulse_num     (adc_pulse_num),
+
+        .dac_start         (dac_start),
+        .adc_start         (adc_start),
+        .dac_rst           (dac_rst),
+        .adc_rst           (adc_rst)
+    );
+
+    
+    // Clock generation
+    initial begin
+        eth_clk_in = 1'b0;
+        forever #(1 * 4.000) eth_clk_in = ~eth_clk_in;   // 125 MHz
+    end
+
+    initial begin
+        dac_clk_in = 1'b0;
+        forever #(1 * 3.846153846) dac_clk_in = ~dac_clk_in; // ~130 MHz
+    end
+
+    initial begin
+        adc_clk_in = 1'b0;
+        forever #(1 * 7.692307692) adc_clk_in = ~adc_clk_in; // ~65 MHz
+    end
+
+    
+    // pulse counters and monitors for testing
+    int dac_rst_count;
+    int adc_rst_count;
+    int dac_start_count;
+    int adc_start_count;
+
+    always_ff @(posedge dac_clk_in) begin
+        if (!rst_n) begin
+            dac_rst_count   <= 0;
+            dac_start_count <= 0;
+        end else begin
+            if (dac_rst)   dac_rst_count   <= dac_rst_count + 1;
+            if (dac_start) dac_start_count <= dac_start_count + 1;
+        end
+    end
+
+    always_ff @(posedge adc_clk_in) begin
+        if (!rst_n) begin
+            adc_rst_count   <= 0;
+            adc_start_count <= 0;
+        end else begin
+            if (adc_rst)   adc_rst_count   <= adc_rst_count + 1;
+            if (adc_start) adc_start_count <= adc_start_count + 1;
+        end
+    end
+
+    
+    // some helpers for axi
+    task automatic axis_send_byte(input logic [7:0] data, input logic last);
+        begin
+            @(negedge eth_clk_in);
+            s_axis_tdata  <= data;
+            s_axis_tvalid <= 1'b1;
+            s_axis_tlast  <= last;
+
+            @(posedge eth_clk_in);
+            while (!s_axis_tready) begin
+                @(posedge eth_clk_in);
+            end
+
+            s_axis_tvalid <= 1'b0;
+            s_axis_tlast  <= 1'b0;
+            s_axis_tdata  <= '0;
+        end
+    endtask
+
+    task automatic send_cmd(input logic [7:0] cmd);
+        begin
+            axis_send_byte(cmd, 1'b1);
+        end
+    endtask
+
+    task automatic send_set_data(
+        input logic [31:0] pulse_width,
+        input logic [31:0] pulse_period,
+        input logic [15:0] pulse_num,
+        input logic [15:0] pulse_height_raw
+    );
+        logic [95:0] payload;
+        int i;
+        begin
+            // little-endian payload layout:
+            // [31:0]   pulse_width
+            // [63:32]  pulse_period
+            // [79:64]  pulse_num
+            // [95:80]  pulse_height_raw
+            payload = {pulse_height_raw, pulse_num, pulse_period, pulse_width};
+
+            axis_send_byte(8'h88, 1'b0); // CMD_SET_DATA
+
+            for (i = 0; i < 12; i++) begin
+                axis_send_byte(payload[i*8 +: 8], (i == 11));
+            end
+        end
+    endtask
+
+    task automatic pulse_finish;
+        begin
+            @(posedge adc_clk_in);
+            finish <= 1'b1;
+            @(posedge adc_clk_in);
+            finish <= 1'b0;
+        end
+    endtask
+
+    
+    // waiters
+    task automatic wait_dac_rst_count(input int expected, input int max_cycles = 100);
+        int i;
+        begin
+            for (i = 0; i < max_cycles; i++) begin
+                @(posedge dac_clk_in);
+                if (dac_rst_count >= expected) return;
+            end
+            $fatal(1, "Timeout waiting for dac_rst_count >= %0d, current=%0d", expected, dac_rst_count);
+        end
+    endtask
+
+    task automatic wait_adc_rst_count(input int expected, input int max_cycles = 100);
+        int i;
+        begin
+            for (i = 0; i < max_cycles; i++) begin
+                @(posedge adc_clk_in);
+                if (adc_rst_count >= expected) return;
+            end
+            $fatal(1, "Timeout waiting for adc_rst_count >= %0d, current=%0d", expected, adc_rst_count);
+        end
+    endtask
+
+    task automatic wait_dac_start_count(input int expected, input int max_cycles = 100);
+        int i;
+        begin
+            for (i = 0; i < max_cycles; i++) begin
+                @(posedge dac_clk_in);
+                if (dac_start_count >= expected) return;
+            end
+            $fatal(1, "Timeout waiting for dac_start_count >= %0d, current=%0d", expected, dac_start_count);
+        end
+    endtask
+
+    task automatic wait_adc_start_count(input int expected, input int max_cycles = 100);
+        int i;
+        begin
+            for (i = 0; i < max_cycles; i++) begin
+                @(posedge adc_clk_in);
+                if (adc_start_count >= expected) return;
+            end
+            $fatal(1, "Timeout waiting for adc_start_count >= %0d, current=%0d", expected, adc_start_count);
+        end
+    endtask
+
+    task automatic wait_cfg_applied(
+        input logic [31:0] exp_pulse_width,
+        input logic [31:0] exp_pulse_period,
+        input logic [15:0] exp_pulse_num,
+        input logic [15:0] exp_pulse_height_raw,
+        input int max_cycles = 200
+    );
+        logic [DAC_DATA_WIDTH-1:0] exp_dac_height;
+        int i;
+        begin
+            exp_dac_height = exp_pulse_height_raw[DAC_DATA_WIDTH-1:0];
+
+            for (i = 0; i < max_cycles; i++) begin
+                @(posedge eth_clk_in);
+                if ((dac_pulse_width  === exp_pulse_width ) &&
+                    (dac_pulse_period === exp_pulse_period) &&
+                    (dac_pulse_num    === exp_pulse_num   ) &&
+                    (dac_pulse_height === exp_dac_height  ) &&
+                    (adc_pulse_period === exp_pulse_period) &&
+                    (adc_pulse_num    === exp_pulse_num   )) begin
+                    return;
+                end
+            end
+
+            $fatal(1,
+                "Timeout waiting config outputs. Got: dac_width=%h dac_period=%h dac_num=%h dac_height=%h adc_period=%h adc_num=%h",
+                dac_pulse_width, dac_pulse_period, dac_pulse_num, dac_pulse_height,
+                adc_pulse_period, adc_pulse_num
+            );
+        end
+    endtask
+
+    
+    // Test sequence
+    logic [31:0] test_pulse_width;
+    logic [31:0] test_pulse_period;
+    logic [15:0] test_pulse_num;
+    logic [15:0] test_pulse_height_raw;
+
+    initial begin
+        // defaults
+        rst_n         = 1'b0;
+        s_axis_tdata  = '0;
+        s_axis_tvalid = 1'b0;
+        s_axis_tlast  = 1'b0;
+        finish        = 1'b0;
+
+        test_pulse_width      = 32'h11223344;
+        test_pulse_period     = 32'h55667788;
+        test_pulse_num        = 16'hA1B2;
+        test_pulse_height_raw = 16'h0CDE; // for DAC_DATA_WIDTH=12 => 12'hCDE
+
+        repeat (10) @(posedge eth_clk_in);
+        rst_n = 1'b1;
+
+        repeat (10) @(posedge eth_clk_in);
+
+        $display("[%0t] TEST 1: soft_reset", $time);
+        send_cmd(8'h0F);
+
+        wait_dac_rst_count(1);
+        wait_adc_rst_count(1);
+
+        if (dac_rst_count != 1) begin
+            $fatal(1, "Expected exactly one dac_rst pulse after first soft_reset, got %0d", dac_rst_count);
+        end
+        if (adc_rst_count != 1) begin
+            $fatal(1, "Expected exactly one adc_rst pulse after first soft_reset, got %0d", adc_rst_count);
+        end
+
+        $display("[%0t] TEST 1 passed", $time);
+
+        $display("[%0t] TEST 2: set_data", $time);
+        send_set_data(
+            test_pulse_width,
+            test_pulse_period,
+            test_pulse_num,
+            test_pulse_height_raw
+        );
+
+        wait_cfg_applied(
+            test_pulse_width,
+            test_pulse_period,
+            test_pulse_num,
+            test_pulse_height_raw
+        );
+
+        if (dac_pulse_width !== 32'h11223344) begin
+            $fatal(1, "dac_pulse_width mismatch: got %h expected %h", dac_pulse_width, 32'h11223344);
+        end
+        if (dac_pulse_period !== 32'h55667788) begin
+            $fatal(1, "dac_pulse_period mismatch: got %h expected %h", dac_pulse_period, 32'h55667788);
+        end
+        if (dac_pulse_num !== 16'hA1B2) begin
+            $fatal(1, "dac_pulse_num mismatch: got %h expected %h", dac_pulse_num, 16'hA1B2);
+        end
+        if (dac_pulse_height !== 12'hCDE) begin
+            $fatal(1, "dac_pulse_height mismatch: got %h expected %h", dac_pulse_height, 12'hCDE);
+        end
+        if (adc_pulse_period !== 32'h55667788) begin
+            $fatal(1, "adc_pulse_period mismatch: got %h expected %h", adc_pulse_period, 32'h55667788);
+        end
+        if (adc_pulse_num !== 16'hA1B2) begin
+            $fatal(1, "adc_pulse_num mismatch: got %h expected %h", adc_pulse_num, 16'hA1B2);
+        end
+
+        $display("[%0t] TEST 2 passed", $time);
+        
+        repeat (20) @(posedge eth_clk_in);
+
+        $display("[%0t] TEST 3: start", $time);
+        send_cmd(8'hF0);
+
+        wait_dac_start_count(1);
+        wait_adc_start_count(1);
+
+        if (dac_start_count != 1) begin
+            $fatal(1, "Expected exactly one dac_start pulse after first start, got %0d", dac_start_count);
+        end
+        if (adc_start_count != 1) begin
+            $fatal(1, "Expected exactly one adc_start pulse after first start, got %0d", adc_start_count);
+        end
+
+        $display("[%0t] TEST 3 start pulses passed", $time);
+
+        // release busy by finish pulse from ADC domain
+        $display("[%0t] Sending finish pulse", $time);
+        pulse_finish();
+
+        // a bit of wait for finish CDC back to ETH
+        repeat (20) @(posedge eth_clk_in);
+
+        // sanity check that commands are accepted again after finish
+        $display("[%0t] TEST 4: soft_reset after finish", $time);
+        send_cmd(8'h0F);
+
+        wait_dac_rst_count(2);
+        wait_adc_rst_count(2);
+
+        if (dac_rst_count != 2) begin
+            $fatal(1, "Expected exactly two dac_rst pulses total, got %0d", dac_rst_count);
+        end
+        if (adc_rst_count != 2) begin
+            $fatal(1, "Expected exactly two adc_rst pulses total, got %0d", adc_rst_count);
+        end
+
+        $display("[%0t] TEST 4 passed", $time);
+
+        $display("==============================================");
+        $display("ALL BASIC TESTS PASSED");
+        $display("dac_rst_count   = %0d", dac_rst_count);
+        $display("adc_rst_count   = %0d", adc_rst_count);
+        $display("dac_start_count = %0d", dac_start_count);
+        $display("adc_start_count = %0d", adc_start_count);
+        $display("==============================================");
+
+        #100;
+        $finish;
+    end
+
+endmodule

rtl/controller/tests/test_timing.xdc

@@ -0,0 +1,13 @@
+# Primary clocks
+create_clock -name eth_clk -period 8.000  [get_ports eth_clk_in]
+create_clock -name dac_clk -period 7.692  [get_ports dac_clk_in]
+create_clock -name adc_clk -period 15.385 [get_ports adc_clk_in]
+
+
+# Asynchronous clock groups
+# eth, dac, adc are independent domains
+
+set_clock_groups -name ASYNC_ETH_DAC_ADC -asynchronous \
+    -group [get_clocks eth_clk] \
+    -group [get_clocks dac_clk] \
+    -group [get_clocks adc_clk]

rtl/ethernet-udp/README.md

@@ -0,0 +1,54 @@
+# Ethernet UDP Stack
+
+Полный стек для Ethernet. Имеется поддержка ARP, ICMP (ping), и UDP. 
+- Рассчитан на скорость 1 ГБит/с
+- IP адреса устанавливаются заранее в axis_mac.sv
+- ARP и ICMP работают автоматически после инициализации модуля
+- Получаемые пейлоады по UDP выводятся через AXIS Master, когда получатель будет ready
+- Для отправки пейлоада по UDP используется сигнал-импульс send_req, который можно подать, когда модуль req_ready, после этого по готовности AXIS Slave можно начинать передавать данные пакета. Отправка следующего пакета будет доступна, когда данные предыдущего начнут отправляться (тоже сигнал req_ready).
+- Для прием имеется небольшая память на 2Кб. Пакет сначала помещается в нее и может быть отправлен по AXIS как только получатель готов. Если получатель не успевает принять полученный UDP пакет, то он может быть перезатерт новым.
+- Для отправки есть FIFO глубиной 2Кб. После запроса на отправку (send_req), при наполнении этого FIFO считается checksum пакета. Когда все data_length байт записаны - начинается отправка пакетов. Когда первые байты ушли - можно начинать передачу байт следующего пакета.
+## Структура src
+```
+├── eth - исходный код ethernet модуля
+│   ├── arbi - арбитер RGMII <-> GMII
+│   │   ├── gmii_arbi.v
+│   │   ├── gmii_rx_buffer.v
+│   │   └── gmii_tx_buffer.v
+│   ├── axis_mac.sv - обертка для AXIS
+│   ├── mac - основные файлы MAC части
+│   │   ├── arp_cache.v
+│   │   ├── crc.v
+│   │   ├── icmp_reply.v
+│   │   ├── mac_test.v
+│   │   ├── mac_top.v
+│   │   ├── rx - прием
+│   │   │   ├── arp_rx.v
+│   │   │   ├── ip_rx.v
+│   │   │   ├── mac_rx_top.v
+│   │   │   ├── mac_rx.v
+│   │   │   └── udp_rx.v
+│   │   └── tx - отправка
+│   │       ├── arp_tx.v
+│   │       ├── ip_tx_mode.v
+│   │       ├── ip_tx.v
+│   │       ├── mac_tx_mode.v
+│   │       ├── mac_tx_top.v
+│   │       ├── mac_tx.v
+│   │       └── udp_tx.v
+│   ├── reset.v
+│   └── util_gmii_to_rgmii.v
+└── ip: XCI файлы ip блоков 
+```
+
+## Тесты
+В tests есть Testbench, эмулирующий прием и отправку пакетов (test_axis_mac_rx.sv), а также имеются следующие тестовые проекты для отладки на ПЛИС AX7A035B:
+- Симуляция запускается в eth_axis через ```make sim```
+- eth_minimal - минимальный проект для теста PHY части. По умолчанию просто отправляет UDP пакет с фиксированным содержимым Hello ALINX на заданный IP. Если отправить UDP - то начнется трансляция пейлоада из принятого пакета.
+- eth_axis - проект с axis_mac и своеобразным echo-loopback. Начинает с ARP запроса, если получает ответ - то готов к работе. Можно отправлять UDP и получать эхо в ответ.
+
+## Сборка
+- Для сборки используется make
+- Собрать все вплоть до битстрима: ```make all```
+- Создать (если нету) и открыть вивадовский проект: ```make vivado```
+- По умолчанию в проектах используются IP 192.168.0.2 для платы и 192.168.0.3 для хоста, порт 8080 и на отправку, и на получение

rtl/ethernet-udp/src/eth/arbi/gmii_arbi.v

@@ -0,0 +1,177 @@
+`timescale 1ns / 1ps  
+//////////////////////////////////////////////////////////////////////////////////
+// Module Name:    ethernet_test 
+//////////////////////////////////////////////////////////////////////////////////
+module gmii_arbi
+(
+ input                 clk,
+ input                 rst_n,
+ input  [1:0]          speed,  
+ input                 link,                                            
+(* MARK_DEBUG="true" *)input                 gmii_rx_dv,
+(* MARK_DEBUG="true" *)input  [7:0]          gmii_rxd,
+(* MARK_DEBUG="true" *)input                 gmii_tx_en,
+(* MARK_DEBUG="true" *)input  [7:0]          gmii_txd,                       
+output reg [31:0]     pack_total_len,     //delay time
+output                e_rst_n,
+(* MARK_DEBUG="true" *)output reg            e_rx_dv,
+(* MARK_DEBUG="true" *)output reg [7:0]      e_rxd,
+(* MARK_DEBUG="true" *)output reg            e_tx_en,
+(* MARK_DEBUG="true" *)output reg [7:0]      e_txd
+);
+
+reg                    eth_1000m_en    ;
+wire                   eth_10_100m_en  ;
+reg                    eth_100m_en     ;
+reg                    eth_10m_en      ;
+reg [1:0]              speed_d0        ;
+reg [1:0]              speed_d1        ;
+reg [1:0]              speed_d2        ;
+reg                    link_d0         ;
+reg                    link_d1         ;
+reg                    link_d2         ;
+                       
+wire                   e10_100_tx_en   ;
+wire [7:0]             e10_100_txd     ;
+wire                   e10_100_rx_dv   ;
+wire [7:0]             e10_100_rxd     ;
+
+reg                    e_rst_en        ;
+reg [7:0]              e_rst_cnt       ;
+
+assign e_rst_n = link_d2 & e_rst_en ;
+
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+	begin
+	  speed_d0 <= 2'b00 ;
+	  speed_d1 <= 2'b00 ;
+	  speed_d2 <= 2'b00 ;
+	  link_d0  <= 1'b0 ;
+	  link_d1  <= 1'b0 ;
+	  link_d2  <= 1'b0 ;
+	end
+	else
+	begin
+	  speed_d0 <= speed    ;
+	  speed_d1 <= speed_d0 ;
+	  speed_d2 <= speed_d1 ;
+	  link_d0  <= link     ;
+	  link_d1  <= link_d0  ;
+	  link_d2  <= link_d1  ;
+	end
+  end
+
+
+
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+	begin
+	  eth_1000m_en   <= 1'b0  ;
+	  eth_100m_en    <= 1'b0 ;
+	  eth_10m_en     <= 1'b0 ;
+	  pack_total_len <= 32'd2500000 ;
+	end
+	else if (speed_d2 == 2'b10)           //1000M
+	begin
+	  eth_1000m_en   <= 1'b1 ;
+	  eth_100m_en    <= 1'b0 ;
+	  eth_10m_en     <= 1'b0 ;
+	  pack_total_len <= 32'd125000000 ;   //1s
+	end
+	else if (speed_d2 == 2'b01)           //100M
+	begin
+	  eth_1000m_en   <= 1'b0  ;
+	  eth_100m_en    <= 1'b1  ;
+	  eth_10m_en     <= 1'b0  ;
+	  pack_total_len <= 32'd25000000 ;    //1s
+	end 
+	else if (speed_d2 == 2'b00)           //10M
+	begin
+	  eth_1000m_en   <= 1'b0  ;
+	  eth_100m_en    <= 1'b0  ;
+	  eth_10m_en     <= 1'b1  ;
+	  pack_total_len <= 32'd2500000 ;     //1s
+	end
+	 
+  end
+
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+	begin
+	  e_rx_dv   <= 1'b0 ;
+	  e_rxd     <= 8'd0 ;
+	  e_tx_en   <= 1'b0 ;
+	  e_txd     <= 8'd0 ;
+	end
+	else if (eth_1000m_en)
+	begin
+	  e_rx_dv   <= gmii_rx_dv  ;
+	  e_rxd     <= gmii_rxd    ;
+	  e_tx_en   <= gmii_tx_en  ;
+	  e_txd     <= gmii_txd    ;
+	end
+	else if (eth_100m_en | eth_10m_en)
+	begin
+	  e_rx_dv   <= e10_100_rx_dv ;
+	  e_rxd     <= e10_100_rxd   ;
+	  e_tx_en   <= e10_100_tx_en ;
+	  e_txd     <= e10_100_txd   ;
+	end
+  end  
+
+
+ 
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      e_rst_en <= 1'b1 ;
+    else if (speed_d2 != speed_d1)
+      e_rst_en <= 1'b0 ;
+    else if (e_rst_cnt == 8'd200)
+	   e_rst_en <= 1'b1 ;
+  end
+
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      e_rst_cnt <= 8'd0 ;
+    else if (~e_rst_en)
+      e_rst_cnt <= e_rst_cnt + 1'b1 ;	  
+    else 
+	  e_rst_cnt <= 8'd0 ;
+  end  
+
+assign eth_10_100m_en = eth_100m_en | eth_10m_en ;
+
+gmii_tx_buffer tx_buffer_inst
+(
+ .clk                    (clk                 ),
+ .rst_n                  (e_rst_n             ), 
+ .eth_10_100m_en         (eth_10_100m_en      ),
+ .link                   (e_rst_n             ),
+ .gmii_tx_en             (gmii_tx_en          ),
+ .gmii_txd               (gmii_txd            ), 
+ .e10_100_tx_en          (e10_100_tx_en       ),
+ .e10_100_txd            (e10_100_txd         ) 
+);
+	
+
+gmii_rx_buffer  rx_buffer_inst
+(
+ .clk                    (clk                 ),
+ .rst_n                  (e_rst_n             ),
+ .link                   (e_rst_n             ),
+ .eth_100m_en            (eth_100m_en         ),
+ .eth_10m_en             (eth_10m_en          ),
+ .gmii_rx_dv             (gmii_rx_dv          ),
+ .gmii_rxd               (gmii_rxd            ), 
+ .e10_100_rx_dv          (e10_100_rx_dv       ),
+ .e10_100_rxd            (e10_100_rxd         )
+ 
+);
+    
+endmodule

rtl/ethernet-udp/src/eth/arbi/gmii_rx_buffer.v

@@ -0,0 +1,305 @@
+`timescale 1ns / 1ps  
+//////////////////////////////////////////////////////////////////////////////////
+// Module Name:    ethernet_test 
+//////////////////////////////////////////////////////////////////////////////////
+module gmii_rx_buffer
+(
+ input              clk,
+ input              rst_n,
+ input              eth_100m_en,   //ethernet 100M enable
+ input              eth_10m_en,    //ethernet 100M enable
+ input              link,          //ethernet link signal
+ input              gmii_rx_dv,    //gmii rx dv
+ input  [7:0]       gmii_rxd,      //gmii rxd
+ 
+ (* MARK_DEBUG="true" *)output reg         e10_100_rx_dv, //ethernet 10/100 rx_dv
+ (* MARK_DEBUG="true" *)output    [7:0]    e10_100_rxd    //ethernet 10/100 rxd
+ 
+);
+
+
+reg  [15:0]           rx_cnt        ;   //write fifo counter
+reg                   rx_wren       ;   //write fifo wren
+reg  [7:0]            rx_wdata      ;   //write fifo data
+reg  [15:0]           rx_data_cnt   ;   //read fifo counter
+reg                   rx_rden       ;   //read fifo rden
+wire [7:0]            rx_rdata      ;   //read fifo data
+reg  [3:0]            rxd_high      ;   //rxd high 4 bit
+reg  [3:0]            rxd_low       ;   //rxd low 4 bit
+                      
+(* MARK_DEBUG="true" *)reg                   gmii_rx_dv_d0 ;
+(* MARK_DEBUG="true" *)reg                   gmii_rx_dv_d1 ;
+reg                   gmii_rx_dv_d2 ;
+                      
+reg  [15:0]           pack_len      ;   //package length                  
+reg  [1:0]            len_cnt       ;   //length latch counter
+wire [4:0]            pack_num      ;   //length fifo usedw
+reg                   rx_len_wren   ;   //length wren
+reg  [15:0]           rx_len_wdata  ;   //length write data
+reg                   rx_len_rden   ;   //length rden
+wire [15:0]           rx_len        ;   //legnth read data
+
+
+localparam IDLE             = 4'd0 ;
+localparam CHECK_FIFO       = 4'd1 ;
+localparam LEN_LATCH        = 4'd2 ;
+localparam REC_WAIT         = 4'd3 ;
+localparam READ_FIFO        = 4'd4 ;
+localparam REC_END          = 4'd5 ;
+
+reg [3:0]    state  ;
+reg [3:0]    next_state ;
+
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      state  <=  IDLE  ;
+    else
+      state  <= next_state ;  
+  end
+  
+always @(*)
+  begin
+    case(state)
+	IDLE  : 
+	  begin
+		  next_state <= CHECK_FIFO ;
+	  end
+    CHECK_FIFO :
+      begin
+	    if (pack_num > 5'd0)                // if length fifo usedw > 0, means there is package in data fifo
+		  next_state <= LEN_LATCH ;
+		else 
+		  next_state <= CHECK_FIFO ;		 
+		end	
+	LEN_LATCH:
+	  begin
+	    if (len_cnt == 2'd3)               // delay some clock
+		  next_state <= REC_WAIT ;
+		else 
+		  next_state <= LEN_LATCH ;
+	  end
+	REC_WAIT :
+	    next_state <= READ_FIFO ;	
+	READ_FIFO :
+      begin
+	    if (rx_data_cnt == pack_len - 1)   // when reach package length read end
+		  next_state <= REC_END ;
+		else 
+		  next_state <= READ_FIFO ;
+		end	
+	REC_END :
+	      next_state <= IDLE ;
+    default :
+	   next_state <= IDLE ;
+	endcase
+  end  
+
+
+
+  
+/*************************************************
+write length to fifo
+*************************************************/
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+    begin
+	  gmii_rx_dv_d0  <= 1'b0 ;
+	  gmii_rx_dv_d1  <= 1'b0 ;
+	  gmii_rx_dv_d2  <= 1'b0 ;
+	end
+	else
+	begin
+	  gmii_rx_dv_d0  <= gmii_rx_dv  ;
+	  gmii_rx_dv_d1  <= gmii_rx_dv_d0 ;
+	  gmii_rx_dv_d2  <= gmii_rx_dv_d1 ;
+	end
+  end
+//write rx length wren to fifo when gmii_rx_dv negedge
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+	  rx_len_wren <=  1'b0 ;
+	else if (gmii_rx_dv == 1'b0 && gmii_rx_dv_d0 == 1'b1)
+	  rx_len_wren <=  eth_100m_en | eth_10m_en  ;
+	else 
+	  rx_len_wren <=  1'b0 ;
+end
+
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+	  rx_cnt   <= 16'd0  ;
+	//else if (eth_10m_en &  (gmii_rx_dv_d0 | gmii_rx_dv_d1))     //when 10M mode, there is one unnecessary 4 bits data need to be take out
+	else if (eth_10m_en &  (gmii_rx_dv | gmii_rx_dv_d0))     //when 10M mode, there is one unnecessary 4 bits data need to be take out
+	  rx_cnt   <= rx_cnt + 1'b1 ;
+	else if (eth_100m_en & (gmii_rx_dv | gmii_rx_dv_d1))
+	  rx_cnt   <= rx_cnt + 1'b1 ;
+	else if (state == REC_WAIT)
+	  rx_cnt   <= 16'd0  ;
+  end
+  
+//write length to fifo 
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+	  rx_len_wdata <= 16'd0 ;
+	else
+	  rx_len_wdata <=  rx_cnt ;
+end
+
+
+
+/*************************************************
+write data to fifo
+*************************************************/
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+    begin
+	  rxd_high   <= 4'd0 ;
+	  rxd_low    <= 4'd0 ;
+	end
+	else if (gmii_rx_dv | gmii_rx_dv_d1)
+	begin
+	  if (rx_cnt[0])
+	  begin
+        rxd_high <= gmii_rxd[3:0] ;	
+	  end
+      else
+	  begin
+        rxd_low  <= gmii_rxd[3:0] ;
+	  end
+    end
+    else
+    begin
+	  rxd_high <= 4'd0 ;
+	  rxd_low  <= 4'd0 ;
+    end
+  end	
+
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+    begin
+	  rx_wren  <= 1'b0 ;	
+	  rx_wdata <= 8'd0 ;
+	end
+	else if (gmii_rx_dv_d1)
+	begin
+	  if (rx_cnt[0])
+	  begin
+        rx_wren  <= 1'b0 ;		
+	  end
+      else
+	  begin
+		rx_wdata <= {rxd_high,rxd_low} ;
+        rx_wren  <= eth_100m_en | eth_10m_en ;		
+	  end
+    end
+    else
+    begin
+	  rx_wren  <= 1'b0 ;	
+	  rx_wdata <= 8'd0 ;
+    end
+  end  
+
+/*************************************************
+read length from fifo
+*************************************************/
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+	  rx_len_rden <=  1'b0 ;
+	else if (state == LEN_LATCH && len_cnt == 2'd0)
+	  rx_len_rden <=  eth_100m_en | eth_10m_en  ;
+	else 
+	  rx_len_rden <=  1'b0 ;
+end
+
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+	  len_cnt <=  2'd0 ;
+	else if (state == LEN_LATCH)
+	  len_cnt <=  len_cnt + 1'b1 ;
+	else 
+	  len_cnt <=  2'd0 ;
+end
+//package total length  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+	  pack_len <= 16'd0 ;
+	else if (state == REC_WAIT)
+	  pack_len <= rx_len/2 ;
+end
+
+
+/*************************************************
+read data from fifo
+*************************************************/	
+
+
+//read data counter  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+	  rx_data_cnt   <= 16'd0  ;
+	else if (state == READ_FIFO)
+	  rx_data_cnt   <= rx_data_cnt + 1'b1 ;
+	else
+	  rx_data_cnt   <= 16'd0  ;
+  end
+
+
+//read enable 
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+	  rx_rden   <= 1'b0  ;
+	else if (state == READ_FIFO)
+	  rx_rden   <= eth_100m_en | eth_10m_en  ;
+	else 
+	  rx_rden   <= 1'b0  ;
+  end 
+
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+	  e10_100_rx_dv   <= 1'b0  ;
+	else 
+	  e10_100_rx_dv   <= rx_rden  ;
+  end  
+
+assign e10_100_rxd = rx_rdata ;
+
+
+ eth_data_fifo rx_fifo 
+ (
+    .clk        (clk            ),                // input wire clk
+    .rst        (~link          ),                // input wire rst
+    .din        (rx_wdata       ),                // input wire [7 : 0] din
+    .wr_en      (rx_wren        ),            // input wire wr_en
+    .rd_en      (rx_rden        ),            // input wire rd_en
+    .dout       (rx_rdata       ),              // output wire [7 : 0] dout
+    .full       (               ),              // output wire full
+    .empty      (               ),            // output wire empty
+    .data_count (               )  // output wire [11 : 0] data_count
+    );  
+ 
+len_fifo rx_len_fifo
+    (	
+    .clk        (clk            ),                // input wire clk
+    .rst        (~link          ),                // input wire rst
+    .din        (rx_len_wdata   ),                // input wire [7 : 0] din
+    .wr_en      (rx_len_wren    ),            // input wire wr_en
+    .rd_en      (rx_len_rden    ),            // input wire rd_en
+    .dout       (rx_len         ),              // output wire [7 : 0] dout
+    .full       (               ),              // output wire full
+    .empty      (               ),            // output wire empty
+    .data_count (pack_num       )  // output wire [11 : 0] data_count
+    );  
+endmodule

rtl/ethernet-udp/src/eth/arbi/gmii_tx_buffer.v

@@ -0,0 +1,298 @@
+`timescale 1ns / 1ps  
+//////////////////////////////////////////////////////////////////////////////////
+// Module Name:    ethernet_test 
+//////////////////////////////////////////////////////////////////////////////////
+module gmii_tx_buffer
+(
+ input              clk,
+ input              rst_n, 
+ input              eth_10_100m_en,      //ethernet 10M/100M enable
+ input              link,                //ethernet link signal
+ input              gmii_tx_en,          //gmii tx enable
+ input  [7:0]       gmii_txd,            //gmii txd
+ output reg         e10_100_tx_en,       //ethernet 10/100M tx enable
+ output reg [7:0]   e10_100_txd          //ethernet 10/100M txd
+
+ 
+);
+
+(* MARK_DEBUG="true" *)reg  [7:0]            tx_wdata    ;      //tx data fifo write data
+(* MARK_DEBUG="true" *)reg                   tx_wren     ;      //tx data fifo write enable
+(* MARK_DEBUG="true" *)reg                   tx_rden     ;      //tx data fifo read enable
+(* MARK_DEBUG="true" *)reg  [15:0]           tx_data_cnt ;      //tx data counter
+(* MARK_DEBUG="true" *)wire [7:0]            tx_rdata    ;      //tx fifo read data
+                      
+                                  
+reg  [16:0]           pack_len    ;      //package length
+reg                   tx_en       ;      //tx enable
+reg  [3:0]            txd_high    ;      //high 4 bits
+reg  [3:0]            txd_low     ;      //low 4 bits
+                                  
+reg                   tx_en_d0    ; 
+reg                   tx_en_d1    ;
+                      
+reg   [15:0]          tx_len_cnt    ;    //tx length counter
+reg                   gmii_tx_en_d0 ;                          
+reg   [1:0]           len_cnt       ;    //length latch counter
+wire  [4:0]           pack_num      ;    //length fifo usedw
+reg                   tx_len_wren   ;    //length fifo wren
+reg                   tx_len_rden   ;    //length fifo rden
+wire  [15:0]          tx_len_wdata  ;    //length fifo write data
+wire  [15:0]          tx_len        ;    //length fifo read data
+
+
+
+localparam IDLE            = 4'd0 ;
+localparam CHECK_FIFO      = 4'd1 ;
+localparam LEN_LATCH       = 4'd2 ;
+localparam SEND_WAIT       = 4'd3 ;
+localparam SEND            = 4'd4 ;
+localparam SEND_WAIT_1     = 4'd5 ;
+localparam SEND_END        = 4'd6 ;
+
+
+reg [3:0]    state  ;
+reg [3:0]    next_state ;
+
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      state  <=  IDLE  ;
+    else
+      state  <= next_state ;  
+  end
+
+
+  
+always @(*)
+  begin
+    case(state)
+	IDLE  :        
+	  begin
+		  next_state <= CHECK_FIFO ;
+	  end
+	CHECK_FIFO :   
+      begin
+	    if (pack_num > 5'd0)                  //check length fifo, if usedw > 0 ,there is a package in data fifo
+		  next_state <= LEN_LATCH ;
+		else 
+		  next_state <= CHECK_FIFO ;		 
+		end	
+	LEN_LATCH:     
+	  begin
+	    if (len_cnt == 2'd3)                  //wait for read length fifo data
+		  next_state <= SEND_WAIT ;
+		else 
+		  next_state <= LEN_LATCH ;
+	  end
+	SEND_WAIT :    
+	  next_state <= SEND ;
+	SEND :         
+      begin
+	    if (tx_data_cnt == pack_len - 1)      //read data fifo and send out
+		  next_state <= SEND_WAIT_1 ;
+		else 
+		  next_state <= SEND ;
+		end	
+	SEND_WAIT_1 :   
+      begin
+	    if (tx_data_cnt == pack_len + 1)      //wait some clock for data latch
+		  next_state <= SEND_END ;
+		else 
+		  next_state <= SEND_WAIT_1 ;
+		end	
+	SEND_END :    
+	      next_state <= IDLE ;
+    default :
+	   next_state <= IDLE ;
+	endcase
+  end  
+/*************************************************
+write length to tx_len_fifo
+*************************************************/
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+	  gmii_tx_en_d0 <= 1'b0 ;
+	else
+	  gmii_tx_en_d0 <=  gmii_tx_en  ;
+end
+//write tx length to fifo when gmii_tx_en negedge
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+	  tx_len_wren <=  1'b0 ;
+	else if (gmii_tx_en == 1'b0 && gmii_tx_en_d0 == 1'b1)
+	  tx_len_wren <=  eth_10_100m_en  ;
+	else 
+	  tx_len_wren <=  1'b0 ;
+end
+//calculate tx length  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+	  tx_len_cnt <= 16'd0 ;
+	else if (gmii_tx_en)
+	  tx_len_cnt <=  tx_len_cnt + 1'b1  ;
+	else if (tx_len_wren)
+	  tx_len_cnt <= 16'd0 ;
+end
+
+assign tx_len_wdata = tx_len_cnt ;     //write length data 
+
+/*************************************************
+read length from tx_len_fifo
+*************************************************/
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+	  tx_len_rden <=  1'b0 ;
+	else if (state == LEN_LATCH && len_cnt == 2'd0)
+	  tx_len_rden <=  eth_10_100m_en  ;
+	else 
+	  tx_len_rden <=  1'b0 ;
+end
+
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+	  len_cnt <=  2'd0 ;
+	else if (state == LEN_LATCH)
+	  len_cnt <=  len_cnt + 1'b1 ;
+	else 
+	  len_cnt <=  2'd0 ;
+end
+//package total length  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+	  pack_len <= 17'd0 ;
+	else if (state == SEND_WAIT)
+	  pack_len <= 2*(tx_len) ;
+end
+//write data to tx_fifo
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+	begin
+	  tx_wren   <= 1'b0 ;
+	  tx_wdata  <= 8'd0 ;
+	end
+	else
+	begin
+	  tx_wren   <= gmii_tx_en & eth_10_100m_en ;
+	  tx_wdata  <= gmii_txd ;
+	end
+  end  
+
+/*************************************************
+read tx_fifo
+*************************************************/	
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+	  tx_data_cnt   <= 16'd0  ;
+	else if (state == SEND || state == SEND_WAIT_1)
+	  tx_data_cnt   <= tx_data_cnt + 1'b1 ;
+	else 
+	  tx_data_cnt   <= 16'd0  ;
+  end
+//read data enable 
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+	  tx_rden   <= 1'b0  ;
+	else if (state == SEND)
+	  tx_rden   <= ~tx_data_cnt[0] & eth_10_100m_en ;
+	else 
+	  tx_rden   <= 1'b0  ;
+  end
+//gmii tx enable
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+	  tx_en   <= 1'b0  ;
+	else if (state == SEND)
+	  tx_en   <= 1'b1 ;
+	else 
+	  tx_en   <= 1'b0  ;
+  end
+
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+	begin
+	  tx_en_d0   <= 1'b0  ;
+	  tx_en_d1   <= 1'b0  ;
+	end
+	else
+	begin
+	  tx_en_d0   <= tx_en ;
+	  tx_en_d1   <= tx_en_d0 ;
+	end
+  end
+
+
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+	begin
+	  txd_high <= 4'd0 ;
+	  txd_low  <= 4'd0 ;
+	end
+	else
+	begin
+	  if (tx_data_cnt[0])
+	    txd_high   <= tx_rdata[7:4]  ;
+	  else 
+	    txd_low   <= tx_rdata[3:0]  ;
+	end
+  end  
+
+//ethernet 10/100M tx enable  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+	  e10_100_tx_en   <= 1'b0  ;
+	else
+	  e10_100_tx_en   <= tx_en_d1 ;
+  end
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+	  e10_100_txd   <= 8'd0  ;
+	else if (tx_data_cnt[0])
+	  e10_100_txd   <= {txd_low[3:0],txd_low[3:0]} ;
+	else
+	  e10_100_txd   <= {txd_high[3:0],txd_high[3:0]} ;
+  end 
+
+
+ eth_data_fifo tx_fifo 
+ (
+    .clk        (clk            ),                // input wire clk
+    .rst        (~link          ),                // input wire rst
+    .din        (tx_wdata       ),                // input wire [7 : 0] din
+    .wr_en      (tx_wren        ),            // input wire wr_en
+    .rd_en      (tx_rden        ),            // input wire rd_en
+    .dout       (tx_rdata       ),              // output wire [7 : 0] dout
+    .full       (               ),              // output wire full
+    .empty      (               ),            // output wire empty
+    .data_count (               )  // output wire [11 : 0] data_count
+    );  
+ 
+len_fifo tx_len_fifo
+    (	
+    .clk        (clk            ),                // input wire clk
+    .rst        (~link          ),                // input wire rst
+    .din        (tx_len_wdata   ),                // input wire [7 : 0] din
+    .wr_en      (tx_len_wren    ),            // input wire wr_en
+    .rd_en      (tx_len_rden    ),            // input wire rd_en
+    .dout       (tx_len         ),              // output wire [7 : 0] dout
+    .full       (               ),              // output wire full
+    .empty      (               ),            // output wire empty
+    .data_count (pack_num       )  // output wire [11 : 0] data_count
+    );  
+    
+endmodule

rtl/ethernet-udp/src/eth/axis_mac.sv

@@ -0,0 +1,435 @@
+// ethernet MAC with axi stream IO with UDP
+
+`timescale 1 ns / 1 ns
+
+module axis_mac
+(
+    input                rst_n,
+    input                gmii_tx_clk,
+    input                gmii_rx_clk,
+    input                gmii_rx_dv,
+    input  [7:0]         gmii_rxd,
+
+    output reg           gmii_tx_en,
+    output reg [7:0]     gmii_txd,
+
+    // AXI-stream RX output (clock domain = gmii_rx_clk)
+    (* MARK_DEBUG="true" *)output reg  [7:0]    m_axis_rx_tdata,
+    (* MARK_DEBUG="true" *)output reg           m_axis_rx_tvalid,
+    (* MARK_DEBUG="true" *)input  wire          m_axis_rx_tready,
+    (* MARK_DEBUG="true" *)output reg           m_axis_rx_tlast,
+    (* MARK_DEBUG="true" *)output wire [15:0]   udp_rec_data_length,
+
+    // tx part
+    (* MARK_DEBUG="true" *)input  wire        send_req,
+    input  wire [15:0] data_length,
+    (* MARK_DEBUG="true" *)output reg         req_ready,
+
+    (* MARK_DEBUG="true" *)input  wire [7:0]  s_axis_tx_tdata,
+    (* MARK_DEBUG="true" *)input  wire        s_axis_tx_tvalid,
+    (* MARK_DEBUG="true" *)output reg         s_axis_tx_tready,
+    (* MARK_DEBUG="true" *)input  wire        s_axis_tx_tlast
+);
+
+    // ----------------------------------------------------------------
+    // GMII RX input registering
+    // ----------------------------------------------------------------
+    reg        gmii_rx_dv_d0;
+    reg [7:0]  gmii_rxd_d0;
+
+    always @(posedge gmii_rx_clk or negedge rst_n) begin
+        if (!rst_n) begin
+            gmii_rx_dv_d0 <= 1'b0;
+            gmii_rxd_d0   <= 8'd0;
+        end else begin
+            gmii_rx_dv_d0 <= gmii_rx_dv;
+            gmii_rxd_d0   <= gmii_rxd;
+        end
+    end
+
+    // ----------------------------------------------------------------
+    // TX path from mac_top
+    // ----------------------------------------------------------------
+    wire       gmii_tx_en_tmp;
+    wire [7:0] gmii_txd_tmp;
+
+    always @(posedge gmii_tx_clk or negedge rst_n) begin
+        if (!rst_n) begin
+            gmii_tx_en <= 1'b0;
+            gmii_txd   <= 8'd0;
+        end else begin
+            gmii_tx_en <= gmii_tx_en_tmp;
+            gmii_txd   <= gmii_txd_tmp;
+        end
+    end
+
+    // TX signals
+    reg  [7:0]  tx_ram_wr_data;
+    reg         tx_ram_wr_en;
+    reg  [15:0] udp_send_data_length;
+    reg         udp_tx_req;
+    reg         arp_request_req;
+    wire        mac_send_end;
+
+    wire        udp_ram_data_req;
+    wire        udp_tx_end;
+    wire        almost_full;
+    (* MARK_DEBUG="true" *)wire        arp_found;
+    wire        mac_not_exist;
+    wire [15:0] udp_ram_data_count;
+
+    // RX signals
+    reg  [10:0] udp_rec_ram_read_addr;
+    wire [7:0]  udp_rec_ram_rdata;
+    
+    wire        udp_rec_data_valid;
+
+    mac_top mac_top0 (
+        .gmii_tx_clk               (gmii_tx_clk),
+        .gmii_rx_clk               (gmii_rx_clk),
+        .rst_n                     (rst_n),
+
+        .source_mac_addr           (48'h00_0a_35_01_fe_c0),
+        .TTL                       (8'h80),
+        .source_ip_addr            (32'hc0a80002),   // 192.168.0.2
+        .destination_ip_addr       (32'hc0a80003),   // 192.168.0.3
+        .udp_send_source_port      (16'h1f90),       // 8080
+        .udp_send_destination_port (16'h1f90),       // 8080
+
+        .ram_wr_data               (tx_ram_wr_data),
+        .ram_wr_en                 (tx_ram_wr_en),
+        .udp_ram_data_req          (udp_ram_data_req),
+        .udp_send_data_length      (udp_send_data_length),
+        .udp_tx_end                (udp_tx_end),
+        .almost_full               (almost_full),
+
+        .udp_tx_req                (udp_tx_req),
+        .arp_request_req           (arp_request_req),
+
+        .mac_send_end              (mac_send_end),
+        .mac_data_valid            (gmii_tx_en_tmp),
+        .mac_tx_data               (gmii_txd_tmp),
+
+        .rx_dv                     (gmii_rx_dv_d0),
+        .mac_rx_datain             (gmii_rxd_d0),
+
+        .udp_rec_ram_rdata         (udp_rec_ram_rdata),
+        .udp_rec_ram_read_addr     (udp_rec_ram_read_addr),
+        .udp_rec_data_length       (udp_rec_data_length),
+        .udp_rec_data_valid        (udp_rec_data_valid),
+
+        .arp_found                 (arp_found),
+        .mac_not_exist             (mac_not_exist)
+    );
+
+    // Detect "new packet ready" on udp_rec_data_valid rising edge
+    reg udp_rec_data_valid_d0;
+
+    always @(posedge gmii_rx_clk or negedge rst_n) begin
+        if (!rst_n)
+            udp_rec_data_valid_d0 <= 1'b0;
+        else
+            udp_rec_data_valid_d0 <= udp_rec_data_valid;
+    end
+
+    wire udp_pkt_done = udp_rec_data_valid & ~udp_rec_data_valid_d0;
+
+    // ----------------------------------------------------------------
+    // RX RAM -> AXI-stream bridge
+    //
+    // Assumption:
+    //   udp_rec_data_length includes 8-byte UDP header,
+    //   so payload length = udp_rec_data_length - 8
+    //
+    // This implementation is simple and safe:
+    // - start on udp_pkt_done
+    // - read bytes 0 .. payload_len-1 from RX RAM
+    // - output them on AXIS
+    //
+    // ----------------------------------------------------------------
+    localparam RX_IDLE  = 2'd0;
+    localparam RX_NOTREADY  = 2'd1;
+    localparam RX_START  = 2'd2;
+    localparam RX_DATA  = 2'd3;
+
+    (* MARK_DEBUG="true" *) reg [1:0]  rx_state;
+    (* MARK_DEBUG="true" *) reg [15:0] rx_payload_len;
+    (* MARK_DEBUG="true" *) reg [15:0] rx_index;
+
+    always @(posedge gmii_rx_clk or negedge rst_n) begin
+        if (!rst_n) begin
+            rx_state              <= RX_IDLE;
+            rx_payload_len        <= 16'd0;
+            rx_index              <= 16'd0;
+            udp_rec_ram_read_addr <= 11'd0;
+
+            m_axis_rx_tdata       <= 8'd0;
+            m_axis_rx_tvalid      <= 1'b0;
+            m_axis_rx_tlast       <= 1'b0;
+
+        end else begin
+            case (rx_state)
+                RX_IDLE: begin
+                    m_axis_rx_tvalid <= 1'b0;
+                    m_axis_rx_tlast  <= 1'b0;
+                    rx_index         <= 16'd0;
+                    udp_rec_ram_read_addr <= 11'd0;
+
+                    if (udp_pkt_done) begin
+                        // protect against pathological short values
+                        if (udp_rec_data_length > 16'd8) begin
+                            rx_payload_len        <= udp_rec_data_length - 16'd8;
+                            udp_rec_ram_read_addr <= 11'd0;   // issue read for byte 0
+                            rx_state              <= RX_NOTREADY;
+                        end else begin
+                            rx_payload_len <= 16'd0;
+                            rx_state       <= RX_IDLE;
+                        end
+                    end
+                end
+
+                // one cycle for synchronous BRAM read latency
+                RX_NOTREADY: begin
+                    m_axis_rx_tvalid <= 1'b0;
+                    m_axis_rx_tlast  <= 1'b0;
+
+                    if (m_axis_rx_tready)
+                        rx_state         <= RX_START;
+                end
+
+                RX_START: begin
+                    if (m_axis_rx_tready) begin
+                        // put current data
+                        // end of data?
+                        if (rx_index == (rx_payload_len - 1)) begin
+                            rx_state <= RX_IDLE;
+                        end else begin 
+                            rx_state <= RX_DATA;
+                        end
+
+                        // always increment pointer
+                        rx_index <= rx_index + 1'b1;
+                        udp_rec_ram_read_addr <= rx_index + 1'b1; // next byte
+                    end else begin 
+                        rx_state <= RX_NOTREADY;
+
+                    end
+                end
+
+                RX_DATA: begin
+                    // hold valid until accepted
+                    if (!m_axis_rx_tready) begin
+                        // take a break while not ready
+                        m_axis_rx_tvalid <= m_axis_rx_tvalid;
+                        m_axis_rx_tlast  <= m_axis_rx_tlast;
+                        rx_state         <= RX_NOTREADY;
+                        // reset increment
+                        rx_index <= rx_index - 1'b1;
+                        udp_rec_ram_read_addr <= rx_index - 1'b1;
+                    end else begin
+                        // present current byte from RAM
+                        m_axis_rx_tdata  <= udp_rec_ram_rdata;
+                        m_axis_rx_tvalid <= 1'b1;
+                        m_axis_rx_tlast  <= (rx_index == (rx_payload_len));
+                        if (rx_index == (rx_payload_len)) begin
+                            // last byte accepted immediately if ready=1,
+                            // otherwise valid/last remain asserted until ready
+                            rx_state <= RX_IDLE;
+                        end
+
+                        rx_index <= rx_index + 1'b1;
+                        udp_rec_ram_read_addr <= rx_index + 1'b1; // next byte
+                    end
+                end
+
+                default: begin
+                    rx_state         <= RX_IDLE;
+                    m_axis_rx_tvalid <= 1'b0;
+                    m_axis_rx_tlast  <= 1'b0;
+                end
+            endcase
+        end
+    end
+
+    // ----------------------------------------------------------------
+    // TX FSM
+    // Semantics:
+    //   - send_req/data_length form a packet send request
+    //   - udp_tx_req is held HIGH until udp_ram_data_req pulses
+    //   - udp_ram_data_req is a pulse - start feeding payload now to RAM
+    //   - AXIS ready is asserted only during payload write phase
+    // ----------------------------------------------------------------
+    
+    
+    localparam TX_IDLE         = 3'd0;
+    localparam TX_ARP_REQ      = 3'd1;
+    localparam TX_ARP_SEND     = 3'd2;
+    localparam TX_WAIT_ARP     = 3'd3;
+    localparam TX_WAIT_RAM_REQ = 3'd4;
+    localparam TX_STREAM       = 3'd5;
+    localparam TX_WAIT_DRAIN   = 3'd6;
+
+    (* MARK_DEBUG="true" *)reg [2:0]  tx_state;
+    
+    assign arp_request_req  = (tx_state == TX_ARP_REQ) ;
+
+    reg [15:0] tx_req_len;
+    reg [15:0] tx_bytes_written;
+    reg [15:0] tx_release_threshold;
+
+    reg        tx_req_inflight;
+    
+    // register for long arp timeout, if no got no response
+    reg [31:0] arp_delay;
+    reg arp_cached;
+
+    always @(posedge gmii_tx_clk or negedge rst_n) begin
+        if (!rst_n) begin
+            tx_state             <= TX_IDLE;
+
+            tx_ram_wr_data       <= 8'd0;
+            arp_cached           <= 1'b0;
+            tx_ram_wr_en         <= 1'b0;
+            udp_send_data_length <= 16'd0;
+            udp_tx_req           <= 1'b0;
+            arp_delay            <= 32'b0;
+
+            s_axis_tx_tready     <= 1'b0;
+            req_ready            <= 1'b0;
+
+            tx_req_len           <= 16'd0;
+            tx_bytes_written     <= 16'd0;
+            tx_release_threshold <= 16'd0;
+
+            tx_req_inflight      <= 1'b0;
+        end else begin
+            // defaults
+            tx_ram_wr_en    <= 1'b0;
+
+            case (tx_state)
+                // Ready to accept a new packet request
+                TX_IDLE: begin
+                    udp_tx_req       <= 1'b0;
+                    s_axis_tx_tready <= 1'b0;
+                    tx_bytes_written <= 16'd0;
+                    tx_req_inflight  <= 1'b0;
+
+                    req_ready <= arp_cached && !almost_full;
+
+                    if (send_req && req_ready) begin
+                        tx_req_len           <= data_length;
+                        udp_send_data_length <= data_length;
+                        tx_req_inflight      <= 1'b1;
+
+                        // threshold for allowing next packet
+                        // to be written to the RAM
+                        if (data_length > 16'd16)
+                            tx_release_threshold <= data_length - 16'd16;
+                        else
+                            tx_release_threshold <= 16'd0;
+
+                            tx_state <= TX_WAIT_RAM_REQ;
+                    end
+                    
+                    // arp check
+                    if (!arp_cached) begin
+                        tx_state <= TX_ARP_REQ;
+                    end
+                end
+
+                // Pulse ARP request
+                TX_ARP_REQ: begin
+                    req_ready        <= 1'b0;
+                    s_axis_tx_tready <= 1'b0;
+                    udp_tx_req       <= 1'b0;
+                    
+                    arp_delay        <= 32'ha000000;
+                    tx_state         <= TX_ARP_SEND;
+                end
+
+                // Wait until ARP is resolved
+                TX_ARP_SEND: begin
+                    req_ready        <= 1'b0;
+                    s_axis_tx_tready <= 1'b0;
+                    udp_tx_req       <= 1'b0;
+
+                    // sent
+                    if (mac_send_end)
+                        tx_state <= TX_WAIT_ARP;
+                end
+                
+                // wait for ARP response
+                TX_WAIT_ARP: begin
+                    if (arp_found) begin
+                        arp_cached <= 1'b1;
+                        tx_state <= TX_IDLE;
+                    end
+                    
+                    // timeout to not spam ARPs
+                    if (arp_delay == 32'b0) begin
+                        // re-try
+                        tx_state <= TX_ARP_REQ;
+                    end else begin
+                        // wait
+                        arp_delay = arp_delay - 32'b1;
+                    end 
+                    
+                end
+
+                // Hold udp_tx_req until udp_ram_data_req pulse arrives
+                TX_WAIT_RAM_REQ: begin
+                    req_ready        <= 1'b0;
+                    udp_tx_req       <= 1'b1;
+
+                    if (udp_ram_data_req) begin
+                        udp_tx_req       <= 1'b0;
+                        s_axis_tx_tready <= 1'b1;
+                        tx_state         <= TX_STREAM;
+                    end
+                end
+
+                // Accept AXIS bytes and write them into TX RAM
+                TX_STREAM: begin
+                    req_ready  <= 1'b0;
+                    udp_tx_req <= 1'b0;
+
+                    // keep ready high while receiving payload bytes
+                    s_axis_tx_tready <= (tx_bytes_written < tx_req_len);
+
+                    if (s_axis_tx_tvalid && s_axis_tx_tready) begin
+                        tx_ram_wr_data <= s_axis_tx_tdata;
+                        tx_ram_wr_en   <= 1'b1;
+
+                        tx_bytes_written <= tx_bytes_written + 1'b1;
+
+                        if (tx_bytes_written + 1'b1 >= tx_req_len) begin
+                            s_axis_tx_tready <= 1'b0;
+                            tx_state         <= TX_WAIT_DRAIN;
+                        end
+                    end
+                end
+
+                // Packet payload is already in RAM.
+                // Wait until TX RAM starts draining enough to allow
+                // the next request.
+                TX_WAIT_DRAIN: begin
+                    s_axis_tx_tready <= 1'b0;
+                    udp_tx_req       <= 1'b0;
+
+                    if (udp_ram_data_count <= tx_release_threshold)
+                        tx_state <= TX_IDLE;
+
+                end
+
+                default: begin
+                    tx_state         <= TX_IDLE;
+                    tx_ram_wr_en     <= 1'b0;
+                    udp_tx_req       <= 1'b0;
+                    s_axis_tx_tready <= 1'b0;
+                    req_ready        <= 1'b0;
+                end
+            endcase
+        end
+    end
+
+endmodule

rtl/ethernet-udp/src/eth/mac/arp_cache.v

@@ -0,0 +1,51 @@
+module arp_cache
+(
+ input                clk ,
+ input                rst_n ,
+ 
+ input                arp_found,
+ input  [31:0]        arp_rec_source_ip_addr,
+ input  [47:0]        arp_rec_source_mac_addr,
+ 
+ input  [31:0]        destination_ip_addr,
+ output reg [47:0]    destination_mac_addr,
+ 
+ output reg           mac_not_exist
+) ;
+       
+reg [79:0]  arp_cache ;
+
+//init arp cache
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      arp_cache  <= 80'h00_00_00_00_ff_ff_ff_ff_ff_ff ;
+    else if (arp_found)
+      arp_cache  <= {arp_rec_source_ip_addr, arp_rec_source_mac_addr} ;
+    else
+      arp_cache  <= arp_cache ;
+  end
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      destination_mac_addr  <= 48'hff_ff_ff_ff_ff_ff ;
+    else if (destination_ip_addr == arp_cache[79:48])
+      destination_mac_addr  <= arp_cache[47:0] ;
+    else
+      destination_mac_addr  <= 48'hff_ff_ff_ff_ff_ff ;
+  end
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      mac_not_exist  <= 1'b0 ;
+    else if (destination_ip_addr != arp_cache[79:48])
+      mac_not_exist  <= 1'b1 ;
+    else if (destination_ip_addr == arp_cache[79:48] && arp_cache[47:0] == 48'hff_ff_ff_ff_ff_ff)
+      mac_not_exist  <= 1'b1 ;
+    else
+      mac_not_exist  <= 1'b0 ;
+  end
+  
+endmodule

rtl/ethernet-udp/src/eth/mac/crc.v

@@ -0,0 +1,66 @@
+`timescale 1ns / 1ps
+/****************************************/
+//      　CRC32数据校验模块　　　   　　　　//
+/****************************************/
+module crc (Clk, Reset, Data_in, Enable, Crc,CrcNext);
+
+
+parameter Tp = 1;
+
+input Clk;
+input Reset;
+input [7:0] Data_in;
+input Enable;
+
+output [31:0] Crc;
+reg  [31:0] Crc;
+
+output [31:0] CrcNext;
+
+wire [7:0] Data;
+
+assign Data={Data_in[0],Data_in[1],Data_in[2],Data_in[3],Data_in[4],Data_in[5],Data_in[6],Data_in[7]};
+
+
+assign CrcNext[0] = Crc[24] ^ Crc[30] ^ Data[0] ^ Data[6];
+assign CrcNext[1] = Crc[24] ^ Crc[25] ^ Crc[30] ^ Crc[31] ^ Data[0] ^ Data[1] ^ Data[6] ^ Data[7];
+assign CrcNext[2] = Crc[24] ^ Crc[25] ^ Crc[26] ^ Crc[30] ^ Crc[31] ^ Data[0] ^ Data[1] ^ Data[2] ^ Data[6] ^ Data[7];
+assign CrcNext[3] = Crc[25] ^ Crc[26] ^ Crc[27] ^ Crc[31] ^ Data[1] ^ Data[2] ^ Data[3] ^ Data[7];
+assign CrcNext[4] = Crc[24] ^ Crc[26] ^ Crc[27] ^ Crc[28] ^ Crc[30] ^ Data[0] ^ Data[2] ^ Data[3] ^ Data[4] ^ Data[6];
+assign CrcNext[5] = Crc[24] ^ Crc[25] ^ Crc[27] ^ Crc[28] ^ Crc[29] ^ Crc[30] ^ Crc[31] ^ Data[0] ^ Data[1] ^ Data[3] ^ Data[4] ^ Data[5] ^ Data[6] ^ Data[7];
+assign CrcNext[6] = Crc[25] ^ Crc[26] ^ Crc[28] ^ Crc[29] ^ Crc[30] ^ Crc[31] ^ Data[1] ^ Data[2] ^ Data[4] ^ Data[5] ^ Data[6] ^ Data[7];
+assign CrcNext[7] = Crc[24] ^ Crc[26] ^ Crc[27] ^ Crc[29] ^ Crc[31] ^ Data[0] ^ Data[2] ^ Data[3] ^ Data[5] ^ Data[7];
+assign CrcNext[8] = Crc[0] ^ Crc[24] ^ Crc[25] ^ Crc[27] ^ Crc[28] ^ Data[0] ^ Data[1] ^ Data[3] ^ Data[4];
+assign CrcNext[9] = Crc[1] ^ Crc[25] ^ Crc[26] ^ Crc[28] ^ Crc[29] ^ Data[1] ^ Data[2] ^ Data[4] ^ Data[5];
+assign CrcNext[10] = Crc[2] ^ Crc[24] ^ Crc[26] ^ Crc[27] ^ Crc[29] ^ Data[0] ^ Data[2] ^ Data[3] ^ Data[5];
+assign CrcNext[11] = Crc[3] ^ Crc[24] ^ Crc[25] ^ Crc[27] ^ Crc[28] ^ Data[0] ^ Data[1] ^ Data[3] ^ Data[4];
+assign CrcNext[12] = Crc[4] ^ Crc[24] ^ Crc[25] ^ Crc[26] ^ Crc[28] ^ Crc[29] ^ Crc[30] ^ Data[0] ^ Data[1] ^ Data[2] ^ Data[4] ^ Data[5] ^ Data[6];
+assign CrcNext[13] = Crc[5] ^ Crc[25] ^ Crc[26] ^ Crc[27] ^ Crc[29] ^ Crc[30] ^ Crc[31] ^ Data[1] ^ Data[2] ^ Data[3] ^ Data[5] ^ Data[6] ^ Data[7];
+assign CrcNext[14] = Crc[6] ^ Crc[26] ^ Crc[27] ^ Crc[28] ^ Crc[30] ^ Crc[31] ^ Data[2] ^ Data[3] ^ Data[4] ^ Data[6] ^ Data[7];
+assign CrcNext[15] =  Crc[7] ^ Crc[27] ^ Crc[28] ^ Crc[29] ^ Crc[31] ^ Data[3] ^ Data[4] ^ Data[5] ^ Data[7];
+assign CrcNext[16] = Crc[8] ^ Crc[24] ^ Crc[28] ^ Crc[29] ^ Data[0] ^ Data[4] ^ Data[5];
+assign CrcNext[17] = Crc[9] ^ Crc[25] ^ Crc[29] ^ Crc[30] ^ Data[1] ^ Data[5] ^ Data[6];
+assign CrcNext[18] = Crc[10] ^ Crc[26] ^ Crc[30] ^ Crc[31] ^ Data[2] ^ Data[6] ^ Data[7];
+assign CrcNext[19] = Crc[11] ^ Crc[27] ^ Crc[31] ^ Data[3] ^ Data[7];
+assign CrcNext[20] = Crc[12] ^ Crc[28] ^ Data[4];
+assign CrcNext[21] = Crc[13] ^ Crc[29] ^ Data[5];
+assign CrcNext[22] = Crc[14] ^ Crc[24] ^ Data[0];
+assign CrcNext[23] = Crc[15] ^ Crc[24] ^ Crc[25] ^ Crc[30] ^ Data[0] ^ Data[1] ^ Data[6];
+assign CrcNext[24] = Crc[16] ^ Crc[25] ^ Crc[26] ^ Crc[31] ^ Data[1] ^ Data[2] ^ Data[7];
+assign CrcNext[25] = Crc[17] ^ Crc[26] ^ Crc[27] ^ Data[2] ^ Data[3];
+assign CrcNext[26] = Crc[18] ^ Crc[24] ^ Crc[27] ^ Crc[28] ^ Crc[30] ^ Data[0] ^ Data[3] ^ Data[4] ^ Data[6];
+assign CrcNext[27] = Crc[19] ^ Crc[25] ^ Crc[28] ^ Crc[29] ^ Crc[31] ^ Data[1] ^ Data[4] ^ Data[5] ^ Data[7];
+assign CrcNext[28] = Crc[20] ^ Crc[26] ^ Crc[29] ^ Crc[30] ^ Data[2] ^ Data[5] ^ Data[6];
+assign CrcNext[29] = Crc[21] ^ Crc[27] ^ Crc[30] ^ Crc[31] ^ Data[3] ^ Data[6] ^ Data[7];
+assign CrcNext[30] = Crc[22] ^ Crc[28] ^ Crc[31] ^ Data[4] ^ Data[7];
+assign CrcNext[31] = Crc[23] ^ Crc[29] ^ Data[5];
+
+always @ (posedge Clk, posedge Reset)
+ begin
+  if (Reset) begin
+    Crc <={32{1'b1}};
+  end
+   else if (Enable)
+    Crc <=CrcNext;
+ end
+endmodule

rtl/ethernet-udp/src/eth/mac/icmp_reply.v

@@ -0,0 +1,558 @@
+//////////////////////////////////////////////////////////////////////////////////////
+//Module Name : icmp_reply
+//Description : This module is used to receive icmp and reply
+//
+
+module icmp_reply
+(
+   input                  clk,
+   input                  rst_n,
+   
+   input                  mac_send_end,
+   input                  ip_tx_ack,
+   input  [7:0]           icmp_rx_data,             //received data
+   input                  icmp_rx_req,              //receive request
+   input                  icmp_rev_error,           //receive error from MAC or IP
+   input  [15:0]          upper_layer_data_length,    //data length received from IP layer
+   
+   input                  icmp_data_req,            //IP layer request data
+   output reg             icmp_tx_ready,            //icmp reply data ready
+   output reg [7:0]       icmp_tx_data,             //icmp reply data
+   output                 icmp_tx_end,              //icmp reply end
+   output reg             icmp_tx_req               //icmp reply request
+ 
+);
+       
+localparam ECHO_REQUEST = 8'h08 ;
+localparam ECHO_REPLY   = 8'h00 ;
+
+reg  [15:0]             icmp_rx_cnt ;
+
+reg                     icmp_rx_end ;
+reg                     icmp_checksum_error ;     //icmp receive checksum error
+reg                     icmp_type_error ;         //if icmp type is not 8'h08, do not reply
+reg  [15:0]             icmp_data_length ;        //data length register
+reg  [15:0]             icmp_data_length_d0 ;
+reg  [10:0]             icmp_rec_ram_read_addr ;  //icmp ram read address
+wire [7:0]              icmp_rec_ram_rdata ;      //icmp ram read data
+reg  [7:0]              icmp_code  ;              //icmp code
+reg  [15:0]             icmp_id  ;                //icmp id
+reg  [15:0]             icmp_seq ;                //icmp seq
+reg                     checksum_finish ;         //icmp reply checksum generated finish
+
+reg [10:0]              ram_write_addr ;          //icmp ram write address, when receive icmp, write ram
+reg                     ram_wr_en ;               //icmp ram write enable
+reg                     icmp_rev_error_d0 ;
+
+reg  [15:0]             timeout ;                 //timeout counter
+reg  [7:0]              icmp_rx_data_d0 ;         //register for receive data
+
+reg                     mac_send_end_d0 ;
+
+//receive and reply FSM
+parameter IDLE             =  12'b00000_0000_001  ;
+parameter REC_DATA         =  12'b00000_0000_010  ;
+parameter REC_ODD_DATA     =  12'b00000_0000_100  ;
+parameter VERIFY_CHECKSUM  =  12'b00000_0001_000  ;
+parameter REC_ERROR        =  12'b00000_0010_000  ;
+parameter REC_END_WAIT     =  12'b00000_0100_000  ;
+parameter GEN_CHECKSUM     =  12'b00000_1000_000  ;
+parameter SEND_WAIT_0      =  12'b00001_0000_000  ;
+parameter SEND_WAIT_1      =  12'b00010_0000_000  ;
+parameter SEND             =  12'b00100_0000_000  ;
+parameter REC_END          =  12'b01000_0000_000  ;
+parameter SEND_END         =  12'b10000_0000_000  ;
+
+
+
+reg [11:0]     state      ;
+reg [11:0]     next_state ;
+
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      state <= IDLE ;
+    else
+      state <= next_state ;
+  end
+  
+always @(*)
+  begin
+    case(state)
+      IDLE            :
+        begin
+          if (icmp_rx_req == 1'b1)
+            next_state <= REC_DATA ;
+          else
+            next_state <= IDLE ;
+        end
+      REC_DATA       :
+        begin
+          if (icmp_rev_error_d0 || icmp_type_error)
+            next_state <= REC_ERROR ;
+          else if (icmp_data_length[0] == 1'b0 && icmp_rx_cnt == icmp_data_length - 1)
+            next_state <= VERIFY_CHECKSUM ;
+          else if (icmp_data_length[0] == 1'b1 && icmp_rx_cnt == icmp_data_length - 2)
+            next_state <= REC_ODD_DATA ;
+          else if (icmp_rx_cnt == 16'hffff)
+            next_state <= IDLE ;
+          else
+            next_state <= REC_DATA ;
+        end
+      REC_ODD_DATA   :
+        begin
+          if (icmp_rev_error_d0 || icmp_type_error)
+            next_state <= REC_ERROR ;
+          else if (icmp_rx_cnt == icmp_data_length - 1)
+            next_state <= VERIFY_CHECKSUM ;
+          else
+            next_state <= REC_ODD_DATA ;
+        end
+      VERIFY_CHECKSUM:
+        begin
+          if (icmp_checksum_error)
+            next_state <= REC_ERROR ;
+          else if (icmp_rx_end && checksum_finish)
+            next_state <= REC_END_WAIT ;
+          else if (icmp_rx_cnt == 16'hffff)
+            next_state <= IDLE ;
+          else
+            next_state <= VERIFY_CHECKSUM ;
+        end
+      REC_ERROR      :
+        next_state <= IDLE  ;
+      REC_END_WAIT   :
+        begin
+          if (icmp_rx_cnt == 16'd63)
+            next_state <= REC_END ;
+          else
+            next_state <= REC_END_WAIT ;
+        end
+	  SEND_WAIT_0      :
+        begin
+          if (ip_tx_ack)
+            next_state <= SEND_WAIT_1 ;
+          else
+            next_state <= SEND_WAIT_0 ;
+        end
+      SEND_WAIT_1      :
+        begin
+          if (icmp_data_req)
+            next_state <= SEND ;
+          else if (timeout == 16'hffff)
+            next_state <= IDLE ;
+          else
+            next_state <= SEND_WAIT_1 ;
+        end
+      SEND           :
+        begin
+          if (icmp_rx_cnt == icmp_data_length)
+            next_state <= SEND_END ;
+          else if (icmp_rx_cnt == 16'hffff)
+            next_state <= IDLE ;
+          else
+            next_state <= SEND ;
+        end
+      REC_END        :
+        next_state <= SEND_WAIT_0  ;
+      SEND_END       :
+	    begin
+		  if (mac_send_end_d0)
+		    next_state <= IDLE  ;
+		  else
+		    next_state <= SEND_END  ;
+	    end        
+      default        :
+        next_state <= IDLE  ;
+    endcase
+  end
+  
+  
+ always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      mac_send_end_d0 <= 1'b0 ;
+    else 
+      mac_send_end_d0 <= mac_send_end ;
+  end   
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      icmp_tx_req <=  1'b0 ;
+	else if (state == SEND_WAIT_1)
+	  icmp_tx_req <=  1'b0 ;
+    else if (state == REC_END)
+      icmp_tx_req <=  1'b1 ;
+  end
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      icmp_tx_ready <=  1'b0 ;
+    else if (state == SEND_WAIT_1)
+      icmp_tx_ready <=  1'b1 ;
+    else
+      icmp_tx_ready <=  1'b0 ;
+  end
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      ram_wr_en <=  1'b0 ;
+    else if (state == REC_DATA  || state == REC_ODD_DATA)
+      begin
+        if (icmp_rx_cnt < icmp_data_length && icmp_rx_cnt > 16'd7)
+          ram_wr_en <=  1'b1 ;
+        else
+          ram_wr_en <=  1'b0 ;
+      end
+    else
+      ram_wr_en <=  1'b0 ;
+  end
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      ram_write_addr <=  11'b0 ;
+    else if (state == REC_DATA  || state == REC_ODD_DATA)
+      ram_write_addr <=  icmp_rx_cnt - 8 ;
+    else
+      ram_write_addr <=  11'b0 ;
+  end
+  
+//timeout counter
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      timeout <= 16'd0 ;
+    else if (state == SEND_WAIT_1)
+      timeout <= timeout + 1'b1 ;
+    else
+      timeout <= 16'd0 ;
+  end
+//received data register
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      icmp_rx_data_d0 <= 8'd0 ;
+    else
+      icmp_rx_data_d0 <= icmp_rx_data ;
+  end
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      icmp_rev_error_d0 <= 1'b0 ;
+    else
+      icmp_rev_error_d0 <= icmp_rev_error ;
+  end
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      icmp_data_length <= 16'd0 ;
+    else if (state == IDLE)
+      icmp_data_length <= upper_layer_data_length ;
+  end
+  
+  
+//icmp receive and reply counter
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      icmp_rx_cnt <= 16'd0 ;
+    else if (state == REC_DATA  || state == REC_END_WAIT ||  state == SEND)
+      icmp_rx_cnt <= icmp_rx_cnt + 1'b1 ;
+    else
+      icmp_rx_cnt <= 16'd0 ;
+  end
+  
+  
+//icmp type is not request
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      icmp_type_error <= 1'b0 ;
+    else if (state == REC_DATA && icmp_rx_cnt == 16'd0 && icmp_rx_data != ECHO_REQUEST)
+      icmp_type_error <= 1'b1 ;
+    else
+      icmp_type_error <= 1'b0 ;
+  end
+  
+//icmp code
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      icmp_code <= 8'd0 ;
+    else if (state == REC_DATA && icmp_rx_cnt == 16'd1)
+      icmp_code <= icmp_rx_data ;
+  end
+  
+//icmp id
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      icmp_id <= 16'd0 ;
+    else if (state == REC_DATA && icmp_rx_cnt == 16'd4)
+      icmp_id[15:8] <= icmp_rx_data ;
+    else if (state == REC_DATA && icmp_rx_cnt == 16'd5)
+      icmp_id[7:0] <= icmp_rx_data ;
+  end
+  
+//icmp seq
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      icmp_seq <= 16'd0 ;
+    else if (state == REC_DATA && icmp_rx_cnt == 16'd6)
+      icmp_seq[15:8] <= icmp_rx_data ;
+    else if (state == REC_DATA && icmp_rx_cnt == 16'd7)
+      icmp_seq[7:0] <= icmp_rx_data ;
+  end
+  
+  
+//read ram address when reply
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      icmp_rec_ram_read_addr <= 11'd0 ;
+    else if (state == SEND && icmp_rx_cnt > 5)
+      icmp_rec_ram_read_addr <= icmp_rx_cnt - 6 ;
+    else
+      icmp_rec_ram_read_addr <= 11'd0 ;
+  end
+//received ram: depth 256 width 8
+icmp_rx_ram_8_256 icmp_receive_ram
+(		
+    .clka(clk),    // input wire clka
+    .wea(ram_wr_en),      // input wire [0 : 0] wea
+    .addra(ram_write_addr),  // input wire [7 : 0] addra
+    .dina(icmp_rx_data_d0),    // input wire [7 : 0] dina
+    .clkb(clk),    // input wire clkb
+    .addrb(icmp_rec_ram_read_addr),  // input wire [7 : 0] addrb
+    .doutb(icmp_rec_ram_rdata)  // output wire [7 : 0] doutb
+	); 
+
+  
+//***************************************************************************//
+//verify checksum 32 bit adder, in the end, add itself until high 16 bit is 0
+//** ************************************************************************//
+reg  [31:0] checksum_tmp ;
+reg  [31:0] checksum_buf ;
+reg  [31:0] check_out ;
+reg  [31:0] checkout_buf ;
+wire [15:0] checksum ;
+reg  [2:0]  checksum_cnt ;
+
+//checksum function
+function [31:0] checksum_adder
+  (
+    input [31:0]  dataina,
+    input [31:0]  datainb
+  );
+  begin
+    checksum_adder = dataina + datainb;
+  end
+endfunction
+
+function [31:0]  checksum_out
+  (
+    input [31:0]  dataina
+  );
+  begin
+    checksum_out = dataina[15:0]+dataina[31:16];
+  end
+endfunction
+
+always @(posedge clk or negedge rst_n)
+  begin
+    if(rst_n == 1'b0)
+      checksum_tmp <= 32'd0;
+    else if (state == REC_DATA)
+      begin
+        if(icmp_rx_cnt[0] == 1'b1)
+          checksum_tmp <= checksum_adder({icmp_rx_data_d0,icmp_rx_data},checksum_buf);
+      end
+    else if (state == REC_ODD_DATA)
+      checksum_tmp <= checksum_adder({icmp_rx_data,8'h00},checksum_tmp);   //if udp data length is odd, fill with one byte 8'h00
+    else if (state == IDLE)
+      checksum_tmp <= 32'd0;
+  end
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if(rst_n == 1'b0)
+      checksum_cnt <= 3'd0 ;
+    else if (state ==  VERIFY_CHECKSUM)
+      checksum_cnt <= checksum_cnt + 1'b1 ;
+    else
+      checksum_cnt <= 3'd0 ;
+  end
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if(rst_n == 1'b0)
+      check_out <= 32'd0;
+    else if (state ==  VERIFY_CHECKSUM)
+      begin
+        if (checksum_cnt == 3'd0)
+          check_out <= checksum_out(checksum_tmp) ;
+        else if (checksum_cnt == 3'd1)
+          check_out <= checksum_out(check_out) ;
+      end
+  end
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      checksum_buf <= 32'd0 ;
+    else if (state == REC_DATA)
+      checksum_buf <= checksum_tmp ;
+    else
+      checksum_buf <= 32'd0 ;
+  end
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      checkout_buf <= 32'd0 ;
+    else
+      checkout_buf <= check_out ;
+  end
+  
+assign checksum = ~checkout_buf[15:0] ;
+
+//generate checksum error signal and rx end signal
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      begin
+        icmp_checksum_error <= 1'b0 ;
+        icmp_rx_end <= 1'b0 ;
+      end
+    else if (state == VERIFY_CHECKSUM && checksum_cnt == 3'd3)
+      begin
+        if (checksum == 16'd0)
+          begin
+            icmp_checksum_error <= 1'b0 ;
+            icmp_rx_end <= 1'b1 ;
+          end
+        else
+          begin
+            icmp_checksum_error <= 1'b1 ;
+            icmp_rx_end <= 1'b0 ;
+          end
+      end
+    else
+      begin
+        icmp_checksum_error <= 1'b0 ;
+        icmp_rx_end <= 1'b0 ;
+      end
+  end
+  
+  
+  
+//*******************************************************************//
+//reply checksum
+//*******************************************************************//
+reg  [31:0] reply_checksum_tmp ;
+reg  [31:0] reply_checksum_buf ;
+reg  [31:0] reply_check_out ;
+reg  [31:0] reply_checkout_buf ;
+wire [15:0] reply_checksum ;
+
+
+always @(posedge clk or negedge rst_n)
+  begin
+    if(rst_n == 1'b0)
+      reply_checksum_tmp <= 32'd0;
+    else if (state == REC_DATA)
+      begin
+        if (icmp_rx_cnt == 16'd1)
+          reply_checksum_tmp <= checksum_adder({8'h00,icmp_rx_data}, 16'h0000);  //source ip address
+        else if (icmp_rx_cnt == 16'd3)
+          reply_checksum_tmp <= reply_checksum_tmp ;  //source ip address
+        else
+          begin
+            if(icmp_rx_cnt[0] == 1'b1)
+              reply_checksum_tmp <= checksum_adder({icmp_rx_data_d0,icmp_rx_data},reply_checksum_buf);
+          end
+      end
+    else if (state == REC_ODD_DATA)
+      reply_checksum_tmp <= checksum_adder({icmp_rx_data,8'h00},reply_checksum_tmp);   //if udp data length is odd, fill with one byte 8'h00
+    else if (state == IDLE)
+      reply_checksum_tmp <= 32'd0;
+  end
+  
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if(rst_n == 1'b0)
+      reply_check_out <= 32'd0;
+    else if (state ==  VERIFY_CHECKSUM)
+      begin
+        if (checksum_cnt == 3'd0)
+          reply_check_out <= checksum_out(reply_checksum_tmp) ;
+        else if (checksum_cnt == 3'd1)
+          reply_check_out <= checksum_out(reply_check_out) ;
+      end
+  end
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      reply_checksum_buf <= 32'd0 ;
+    else if (state == REC_DATA)
+      reply_checksum_buf <= reply_checksum_tmp ;
+    else
+      reply_checksum_buf <= 32'd0 ;
+  end
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      reply_checkout_buf <= 32'd0 ;
+    else if (state == VERIFY_CHECKSUM)
+      reply_checkout_buf <= reply_check_out ;
+  end
+  
+assign reply_checksum = ~reply_checkout_buf[15:0] ;
+
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      checksum_finish <= 1'b0 ;
+    else if (state == VERIFY_CHECKSUM && checksum_cnt == 3'd3)
+      checksum_finish <= 1'b1 ;
+    else
+      checksum_finish <= 1'b0 ;
+  end
+  
+  
+//*****************************************************************************************//
+//send icmp data
+//*****************************************************************************************//
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      icmp_tx_data <= 8'h00  ;
+    else if (state == SEND)
+      begin
+        case(icmp_rx_cnt)
+          16'd0    :   icmp_tx_data <= ECHO_REPLY ;
+          16'd1    :   icmp_tx_data <= icmp_code ;
+          16'd2    :   icmp_tx_data <= reply_checksum[15:8];
+          16'd3    :   icmp_tx_data <= reply_checksum[7:0] ;
+          16'd4    :   icmp_tx_data <= icmp_id[15:8] ;
+          16'd5    :   icmp_tx_data <= icmp_id[7:0] ;
+          16'd6    :   icmp_tx_data <= icmp_seq[15:8] ;
+          16'd7    :   icmp_tx_data <= icmp_seq[7:0] ;
+          default  :   icmp_tx_data <= icmp_rec_ram_rdata ;
+        endcase
+      end
+    else
+      icmp_tx_data <= 8'h00 ;
+  end
+  
+endmodule

rtl/ethernet-udp/src/eth/mac/mac_test.v

@@ -0,0 +1,435 @@
+
+//////////////////////////////////////////////////////////////////////////////////////
+//Module Name : mac_top
+//Description :
+//
+//////////////////////////////////////////////////////////////////////////////////////
+`define TEST_SPEED
+`timescale 1 ns/1 ns
+module mac_test
+(
+ input                rst_n  ,  
+ input [31:0]         pack_total_len,     
+ input                gmii_tx_clk ,
+ input                gmii_rx_clk ,
+ input                gmii_rx_dv,
+ input  [7:0]         gmii_rxd,
+ output reg           gmii_tx_en,
+ output reg [7:0]     gmii_txd 
+);
+
+localparam UDP_WIDTH = 32 ;
+localparam UDP_DEPTH = 5 ;
+
+
+reg                  gmii_rx_dv_d0 ;
+reg   [7:0]          gmii_rxd_d0 ;
+wire                 gmii_tx_en_tmp ;
+wire   [7:0]         gmii_txd_tmp ;
+
+reg   [7:0]          ram_wr_data ;
+reg                  ram_wr_en ;
+wire                 udp_ram_data_req ;
+reg   [15:0]         udp_send_data_length ;
+
+wire  [7:0]          tx_ram_wr_data ;
+wire                 tx_ram_wr_en ;
+wire                 udp_tx_req ;
+wire                 arp_request_req ;
+wire                 mac_send_end ;
+reg                  write_end ;
+
+wire [7:0]           udp_rec_ram_rdata ;
+reg  [10:0]          udp_rec_ram_read_addr ;
+wire [15:0]          udp_rec_data_length ;
+wire                 udp_rec_data_valid ;
+
+wire                 udp_tx_end  ;
+wire                 almost_full ;
+
+reg                  udp_ram_wr_en ;
+reg                  udp_write_end ;
+wire                 write_ram_end ;
+reg  [31:0]          wait_cnt ;
+reg  [UDP_WIDTH-1:0]  udp_data [UDP_DEPTH-1:0];
+
+reg  [4:0] i;
+reg  [1:0] j ;
+
+reg  write_sel ;
+
+wire button_negedge ;
+
+wire mac_not_exist ;
+wire arp_found ;
+
+parameter IDLE          = 9'b000_000_001 ;
+parameter ARP_REQ       = 9'b000_000_010 ;
+parameter ARP_SEND      = 9'b000_000_100 ;
+parameter ARP_WAIT      = 9'b000_001_000 ;
+parameter GEN_REQ       = 9'b000_010_000 ;
+parameter WRITE_RAM     = 9'b000_100_000 ;
+parameter SEND          = 9'b001_000_000 ;
+parameter WAIT          = 9'b010_000_000 ;
+parameter CHECK_ARP     = 9'b100_000_000 ;
+
+
+(* MARK_DEBUG="true" *)  reg [8:0]    state  ;
+reg [8:0]    next_state ;
+reg  [15:0]  ram_cnt ;
+reg    almost_full_d0 ;
+reg    almost_full_d1 ;
+always @(posedge gmii_tx_clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      state  <=  IDLE  ;
+    else
+      state  <= next_state ;
+  end
+  
+always @(*)
+  begin
+    case(state)
+      IDLE        :
+        begin
+        if (wait_cnt == pack_total_len)    
+            next_state <= ARP_REQ ;
+          else
+            next_state <= IDLE ;
+        end
+
+      ARP_REQ     :
+        next_state <= ARP_SEND ;
+      ARP_SEND    :
+        begin
+          if (mac_send_end)
+            next_state <= ARP_WAIT ;
+          else
+            next_state <= ARP_SEND ;
+        end
+      ARP_WAIT    :
+        begin
+          if (arp_found)
+            next_state <= WAIT ;
+          else if (wait_cnt == pack_total_len)
+            next_state <= ARP_REQ ;
+          else
+            next_state <= ARP_WAIT ;
+        end
+      GEN_REQ     :
+        begin
+          if (udp_ram_data_req)
+            next_state <= WRITE_RAM ;
+          else
+            next_state <= GEN_REQ ;
+        end
+      WRITE_RAM   :
+        begin
+		  `ifdef TEST_SPEED
+		  if (ram_cnt == udp_send_data_length - 1)
+		  `else
+          if (write_ram_end) 
+		  `endif
+            next_state <= WAIT     ;
+          else
+            next_state <= WRITE_RAM ;
+        end
+        
+      SEND        :
+        begin
+          if (udp_tx_end)
+            next_state <= WAIT ;
+          else
+            next_state <= SEND ;
+        end
+        
+      WAIT        :
+        begin
+		  `ifdef TEST_SPEED  
+          if (wait_cnt == 32'd90)             //frame gap
+		  `else
+		  if (wait_cnt == pack_total_len)
+		  `endif
+            next_state <= CHECK_ARP ;
+          else
+            next_state <= WAIT ;
+        end
+      CHECK_ARP   :
+        begin
+          if (mac_not_exist)
+            next_state <= ARP_REQ ;
+          else if (almost_full_d1)
+            next_state <= CHECK_ARP ;
+          else
+            next_state <= GEN_REQ ;
+        end
+      default     :
+        next_state <= IDLE ;
+    endcase
+  end
+  
+  
+assign write_ram_end        = (write_sel)? udp_write_end : write_end ;
+assign tx_ram_wr_data       = (write_sel)? udp_rec_ram_rdata : ram_wr_data ;
+assign tx_ram_wr_en         = (write_sel)? udp_ram_wr_en : ram_wr_en ;
+
+
+always@(posedge gmii_rx_clk or negedge rst_n)
+  begin
+    if(rst_n == 1'b0)
+      begin
+        gmii_rx_dv_d0 <= 1'b0 ;
+        gmii_rxd_d0   <= 8'd0 ;
+      end
+    else
+      begin
+        gmii_rx_dv_d0 <= gmii_rx_dv ;
+        gmii_rxd_d0   <= gmii_rxd ;
+      end
+  end
+  
+always@(posedge gmii_tx_clk or negedge rst_n)
+  begin
+    if(rst_n == 1'b0)
+      begin
+        gmii_tx_en <= 1'b0 ;
+        gmii_txd   <= 8'd0 ;
+      end
+    else
+      begin
+        gmii_tx_en <= gmii_tx_en_tmp ;
+        gmii_txd   <= gmii_txd_tmp ;
+      end
+  end
+
+
+
+  
+mac_top mac_top0
+(
+ .gmii_tx_clk                 (gmii_tx_clk)                  ,
+ .gmii_rx_clk                 (gmii_rx_clk)                  ,
+ .rst_n                       (rst_n)  ,
+ 
+ .source_mac_addr             (48'h00_0a_35_01_fe_c0)   ,       //source mac address
+ .TTL                         (8'h80),
+ .source_ip_addr              (32'hc0a80002),
+ .destination_ip_addr         (32'hc0a80003),
+ .udp_send_source_port        (16'h1f90),
+ .udp_send_destination_port   (16'h1f90),
+ 
+ .ram_wr_data                 (tx_ram_wr_data) ,
+ .ram_wr_en                   (tx_ram_wr_en),
+ .udp_ram_data_req            (udp_ram_data_req),
+ .udp_send_data_length        (udp_send_data_length),
+ .udp_tx_end                  (udp_tx_end                 ),
+ .almost_full                 (almost_full                ), 
+ 
+ .udp_tx_req                  (udp_tx_req),
+ .arp_request_req             (arp_request_req ),
+ 
+ .mac_send_end                (mac_send_end),
+ .mac_data_valid              (gmii_tx_en_tmp),
+ .mac_tx_data                 (gmii_txd_tmp),
+ .rx_dv                       (gmii_rx_dv_d0   ),
+ .mac_rx_datain               (gmii_rxd_d0 ),
+ 
+ .udp_rec_ram_rdata           (udp_rec_ram_rdata),
+ .udp_rec_ram_read_addr       (udp_rec_ram_read_addr),
+ .udp_rec_data_length         (udp_rec_data_length ),
+ 
+ .udp_rec_data_valid          (udp_rec_data_valid),
+ .arp_found                   (arp_found ),
+ .mac_not_exist               (mac_not_exist )
+) ;
+                       
+always @(*)
+  begin
+    udp_data[0] <={"H","E","L","L"};
+    udp_data[1] <={"O"," ","A","L"};
+    udp_data[2] <={"I","N","X"," "};
+    udp_data[3] <={"H","E","I","J"};
+    udp_data[4] <={"I","N","\r","\n"};
+    
+  end
+  
+//reg    almost_full_d0 ;
+//reg    almost_full_d1 ;
+  
+always@(posedge gmii_rx_clk or negedge rst_n)
+  begin
+    if(rst_n == 1'b0)
+      begin
+        almost_full_d0   <= 1'b0 ;
+        almost_full_d1   <= 1'b0 ;
+      end
+    else
+      begin
+        almost_full_d0   <= almost_full ;
+        almost_full_d1   <= almost_full_d0 ;
+      end
+  end
+
+always@(posedge gmii_rx_clk or negedge rst_n)
+  begin
+    if(rst_n == 1'b0)
+	   udp_send_data_length <= 16'd0 ;
+    else if (write_sel)	 
+		udp_send_data_length <= udp_rec_data_length - 8  ;
+	 else
+	 `ifdef TEST_SPEED 
+       udp_send_data_length <= 16'd100 ;	 
+	 `else	 
+	   udp_send_data_length <= 4*UDP_DEPTH ;
+	 `endif
+  end
+  
+  
+always@(posedge gmii_tx_clk or negedge rst_n)
+  begin
+    if(rst_n == 1'b0)
+      write_sel <= 1'b0 ;
+    else if (state == WAIT)
+      begin
+        if (udp_rec_data_valid)
+          write_sel <= 1'b1 ;
+        else
+          write_sel <= 1'b0 ;
+      end
+  end
+  
+assign udp_tx_req    = (state == GEN_REQ) ;
+assign arp_request_req  = (state == ARP_REQ) ;
+
+always@(posedge gmii_tx_clk or negedge rst_n)
+  begin
+    if(rst_n == 1'b0)
+      wait_cnt <= 0 ;
+    else if ((state==IDLE||state == WAIT || state == ARP_WAIT) && state != next_state)
+      wait_cnt <= 0 ;
+    else if (state==IDLE||state == WAIT || state == ARP_WAIT)
+      wait_cnt <= wait_cnt + 1'b1 ;
+	 else
+	   wait_cnt <= 0 ;
+  end
+  
+
+`ifdef TEST_SPEED
+/*************************************************************/
+//Test ethernet speed
+//reg  [15:0]     ram_cnt ;
+always@(posedge gmii_tx_clk or negedge rst_n)
+ begin
+   if(rst_n == 1'b0)
+     ram_cnt <= 11'd0 ;
+   else if (state == WRITE_RAM)
+     ram_cnt <= ram_cnt + 1'b1 ;
+   else
+     ram_cnt <= 11'd0 ;
+ end
+
+always@(posedge gmii_tx_clk or negedge rst_n)
+ begin
+   if(rst_n == 1'b0)
+     ram_wr_en <= 1'b0 ;
+   else if (state == WRITE_RAM)
+     ram_wr_en <= 1'b1 ;
+   else
+     ram_wr_en <= 1'b0 ;
+ end  
+ 
+
+always@(posedge gmii_tx_clk or negedge rst_n)
+ begin
+   if(rst_n == 1'b0)
+     ram_wr_data <= 8'd0 ;
+   else if (state == WRITE_RAM)
+     ram_wr_data <= ram_cnt[7:0] ;
+   else
+     ram_wr_data <= 8'd0 ;
+ end  
+/*************************************************************/
+`else
+always@(posedge gmii_tx_clk or negedge rst_n)
+  begin
+    if(rst_n == 1'b0)
+      begin
+        write_end  <= 1'b0;
+        ram_wr_data <= 0;
+        ram_wr_en  <= 0 ;
+        i <= 0 ;
+        j <= 0 ;
+      end
+    else if (state == WRITE_RAM)
+      begin
+        if(i == 5)
+          begin
+            ram_wr_en <=1'b0;
+            write_end <= 1'b1;
+          end
+        else
+          begin
+            ram_wr_en <= 1'b1 ;
+            write_end <= 1'b0 ;
+            j <= j + 1'b1 ;
+            case(j)
+              2'd0    :  ram_wr_data <= udp_data[i][31:24] ;
+              2'd1    :  ram_wr_data <= udp_data[i][23:16] ;
+              2'd2    :  ram_wr_data <= udp_data[i][15:8] ;
+              2'd3    :  ram_wr_data <= udp_data[i][7:0] ;
+              default :  ram_wr_data <= 8'h00 ;
+            endcase
+            
+            if (j == 3)
+              begin
+                j <= 0 ;
+                i <= i + 1'b1;
+              end
+          end
+      end
+    else
+      begin
+        write_end  <= 1'b0;
+        ram_wr_data <= 0;
+        ram_wr_en  <= 0 ;
+        i <= 0 ;
+        j <= 0 ;
+      end
+  end
+`endif
+  
+//send udp received data to udp tx ram
+always@(posedge gmii_tx_clk or negedge rst_n)
+  begin
+    if(rst_n == 1'b0)
+      udp_rec_ram_read_addr <= 11'd0 ;
+    else if (state == WRITE_RAM)
+      udp_rec_ram_read_addr <= udp_rec_ram_read_addr + 1'b1 ;
+    else
+      udp_rec_ram_read_addr <= 11'd0 ;
+  end
+  
+always@(posedge gmii_tx_clk or negedge rst_n)
+  begin
+    if(rst_n == 1'b0)
+      udp_ram_wr_en <= 1'b0 ;
+    else if (state == WRITE_RAM && udp_rec_ram_read_addr < udp_rec_data_length - 8)
+      udp_ram_wr_en <= 1'b1 ;
+    else
+      udp_ram_wr_en <= 1'b0 ;
+  end
+  
+always@(posedge gmii_tx_clk or negedge rst_n)
+  begin
+    if(rst_n == 1'b0)
+      udp_write_end <= 1'b0 ;
+    else if (state == WRITE_RAM && udp_rec_ram_read_addr == udp_rec_data_length - 8)
+      udp_write_end <= 1'b1 ;
+    else
+      udp_write_end <= 1'b0 ;
+  end
+  
+  
+endmodule
+
+

rtl/ethernet-udp/src/eth/mac/mac_top.v

@@ -0,0 +1,176 @@
+// Top module for base ethernet operations
+// inheireted from Alinx
+
+`timescale 1 ns/1 ns
+module mac_top
+       (
+         input                gmii_tx_clk  ,
+         input                gmii_rx_clk  ,
+         input                rst_n     ,
+         
+         input  [47:0]        source_mac_addr ,       //source mac address
+         input  [7:0]         TTL,
+         input  [31:0]        source_ip_addr,
+         input  [31:0]        destination_ip_addr,
+         input  [15:0]        udp_send_source_port,
+         input  [15:0]        udp_send_destination_port,
+         
+         
+         input  [7:0]         ram_wr_data,
+         input                ram_wr_en,
+         output               udp_ram_data_req,
+         input  [15:0]        udp_send_data_length,
+         output               udp_tx_end,
+         output               almost_full,
+         
+         input                udp_tx_req,
+         input                arp_request_req,
+         output               mac_data_valid,
+         output               mac_send_end,
+         output [7:0]         mac_tx_data,
+         
+         input                rx_dv,
+         input  [7:0]         mac_rx_datain,
+         output [7:0]         udp_rec_ram_rdata ,
+         input  [10:0]        udp_rec_ram_read_addr,
+         output [15:0]        udp_rec_data_length,
+         output               udp_rec_data_valid,
+         output [11:0]        udp_ram_data_count,
+         
+         output               arp_found,
+         output               mac_not_exist
+         
+       ) ;
+       
+       
+wire                  arp_reply_ack ;
+wire                  arp_reply_req ;
+wire  [31:0]          arp_rec_source_ip_addr ;
+wire  [47:0]          arp_rec_source_mac_addr ;
+wire   [47:0]         destination_mac_addr ;
+
+wire [7:0]            mac_rx_dataout ;
+wire [15:0]           upper_layer_data_length ;
+wire                  icmp_rx_req ;
+wire                  icmp_rev_error ;
+wire                  upper_data_req ;
+wire                  icmp_tx_ready ;
+wire  [7:0]           icmp_tx_data ;
+wire                  icmp_tx_end ;
+wire                  icmp_tx_req ;
+wire                  icmp_tx_ack ;
+wire [15:0]           icmp_send_data_length ;
+
+mac_tx_top mac_tx0
+           (
+            .clk                         (gmii_tx_clk)                  ,
+            .rst_n                       (rst_n)  ,
+            
+            .destination_mac_addr        (destination_mac_addr)   , //destination mac address
+            .source_mac_addr             (source_mac_addr)   ,       //source mac address
+            .TTL                         (TTL),
+            .source_ip_addr              (source_ip_addr),
+            .destination_ip_addr         (destination_ip_addr),
+            
+            .udp_send_source_port        (udp_send_source_port),
+            .udp_send_destination_port   (udp_send_destination_port),
+            
+            .arp_reply_ack               (arp_reply_ack ),
+            .arp_reply_req               (arp_reply_req ),
+            .arp_rec_source_ip_addr      (arp_rec_source_ip_addr ),
+            .arp_rec_source_mac_addr     (arp_rec_source_mac_addr ),
+            .arp_request_req             (arp_request_req ),
+            .udp_ram_data_count          (udp_ram_data_count ),
+            
+            
+            .ram_wr_data                 (ram_wr_data) ,
+            .ram_wr_en                   (ram_wr_en),
+            .udp_tx_req                  (udp_tx_req),
+            .udp_send_data_length        (udp_send_data_length       ),
+            .udp_ram_data_req            (udp_ram_data_req           ),
+            .udp_tx_end                  (udp_tx_end                 ),
+            .almost_full                 (almost_full                ),  
+            
+            .upper_data_req              (upper_data_req ),
+            .icmp_tx_ready               (icmp_tx_ready ),
+            .icmp_tx_data                (icmp_tx_data  ),
+            .icmp_tx_end                 (icmp_tx_end  ),
+            .icmp_tx_req                 (icmp_tx_req  ),
+            .icmp_tx_ack                 (icmp_tx_ack  ),
+            .icmp_send_data_length       (icmp_send_data_length),
+            
+            .mac_data_valid              (mac_data_valid),
+            .mac_send_end                (mac_send_end),
+            .mac_tx_data                 (mac_tx_data)
+           ) ;
+           
+           
+           
+           
+           
+           
+mac_rx_top mac_rx0
+           (
+            .clk                      (gmii_rx_clk)                  ,
+            .rst_n                    (rst_n)  ,
+            
+            .rx_dv                    (rx_dv   ),
+            .mac_rx_datain            (mac_rx_datain ),
+            
+            .local_ip_addr            (source_ip_addr ),
+            .local_mac_addr           (source_mac_addr),
+            .arp_reply_ack            (arp_reply_ack ),
+            .arp_reply_req            (arp_reply_req ),
+            .arp_rec_source_ip_addr   (arp_rec_source_ip_addr ),
+            .arp_rec_source_mac_addr  (arp_rec_source_mac_addr ),
+            
+            .udp_rec_ram_rdata        (udp_rec_ram_rdata),
+            .udp_rec_ram_read_addr    (udp_rec_ram_read_addr),
+            .udp_rec_data_length      (udp_rec_data_length ),
+            .udp_rec_data_valid       (udp_rec_data_valid),
+            
+            .mac_rx_dataout           (mac_rx_dataout ),
+            .upper_layer_data_length  (upper_layer_data_length  ),
+            .ip_total_data_length     (icmp_send_data_length),
+            .icmp_rx_req              (icmp_rx_req ),
+            .icmp_rev_error           (icmp_rev_error ),
+            
+            .arp_found                (arp_found  )
+           ) ;
+           
+           
+icmp_reply icmp0
+           (
+              .clk                      (gmii_rx_clk)                  ,
+              .rst_n                    (rst_n)  ,
+              .mac_send_end             (mac_send_end   ),
+              .icmp_rx_data             (mac_rx_dataout ),
+              .icmp_rx_req              (icmp_rx_req ),
+              .icmp_rev_error           (icmp_rev_error ),
+              
+              .upper_layer_data_length  (upper_layer_data_length  ),
+              
+              .icmp_data_req            (upper_data_req  ),
+              .icmp_tx_ready            (icmp_tx_ready ),
+              .icmp_tx_data             (icmp_tx_data  ),
+              .icmp_tx_end              (icmp_tx_end  ),
+              .ip_tx_ack              (icmp_tx_ack  ),
+              .icmp_tx_req              (icmp_tx_req  )
+             
+             
+           );
+           
+           
+arp_cache cache0
+(
+ .clk                         (gmii_tx_clk),
+ .rst_n                       (rst_n),
+ .arp_found                   (arp_found  ),
+ .arp_rec_source_ip_addr      (arp_rec_source_ip_addr ),
+ .arp_rec_source_mac_addr     (arp_rec_source_mac_addr ),
+ .destination_ip_addr         (destination_ip_addr),
+ .destination_mac_addr        (destination_mac_addr)   ,
+ .mac_not_exist               (mac_not_exist )
+);
+endmodule
+

rtl/ethernet-udp/src/eth/mac/rx/arp_rx.v

@@ -0,0 +1,210 @@
+//////////////////////////////////////////////////////////////////////////////////////
+//Module Name : arp_rx
+//Description : This module is used to receive ARP data and send ARP reply request
+//
+//////////////////////////////////////////////////////////////////////////////////////
+`timescale 1 ns/1 ns
+module arp_rx
+       (
+         input                  clk,
+         input                  rst_n,
+		 input                  crc_error,
+         
+         input [31:0]           local_ip_addr,
+         input [47:0]           local_mac_addr,
+         input  [7:0]           arp_rx_data,              //arp received data
+         input                  arp_rx_req,               //arp rx request from mac
+         output reg             arp_rx_end,               //arp rx end
+         
+         input                  arp_reply_ack,            //arp reply ack from arp reply module
+         output reg             arp_reply_req,            //arp reply request to arp reply module
+         
+         output reg [31:0]      arp_rec_source_ip_addr,   //arp received source ip address
+         output reg [47:0]      arp_rec_source_mac_addr,  //arp received mac address
+         output reg             arp_found                 //found destination mac address			
+			
+       ) ;
+       
+localparam ARP_REQUEST_CODE = 16'h0001 ;
+localparam ARP_REPLY_CODE   = 16'h0002 ;
+
+reg [31:0]              arp_rec_destination_ip_addr ;
+reg [47:0]              arp_rec_destination_mac_addr ;
+reg [15:0]              arp_rec_op ;
+reg [7:0]               arp_rx_cnt ;
+
+parameter IDLE          = 4'b0001 ;
+parameter ARP_REC_DATA  = 4'b0010 ;
+parameter ARP_WAIT      = 4'b0100 ;
+parameter ARP_END       = 4'b1000 ;
+
+reg [3:0]    state  ;
+reg [3:0]    next_state ;
+
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      state  <=  IDLE  ;
+    else
+      state  <= next_state ;
+  end
+  
+always @(*)
+  begin
+    case(state)
+      IDLE         :
+        begin
+          if (arp_rx_req)
+            next_state <= ARP_REC_DATA ;
+          else
+            next_state <= IDLE ;
+        end
+      ARP_REC_DATA :
+        begin
+          if (arp_rx_cnt == 45)
+            next_state <= ARP_WAIT     ;
+          else
+            next_state <= ARP_REC_DATA ;
+        end
+      ARP_WAIT     :
+        begin
+          if (arp_rx_cnt == 99)
+            next_state <= ARP_END     ;
+          else
+            next_state <= ARP_WAIT ;
+        end
+        
+      ARP_END      :
+        next_state <= IDLE ;
+        
+      default      :
+        next_state <= IDLE ;
+    endcase
+  end
+  
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      arp_rx_end <= 1'b0 ;
+    else if (state == ARP_REC_DATA && arp_rx_cnt == 44)
+      arp_rx_end <= 1'b1 ;
+    else
+      arp_rx_end <= 1'b0 ;
+  end
+  
+//received arp request
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      arp_reply_req  <= 1'b0 ;
+    else if (arp_rx_req)
+      arp_reply_req  <= 1'b0 ;
+    else if (arp_reply_ack)
+      arp_reply_req  <= 1'b0 ;
+    else if (state == ARP_END && crc_error == 1'b0)
+      begin
+        if (arp_rec_op == ARP_REQUEST_CODE && arp_rec_destination_ip_addr == local_ip_addr)
+          arp_reply_req <= 1'b1 ;
+      end
+  end
+//received arp reply
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      arp_found  <= 1'b0 ;
+    else if (state == ARP_END && crc_error == 1'b0)
+      begin
+        if (arp_rec_op == ARP_REPLY_CODE && arp_rec_destination_ip_addr == local_ip_addr && arp_rec_destination_mac_addr == local_mac_addr)			  
+          arp_found <= 1'b1 ;
+      end
+    else
+      arp_found  <= 1'b0 ;
+  end
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      arp_rx_cnt  <= 8'd0 ;
+    else if (state == ARP_REC_DATA || state == ARP_WAIT)
+      arp_rx_cnt <= arp_rx_cnt + 1'b1 ;
+    else
+      arp_rx_cnt <= 8'd0 ;
+  end
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      arp_rec_op <= 16'd0 ;
+    else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd6)
+      arp_rec_op[15:8] <= arp_rx_data ;
+    else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd7)
+      arp_rec_op[7:0] <= arp_rx_data ;
+  end
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      arp_rec_source_mac_addr <= 48'd0 ;
+    else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd8)
+      arp_rec_source_mac_addr[47:40] <= arp_rx_data ;
+    else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd9)
+      arp_rec_source_mac_addr[39:32] <= arp_rx_data ;
+    else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd10)
+      arp_rec_source_mac_addr[31:24] <= arp_rx_data ;
+    else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd11)
+      arp_rec_source_mac_addr[23:16] <= arp_rx_data ;
+    else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd12)
+      arp_rec_source_mac_addr[15:8] <= arp_rx_data ;
+    else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd13)
+      arp_rec_source_mac_addr[7:0] <= arp_rx_data ;
+  end
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      arp_rec_source_ip_addr <= 32'd0 ;
+    else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd14)
+      arp_rec_source_ip_addr[31:24] <= arp_rx_data ;
+    else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd15)
+      arp_rec_source_ip_addr[23:16] <= arp_rx_data ;
+    else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd16)
+      arp_rec_source_ip_addr[15:8] <= arp_rx_data ;
+    else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd17)
+      arp_rec_source_ip_addr[7:0] <= arp_rx_data ;
+  end
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      arp_rec_destination_mac_addr <= 48'd0 ;
+    else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd18)
+      arp_rec_destination_mac_addr[47:40] <= arp_rx_data ;
+    else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd19)
+      arp_rec_destination_mac_addr[39:32] <= arp_rx_data ;
+    else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd20)
+      arp_rec_destination_mac_addr[31:24] <= arp_rx_data ;
+    else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd21)
+      arp_rec_destination_mac_addr[23:16] <= arp_rx_data ;
+    else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd22)
+      arp_rec_destination_mac_addr[15:8] <= arp_rx_data ;
+    else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd23)
+      arp_rec_destination_mac_addr[7:0] <= arp_rx_data ;
+  end
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      arp_rec_destination_ip_addr <= 32'd0 ;
+    else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd24)
+      arp_rec_destination_ip_addr[31:24] <= arp_rx_data ;
+    else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd25)
+      arp_rec_destination_ip_addr[23:16] <= arp_rx_data ;
+    else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd26)
+      arp_rec_destination_ip_addr[15:8] <= arp_rx_data ;
+    else if (state == ARP_REC_DATA && arp_rx_cnt == 8'd27)
+      arp_rec_destination_ip_addr[7:0] <= arp_rx_data ;
+  end
+  
+  
+endmodule

rtl/ethernet-udp/src/eth/mac/rx/ip_rx.v

@@ -0,0 +1,360 @@
+//////////////////////////////////////////////////////////////////////////////////////
+//Module Name : ip_rx
+//Description : This module is used to receive IP data and verify IP header checksum
+//
+//////////////////////////////////////////////////////////////////////////////////////
+`timescale 1 ns/1 ns
+module ip_rx
+//#
+//(
+// parameter local_mac_addr = 48'h00_0a_35_01_fe_c0,
+// parameter local_ip_addr  = 32'hc0a80002
+//)
+(
+ input                  clk,   
+ input                  rst_n,  
+ 
+ input	[31:0]					local_ip_addr,
+ input	[47:0]					local_mac_addr,
+ 
+ input  [7:0]           ip_rx_data,
+ input                  ip_rx_req,  
+ input  [47:0]          mac_rx_destination_mac_addr, 
+
+ output reg             udp_rx_req,                   //udp rx request
+ output reg             icmp_rx_req,                  //icmp rx request  
+ output reg             ip_addr_check_error,          //ip address is not equal to local address
+ 
+ output reg [15:0]      upper_layer_data_length,      //udp or icmp data length = ip data length - ip header length
+ output reg [15:0]      ip_total_data_length,         //send data length
+ 
+ output reg [7:0]       net_protocol,                 //network layer protocol: 8'h11 udp  8'h01 icmp
+ output reg [31:0]      ip_rec_source_addr,           //received source ip address
+ output reg [31:0]      ip_rec_destination_addr,      //received destination ip address
+ 
+ output reg             ip_rx_end,
+ output reg             ip_checksum_error
+ 
+) ;
+
+reg  [15:0]             ip_rx_cnt ;
+reg  [15:0]             ip_rec_data_length ;
+          
+reg  [7:0]              ip_rx_data_d0 ;
+reg  [7:0]              ip_rx_data_d1 ;
+          
+reg  [15:0]             ip_rec_checksum ;
+
+reg  [3:0]              header_length_buf ;
+wire [5:0]              header_length ;
+
+parameter IDLE             =  5'b00001  ;
+parameter REC_HEADER0      =  5'b00010  ;
+parameter REC_HEADER1      =  5'b00100  ;
+parameter REC_DATA         =  5'b01000  ;
+parameter REC_END          =  5'b10000  ;
+
+reg [4:0]     state      ;
+reg [4:0]     next_state ;
+
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+    state <= IDLE ;
+  else 
+    state <= next_state ;
+end
+
+always @(*)
+begin
+    case(state)
+	 IDLE            :  begin
+	                      if (ip_rx_req == 1'b1)
+													next_state <= REC_HEADER0 ;
+												else
+													next_state <= IDLE ;
+											end
+	 REC_HEADER0    :	  begin
+                        if (ip_rx_cnt == 16'd3)
+													next_state <= REC_HEADER1 ;
+												else
+	                        next_state <= REC_HEADER0 ;
+											end
+	 REC_HEADER1    :  	begin
+                        if (ip_rx_cnt == header_length - 1)
+													next_state <= REC_DATA ;
+												else
+	                        next_state <= REC_HEADER1 ;
+											end
+	 REC_DATA       :   begin
+                        if (ip_checksum_error || ip_rx_end)
+													next_state <= REC_END ;		
+												else if (ip_rx_cnt == 16'hffff)
+													next_state <= REC_END ; 						
+												else
+	                        next_state <= REC_DATA ;
+											end	
+	 REC_END        : 			next_state <= IDLE  ;
+	 default        : 			next_state <= IDLE  ;
+	 endcase
+end
+
+assign header_length       = 4*header_length_buf ;
+
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+    ip_rx_end <= 1'b0 ;
+  else if (state == REC_DATA && ip_rx_cnt == ip_total_data_length - 2)
+    ip_rx_end <= 1'b1 ;
+  else
+    ip_rx_end <= 1'b0 ;
+end
+//mac addr and ip addr is not equal to local addr, assert error
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+    ip_addr_check_error <= 1'b0 ;
+  else if (state == REC_DATA)
+  begin
+    if (mac_rx_destination_mac_addr == local_mac_addr && ip_rec_destination_addr == local_ip_addr)						
+      ip_addr_check_error <= 1'b0 ;
+    else
+      ip_addr_check_error <= 1'b1 ;
+  end
+  else
+    ip_addr_check_error <= 1'b0 ;
+end
+//generate udp rx request signal
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+    udp_rx_req <= 1'b0 ;
+  else if (state == REC_HEADER1 && net_protocol == 8'h11 && ip_rx_cnt == header_length - 2)
+    udp_rx_req <= 1'b1 ;
+  else
+    udp_rx_req <= 1'b0 ;
+end
+//generate icmp rx request signal
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+    icmp_rx_req <= 1'b0 ;
+  else if (state == REC_HEADER1 && net_protocol == 8'h01 && ip_rx_cnt == header_length - 2)
+    icmp_rx_req <= 1'b1 ;
+  else
+    icmp_rx_req <= 1'b0 ;
+end
+
+
+//icmp or udp data length										
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+  begin
+    upper_layer_data_length <= 16'd0 ;
+  end
+  else
+  begin
+    upper_layer_data_length <= ip_rec_data_length - header_length  ;
+  end
+end 
+										
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+  begin
+    ip_rx_data_d0 <= 8'd0 ;
+		ip_rx_data_d1 <= 8'd0 ;
+  end
+  else
+  begin
+    ip_rx_data_d0 <= ip_rx_data ;
+		ip_rx_data_d1 <= ip_rx_data_d0 ;
+  end
+end  
+
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+    ip_rx_cnt <= 16'd0 ;
+  else if (state == REC_HEADER0 || state == REC_HEADER1 || state == REC_DATA)
+    ip_rx_cnt <= ip_rx_cnt + 1'b1 ;
+  else
+    ip_rx_cnt <= 16'd0 ;
+end
+//total length
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+    ip_total_data_length <= 16'd0 ;
+  else if (state == REC_HEADER1)
+  begin
+    if (ip_rec_data_length < 16'd46)
+			ip_total_data_length <= 16'd46 ;
+    else
+      ip_total_data_length <= ip_rec_data_length ;
+  end
+end
+
+
+//ip header length
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+    header_length_buf <= 4'd0 ;
+  else if (state == REC_HEADER0 && ip_rx_cnt == 16'd0)
+    header_length_buf <= ip_rx_data[3:0] ;
+end
+//ip data total length
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+    ip_rec_data_length <= 16'd0 ;
+  else if (state == REC_HEADER0 && ip_rx_cnt == 16'd2)
+    ip_rec_data_length[15:8] <= ip_rx_data  ;
+  else if (state == REC_HEADER0 && ip_rx_cnt == 16'd3)
+    ip_rec_data_length[7:0] <= ip_rx_data  ;
+end
+//network layer protocol
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+    net_protocol <= 8'd0 ;
+  else if (state == REC_HEADER1 && ip_rx_cnt == 16'd9)
+    net_protocol <= ip_rx_data ;
+end
+
+//ip source address
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+    ip_rec_source_addr <= 32'd0 ;
+  else if (state == REC_HEADER1 && ip_rx_cnt == 16'd12)
+    ip_rec_source_addr[31:24] <= ip_rx_data ;
+  else if (state == REC_HEADER1 && ip_rx_cnt == 16'd13)
+    ip_rec_source_addr[23:16] <= ip_rx_data ;
+  else if (state == REC_HEADER1 && ip_rx_cnt == 16'd14)
+    ip_rec_source_addr[15:8] <= ip_rx_data ;
+  else if (state == REC_HEADER1 && ip_rx_cnt == 16'd15)
+    ip_rec_source_addr[7:0] <= ip_rx_data ;
+end
+//ip source address
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+    ip_rec_destination_addr <= 32'd0 ;
+  else if (state == REC_HEADER1 && ip_rx_cnt == 16'd16)
+    ip_rec_destination_addr[31:24] <= ip_rx_data ;
+  else if (state == REC_HEADER1 && ip_rx_cnt == 16'd17)
+    ip_rec_destination_addr[23:16] <= ip_rx_data ;
+  else if (state == REC_HEADER1 && ip_rx_cnt == 16'd18)
+    ip_rec_destination_addr[15:8] <= ip_rx_data ;
+  else if (state == REC_HEADER1 && ip_rx_cnt == 16'd19)
+    ip_rec_destination_addr[7:0] <= ip_rx_data ;
+end
+
+
+//****************************************************************//
+//verify checksum
+//****************************************************************//
+reg  [31:0] checksum_tmp ;
+reg  [31:0] checksum_buf ;
+reg  [31:0] check_out ;
+reg  [31:0] checkout_buf ;
+wire [15:0] checksum ;
+reg  [2:0]  checksum_cnt ;
+
+//checksum function 
+function    [31:0]  checksum_adder
+(
+ input       [31:0]  dataina,
+ input       [31:0]  datainb
+);
+
+begin
+    checksum_adder = dataina + datainb;
+end   
+endfunction 
+
+function    [31:0]  checksum_out
+(
+ input      [31:0]  dataina
+);
+
+begin
+    checksum_out = dataina[15:0]+dataina[31:16];
+end  
+ 
+endfunction 
+
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+     checksum_tmp <= 32'd0; 
+  else if (state == REC_HEADER0 || state == REC_HEADER1)
+  begin
+    if (ip_rx_cnt[0] == 1'b1)
+      checksum_tmp <= checksum_adder({ip_rx_data_d0, ip_rx_data},checksum_buf);
+  end
+  else if (state == IDLE)
+    checksum_tmp <= 32'd0; 
+end
+
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+     check_out <= 32'd0; 
+  else if (state == REC_DATA)   
+	  check_out <= checksum_out(checksum_tmp) ;
+end
+
+always @(posedge clk or negedge rst_n)
+begin
+  if(rst_n == 1'b0)
+      checksum_cnt <= 3'd0 ; 
+  else if (state == 	REC_DATA)
+  begin
+    if (checksum_cnt == 3'd7)
+	   checksum_cnt <= checksum_cnt ;	
+    else	
+	   checksum_cnt <= checksum_cnt + 1'b1 ;
+  end
+  else
+	   checksum_cnt <= 3'd0 ;	
+end
+
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+    checksum_buf <= 32'd0 ;
+  else
+    checksum_buf <= checksum_tmp ;
+end
+
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+    checkout_buf <= 32'd0 ;
+  else
+    checkout_buf <= check_out ;
+end
+
+assign checksum = ~checkout_buf[15:0] ;
+
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+    ip_checksum_error <= 1'b0 ;
+  else if (state == REC_DATA && checksum_cnt == 3'd2)
+  begin
+    if (checksum == 16'd0)	 
+      ip_checksum_error <= 1'b0 ;
+    else
+      ip_checksum_error <= 1'b1 ;
+    end
+  else
+      ip_checksum_error <= 1'b0 ;
+end 
+
+endmodule

rtl/ethernet-udp/src/eth/mac/rx/mac_rx.v

@@ -0,0 +1,449 @@
+//////////////////////////////////////////////////////////////////////////////////////
+//Module Name : mac_rx
+//Description : This module is used to receive MAC layer data and verify CRC
+//
+//////////////////////////////////////////////////////////////////////////////////////
+`timescale 1 ns/1 ns
+module mac_rx
+(
+ input                  clk,   
+ input                  rst_n,    
+ 
+ input                  rx_dv,
+ input      [7:0]       mac_rx_datain,
+ 
+ input      [31:0]      crc_result ,       
+ output reg                crcen,          
+ output reg                crcre, 
+ output reg    [7:0]       crc_din,
+ 
+ input                  checksum_err,     //checksum error from IP layer
+ 
+ input                  ip_rx_end,        //ip receive end
+ input                  arp_rx_end,       //arp receive end 
+ output reg             ip_rx_req,        //ip rx request
+ output reg             arp_rx_req,       //arp rx request
+ 
+ output     [7:0]       mac_rx_dataout,
+ output reg             mac_rec_error ,
+ 
+ output reg [47:0]      mac_rx_destination_mac_addr,
+ output reg [47:0]      mac_rx_source_mac_addr
+);
+
+reg [4:0]               mac_rx_cnt       ;
+reg [15:0]              mac_crc_cnt      ;
+reg                     mac_sync         ;   //check preamble is right, then sync
+reg [63:0]              preamble         ;           
+reg [3:0]               preamble_cnt     ;
+           
+reg [15:0]              frame_type       ;   //type 16'h0800 IP; 16'h0806 ARP
+
+           
+wire                    rx_dv_posedge    ;
+reg                     rx_dv_d0         ;
+reg                     rx_dv_d1         ;
+       
+reg [7:0]               mac_rx_data_d0   ;
+reg [7:0]               mac_rx_data_d1   ;
+reg [7:0]               mac_rx_data_d2   ;
+       
+wire                    mac_rx_head_end  ;
+       
+reg  [15:0]             timeout          ;
+       
+reg  [31:0]             crc              ;
+reg  [31:0]             crc_check        ;
+reg                     crc_error        ;
+reg  [31:0]             crc_rec          ;
+reg	 [31:0]			    crc_result_d0   ;
+
+//MAC receive FSM
+parameter IDLE                =  9'b000_000_001 ;
+parameter REC_PREAMBLE        =  9'b000_000_010 ;
+parameter REC_MAC_HEAD        =  9'b000_000_100 ;
+parameter REC_IDENTIFY        =  9'b000_001_000 ;
+parameter REC_IP_DATA         =  9'b000_010_000 ;
+parameter REC_ARP_DATA        =  9'b000_100_000 ;
+parameter REC_CRC             =  9'b001_000_000 ;
+parameter REC_ERROR           =  9'b010_000_000 ;
+parameter REC_END             =  9'b100_000_000 ;
+
+reg [8:0]     rec_state      ;
+reg [8:0]     rec_next_state ;
+
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+    rec_state <= IDLE ;
+  else 
+    rec_state <= rec_next_state ;
+end
+
+always @(*)
+begin
+    case(rec_state)
+	 IDLE            :  begin
+	                      if (rx_dv_posedge == 1'b1)
+                                rec_next_state <= REC_PREAMBLE ;
+                        else
+                                rec_next_state <= IDLE ;
+	                    end
+	 REC_PREAMBLE    :  begin
+                            if (mac_sync == 1'b1)
+                                rec_next_state <=  REC_MAC_HEAD  ;
+                            else if (timeout == 16'hffff)
+                                rec_next_state <= REC_ERROR ;
+                            else
+                                rec_next_state <=  REC_PREAMBLE    ;
+                        end
+
+	 REC_MAC_HEAD    : begin
+                            if ( mac_rx_cnt == 16'd13)
+                                rec_next_state <= REC_IDENTIFY ;
+                            else if (timeout == 16'hffff)
+                                rec_next_state <= REC_ERROR ;
+                            else
+                                rec_next_state <= REC_MAC_HEAD ; 
+                     end
+	 REC_IDENTIFY    : begin
+	                      if (frame_type == 16'h0800)
+                                rec_next_state <= REC_IP_DATA ;
+                            else if (frame_type == 16'h0806)
+                                rec_next_state <= REC_ARP_DATA ;
+                            else if (timeout == 16'hffff)
+                                rec_next_state <= REC_ERROR ;
+                            else
+                                rec_next_state <= REC_IDENTIFY ; 
+                     end
+	 REC_IP_DATA     : begin
+	                      if (checksum_err)
+                            rec_next_state <= REC_ERROR ;
+                        else if (ip_rx_end)
+                            rec_next_state <= REC_CRC ;
+                        else if (timeout == 16'hffff)
+                            rec_next_state <= REC_ERROR ;
+                        else
+                        rec_next_state <= REC_IP_DATA ;
+                        end
+	 REC_ARP_DATA    : begin
+	                    if (arp_rx_end)
+                            rec_next_state <= REC_CRC ;
+                        else if (timeout == 16'hffff)
+                            rec_next_state <= REC_ERROR ;
+                        else
+	                      rec_next_state <= REC_ARP_DATA ;
+                         end
+	  						 
+	 REC_CRC         : begin
+                        if (crc_error)
+                            rec_next_state <= REC_ERROR ;
+                        else if (mac_rx_cnt == 7)
+                            rec_next_state <= REC_END ;
+                        else
+                            rec_next_state <= REC_CRC ;
+                       end
+	 REC_ERROR      : 			rec_next_state <= IDLE  ;
+	 REC_END        : 			rec_next_state <= IDLE  ;
+	 default        : 			rec_next_state <= IDLE  ;
+	 endcase
+end
+
+
+
+
+assign mac_rx_dataout  = mac_rx_data_d2 ;
+assign rx_dv_posedge   = ~rx_dv_d0 & rx_dv ;
+
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+  begin
+    crcen <= 	1'b0 ;
+		crcre <= 1'b1 ;
+		crc_din <= 8'd0 ;
+  end
+  else if (rec_state == REC_MAC_HEAD || rec_state == REC_IDENTIFY || rec_state == REC_IP_DATA || rec_state == REC_ARP_DATA)
+  begin
+    crcen <= 	1'b1 ;
+		crcre <= 	1'b0 ;
+		crc_din <= mac_rx_data_d0 ;
+  end
+  else
+  begin
+    crcen <= 	1'b0 ;
+		crcre <= 1'b1 ;
+		crc_din <= 8'd0 ;
+  end
+end
+
+
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+    ip_rx_req <= 	1'b0 ;
+  else if (rec_state == REC_IDENTIFY &&  frame_type == 16'h0800)
+    ip_rx_req <=  1'b1 ;
+  else
+    ip_rx_req <=  1'b0 ;
+end
+
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+    arp_rx_req <= 	1'b0 ;
+  else if (rec_state == REC_IDENTIFY &&  frame_type == 16'h0806)
+    arp_rx_req <=  	1'b1 ;
+  else
+    arp_rx_req <=  	1'b0 ;
+end
+
+//rx dv and rx data resigster
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+  begin
+    rx_dv_d0       <= 1'b0 ;
+		rx_dv_d1       <= 1'b0 ;
+    mac_rx_data_d0 <= 8'd0 ;
+		mac_rx_data_d1 <= 8'd0 ;
+		mac_rx_data_d2 <= 8'd0 ;
+  end
+  else
+  begin
+		rx_dv_d0       		<= rx_dv ;
+		rx_dv_d1      	  <= rx_dv_d0 ;
+		mac_rx_data_d0 		<= mac_rx_datain ;
+		mac_rx_data_d1	 	<= mac_rx_data_d0 ;
+		mac_rx_data_d2 		<= mac_rx_data_d1 ;
+  end
+end
+//timeout
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+    timeout <= 16'd0 ;
+  else if (rec_state == REC_PREAMBLE || rec_state == REC_MAC_HEAD || rec_state == REC_MAC_HEAD || rec_state == REC_IDENTIFY 
+           || rec_state == REC_IP_DATA || rec_state == REC_ARP_DATA)
+    timeout <= timeout + 1'b1 ;
+  else
+    timeout <= 16'd0 ;
+end
+
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+    mac_rx_cnt <= 5'd0 ;
+  else if (mac_sync)
+    mac_rx_cnt <= 5'd0 ;
+  else if (rec_state == REC_PREAMBLE || rec_state == REC_MAC_HEAD || rec_state == REC_CRC)
+    mac_rx_cnt <= mac_rx_cnt + 1'b1 ;
+  else
+    mac_rx_cnt <= 5'd0 ;
+end
+
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+    mac_crc_cnt <= 16'd0 ;
+  else if (rx_dv_d1)
+    mac_crc_cnt <= mac_crc_cnt + 1'b1 ;
+  else
+    mac_crc_cnt <= 16'd0 ;
+end
+
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+    mac_rec_error <= 1'b0 ;
+  else if (rx_dv_posedge)
+    mac_rec_error <= 1'b0 ;
+  else if (rec_state == REC_ERROR)
+    mac_rec_error <= 1'b1 ;
+end
+
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+    crc <= 32'd0 ;
+  else if (crcen)
+    crc <= crc_result_d0 ;
+end
+
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+    crc_result_d0 <= 32'd0 ;
+  else 
+    crc_result_d0 <= crc_result ;
+end
+
+
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+    crc_check <= 32'd0 ;
+  else if (rec_state == REC_CRC)
+  begin
+    case(mac_rx_cnt)
+      5'd1  :  crc_check[31:24] <= {~crc[24], ~crc[25], ~crc[26], ~crc[27], ~crc[28], ~crc[29], ~crc[30], ~crc[31]} ;
+      5'd2  :  crc_check[23:16] <= {~crc[16], ~crc[17], ~crc[18], ~crc[19], ~crc[20], ~crc[21], ~crc[22], ~crc[23]} ;
+      5'd3  :  crc_check[15:8]  <= {~crc[8], ~crc[9], ~crc[10], ~crc[11], ~crc[12], ~crc[13], ~crc[14], ~crc[15]}   ;
+      5'd4  :  crc_check[7:0]   <= {~crc[0], ~crc[1], ~crc[2], ~crc[3], ~crc[4], ~crc[5], ~crc[6], ~crc[7]}   ;
+    default :  crc_check <= crc_check ;
+    endcase
+  end
+  else 
+    crc_check <= 32'd0 ;
+end
+//received crc data
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n) 
+    crc_rec  <= 48'd0 ;
+  else if (rec_state == REC_CRC)
+  begin
+    case(mac_rx_cnt)
+	  5'd0   : crc_rec[31:24]      <= mac_rx_data_d2 ;
+      5'd1   : crc_rec[23:16]      <= mac_rx_data_d2 ;
+      5'd2   : crc_rec[15:8]       <= mac_rx_data_d2 ;
+      5'd3   : crc_rec[7:0]        <= mac_rx_data_d2 ;
+      default : crc_rec             <= crc_rec     ;
+    endcase
+  end
+  else
+    crc_rec <= crc_rec ;
+end 
+//check crc
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+    crc_error <= 1'b0 ;
+  else if (rec_state == REC_CRC && mac_rx_cnt == 5)
+  begin
+    if (crc_check == crc_rec)
+       crc_error <= 1'b0 ;
+	 else
+	    crc_error <= 1'b1 ;
+  end
+  else
+    crc_error <= 1'b0 ;
+end
+
+//mac sync signal
+always @(*)
+begin
+  if (rec_state == REC_PREAMBLE)
+  begin
+    if (mac_rx_cnt == 7 && preamble == 64'h55_55_55_55_55_55_55_d5)
+	   mac_sync <= 1'b1 ;
+	 else
+	   mac_sync <= 1'b0 ;
+   end
+  else
+      mac_sync <= 1'b0 ;
+end	  
+
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n) 
+    preamble_cnt  <= 4'd0 ;
+  else if (rx_dv)
+  begin
+    if (preamble_cnt < 8)
+      preamble_cnt <= preamble_cnt + 1'b1 ;
+  end
+  else
+    preamble_cnt <= 4'd0 ;
+end
+
+
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n) 
+    preamble  <= 64'd0 ;
+  else if (rx_dv)
+  begin
+    if (preamble_cnt == 4'd0)
+      preamble[63:56] <= mac_rx_datain ;
+    if (preamble_cnt == 4'd1)
+      preamble[55:48] <= mac_rx_datain ;
+    if (preamble_cnt == 4'd2)
+      preamble[47:40] <= mac_rx_datain ;
+    if (preamble_cnt == 4'd3)
+      preamble[39:32] <= mac_rx_datain ;
+    if (preamble_cnt == 4'd4)
+      preamble[31:24] <= mac_rx_datain ;
+    if (preamble_cnt == 4'd5)
+      preamble[23:16] <= mac_rx_datain ; 
+    if (preamble_cnt == 4'd6)
+      preamble[15:8] <= mac_rx_datain ;
+    if (preamble_cnt == 4'd7)
+      preamble[7:0] <= mac_rx_datain ; 
+  end
+  else
+    preamble <= 64'd0 ;
+end   
+
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n) 
+    mac_rx_destination_mac_addr  <= 48'd0 ;
+  else if (rec_state == REC_MAC_HEAD)
+  begin
+    case(mac_rx_cnt)
+      5'd0   : mac_rx_destination_mac_addr[47:40] <= mac_rx_data_d0 ;
+      5'd1   : mac_rx_destination_mac_addr[39:32] <= mac_rx_data_d0 ;
+      5'd2   : mac_rx_destination_mac_addr[31:24] <= mac_rx_data_d0 ;
+      5'd3   : mac_rx_destination_mac_addr[23:16] <= mac_rx_data_d0 ;
+      5'd4   : mac_rx_destination_mac_addr[15:8]  <= mac_rx_data_d0 ;
+      5'd5   : mac_rx_destination_mac_addr[7:0]   <= mac_rx_data_d0 ;
+      default : mac_rx_destination_mac_addr <= mac_rx_destination_mac_addr ;
+	 endcase
+  end
+  else
+    mac_rx_destination_mac_addr <= mac_rx_destination_mac_addr ;
+end
+
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n) 
+    mac_rx_source_mac_addr  <= 48'd0 ;
+  else if (rec_state == REC_MAC_HEAD)
+  begin
+    case(mac_rx_cnt)
+      5'd6   : mac_rx_source_mac_addr[47:40]      <= mac_rx_data_d0 ;
+      5'd7   : mac_rx_source_mac_addr[39:32]      <= mac_rx_data_d0 ;
+      5'd8   : mac_rx_source_mac_addr[31:24]      <= mac_rx_data_d0 ;
+      5'd9   : mac_rx_source_mac_addr[23:16]      <= mac_rx_data_d0 ;
+      5'd10  : mac_rx_source_mac_addr[15:8]       <= mac_rx_data_d0 ;
+      5'd11  : mac_rx_source_mac_addr[7:0]        <= mac_rx_data_d0 ;
+	 default : mac_rx_source_mac_addr             <= mac_rx_source_mac_addr ;
+	 endcase
+  end
+  else
+    mac_rx_source_mac_addr <= mac_rx_source_mac_addr ;
+end
+
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n) 
+    frame_type  <= 16'd0 ;
+  else if (rec_state == REC_MAC_HEAD)
+  begin
+    case(mac_rx_cnt)
+	  5'd12  : frame_type[15:8]                   <= mac_rx_data_d0 ;
+      5'd13  : frame_type[7:0]                    <= mac_rx_data_d0 ;
+      default : frame_type                         <= frame_type     ;
+    endcase
+  end
+  else
+    frame_type <= frame_type ;
+end 
+ 
+
+
+ 
+endmodule
+
+

rtl/ethernet-udp/src/eth/mac/rx/mac_rx_top.v

@@ -0,0 +1,186 @@
+//////////////////////////////////////////////////////////////////////////////////////
+//Module Name : mac_rx_top
+//Description : MAC RX Top
+//
+//////////////////////////////////////////////////////////////////////////////////////
+`timescale 1 ns/1 ns
+module mac_rx_top
+       (
+         input                  clk,
+         input                  rst_n,
+         
+         input                  rx_dv,
+         (* MARK_DEBUG="true" *)input  [7:0]           mac_rx_datain,
+         
+         input [31:0]           local_ip_addr,
+         input [47:0]           local_mac_addr,
+         
+         input                  arp_reply_ack,
+         output                 arp_reply_req,
+         output [31:0]          arp_rec_source_ip_addr,
+         output [47:0]          arp_rec_source_mac_addr,
+         
+         
+         (* MARK_DEBUG="true" *)output [7:0]           udp_rec_ram_rdata ,
+         (* MARK_DEBUG="true" *)input  [10:0]          udp_rec_ram_read_addr,
+         (* MARK_DEBUG="true" *)output [15:0]          udp_rec_data_length,
+         (* MARK_DEBUG="true" *)output                 udp_rec_data_valid,
+         
+         (* MARK_DEBUG="true" *)output [7:0]           mac_rx_dataout,
+         (* MARK_DEBUG="true" *)output [15:0]          upper_layer_data_length ,
+         (* MARK_DEBUG="true" *)output [15:0]          ip_total_data_length,
+         output                 icmp_rx_req,
+         output                 icmp_rev_error,
+         
+         output                 arp_found
+       ) ;
+       
+       
+       
+wire                    ip_rx_req ;
+wire                    udp_rx_req ;
+wire                    ip_rx_end ;
+
+wire                    arp_rx_req ;
+wire                    arp_rx_end  ;
+
+wire [7:0]              net_protocol ;
+wire [31:0]             ip_rec_destination_addr ;
+wire [31:0]             ip_rec_source_ip_addr ;
+
+wire                    ip_addr_check_error  ;
+wire                    ip_checksum_error ;
+wire                    mac_rec_error ;
+
+wire [47:0]             mac_rx_destination_mac_addr ;
+wire [47:0]             mac_rx_source_mac_addr ;
+
+wire                    crcen ;
+wire                    crcre ;
+wire [7:0]              crc_din ;
+wire [31:0]             crc_result ;
+
+
+
+assign  icmp_rev_error = (mac_rec_error | ip_checksum_error | ip_addr_check_error)  ;
+
+
+crc c0
+    (
+      .Clk                           (clk),
+      .Reset                         (crcre),
+      .Data_in                       (crc_din),
+      .Enable                        (crcen),
+      .Crc                           (crc_result),
+      .CrcNext                       ()
+    ) ;
+    
+mac_rx mac0
+       (
+         .clk                           (clk)   ,
+         .rst_n                         (rst_n)   ,
+         
+         .rx_dv                         (rx_dv   ),
+         .mac_rx_datain                 (mac_rx_datain ),
+         
+         .crc_result                    (crc_result ) ,
+         .crcen                         (crcen  ),
+         .crcre                         (crcre  ),
+         .crc_din                       (crc_din ),
+         
+         .checksum_err                  (ip_checksum_error  ),
+         
+         .ip_rx_end                     (ip_rx_end  ),
+         .arp_rx_end                    (arp_rx_end),
+         
+         .ip_rx_req                     (ip_rx_req ),
+         .arp_rx_req                    (arp_rx_req),
+         
+         .mac_rx_dataout                (mac_rx_dataout ),
+         .mac_rec_error                 (mac_rec_error),
+         
+         .mac_rx_destination_mac_addr   (mac_rx_destination_mac_addr ),
+         .mac_rx_source_mac_addr        (mac_rx_source_mac_addr)
+       );
+       
+       
+ip_rx ip0
+      (
+        .clk                           (clk),
+        .rst_n                         (rst_n) ,
+        
+        .local_ip_addr                 (local_ip_addr ),
+        .local_mac_addr                (local_mac_addr),
+        
+        .ip_rx_data                    (mac_rx_dataout) ,
+        .ip_rx_req                     (ip_rx_req)  ,
+        .ip_rx_end                     (ip_rx_end) ,
+        .icmp_rx_req                   (icmp_rx_req ),
+        
+        .ip_addr_check_error           (ip_addr_check_error),
+        .mac_rx_destination_mac_addr   (mac_rx_destination_mac_addr),
+        
+        .upper_layer_data_length       (upper_layer_data_length  ),
+        .ip_total_data_length          (ip_total_data_length    ),
+        
+        .net_protocol                  (net_protocol),
+        .ip_rec_source_addr            (ip_rec_source_ip_addr),
+        .ip_rec_destination_addr       (ip_rec_destination_addr),
+        .udp_rx_req                    (udp_rx_req),
+        .ip_checksum_error             (ip_checksum_error)
+        
+      ) ;
+      
+      
+udp_rx udp0
+       (
+         .clk                           (clk)   ,
+         .rst_n                         (rst_n) ,
+         
+         .udp_rx_data                   (mac_rx_dataout),
+         .udp_rx_req                    (udp_rx_req),
+         
+         .mac_rec_error                 (mac_rec_error),
+         
+         .ip_addr_check_error           (ip_addr_check_error),
+         
+         .net_protocol                  (net_protocol),
+         .ip_rec_source_addr            (ip_rec_source_ip_addr),
+         .ip_rec_destination_addr       (ip_rec_destination_addr),
+         .ip_checksum_error             (ip_checksum_error),
+         
+         .upper_layer_data_length       (upper_layer_data_length  ),
+         
+         .udp_rec_ram_rdata             (udp_rec_ram_rdata),
+         .udp_rec_ram_read_addr         (udp_rec_ram_read_addr),
+         .udp_rec_data_length           (udp_rec_data_length ),
+         
+         .udp_rec_data_valid            (udp_rec_data_valid)
+       );
+       
+       
+arp_rx  arp0
+        (
+          .clk                           (clk) ,
+          .rst_n                         (rst_n),
+			 
+		 .crc_error                     (mac_rec_error),
+          
+          .local_ip_addr                 (local_ip_addr ),
+          .local_mac_addr                (local_mac_addr),
+          
+          .arp_rx_data                   (mac_rx_dataout ),
+          .arp_rx_req                    (arp_rx_req ),
+          
+          .arp_reply_ack                 (arp_reply_ack ),
+          .arp_rx_end                    (arp_rx_end ),
+          .arp_reply_req                 (arp_reply_req ),
+          
+          .arp_rec_source_ip_addr        (arp_rec_source_ip_addr ),
+          .arp_rec_source_mac_addr       (arp_rec_source_mac_addr ),
+          .arp_found                     (arp_found )
+          
+        ) ;
+        
+        
+endmodule

rtl/ethernet-udp/src/eth/mac/rx/udp_rx.v

@@ -0,0 +1,372 @@
+//////////////////////////////////////////////////////////////////////////////////////
+//Module Name : udp_rx
+//Description : This module is used to receive UDP data and verify UDP checksum
+//
+//////////////////////////////////////////////////////////////////////////////////////
+`timescale 1 ns/1 ns
+module udp_rx
+(
+ input                  clk,   
+ input                  rst_n,  
+ 
+ input      [7:0]       udp_rx_data,
+ input                  udp_rx_req,
+ 
+ input                  mac_rec_error, 
+ input      [7:0]       net_protocol,
+ input      [31:0]      ip_rec_source_addr,
+ input      [31:0]      ip_rec_destination_addr,
+ input                  ip_checksum_error,
+ input                  ip_addr_check_error,
+ 
+ input      [15:0]      upper_layer_data_length, 
+ output     [7:0]       udp_rec_ram_rdata ,      //udp ram read data
+ input      [10:0]      udp_rec_ram_read_addr,   //udp ram read address
+ output reg [15:0]      udp_rec_data_length,     //udp data length
+ output reg             udp_rec_data_valid       //udp data valid
+);
+
+reg  [15:0]             udp_rx_cnt ;
+reg                     verify_end ;
+reg                     udp_checksum_error ;  
+          
+(* MARK_DEBUG="true" *)reg	 [10:0]             ram_write_addr ;
+(* MARK_DEBUG="true" *)reg	                    ram_wr_en ;
+reg  [15:0]             udp_data_length ;
+reg                     ip_addr_check_error_d0 ;
+reg  [7:0]              udp_rx_data_d0 ;         //udp data resigster
+
+parameter IDLE             =  8'b0000_0001  ;
+parameter REC_HEAD         =  8'b0000_0010  ;
+parameter REC_DATA         =  8'b0000_0100  ;
+parameter REC_ODD_DATA     =  8'b0000_1000  ;
+parameter VERIFY_CHECKSUM  =  8'b0001_0000  ;
+parameter REC_ERROR        =  8'b0010_0000  ;
+parameter REC_END_WAIT     =  8'b0100_0000  ;
+parameter REC_END          =  8'b1000_0000  ;
+
+reg [7:0]     state      ;
+reg [7:0]     next_state ;
+
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+    state <= IDLE ;
+  else 
+    state <= next_state ;
+end
+
+always @(*)
+begin
+    case(state)
+	 IDLE            :begin
+	                    if (udp_rx_req == 1'b1)
+												next_state <= REC_HEAD ;
+											else
+												next_state <= IDLE ;
+										end
+	 REC_HEAD       : begin
+	                    if (ip_checksum_error)
+												next_state <= REC_ERROR ;
+                      else if (udp_rx_cnt == 16'd7)
+											begin
+												if (udp_data_length == 16'd9)
+													next_state <= REC_ODD_DATA ;
+												else
+													next_state <= REC_DATA ;
+											end
+											else if (ip_addr_check_error_d0)
+													next_state <= REC_ERROR ;
+											else
+	                       next_state <= REC_HEAD ;
+	                   end
+	 REC_DATA       : begin
+	                    if (ip_checksum_error)
+												next_state <= REC_ERROR ;
+											else if (udp_data_length[0] == 1'b1 && udp_rx_cnt == udp_data_length - 2)
+												next_state <= REC_ODD_DATA ;
+											else if (udp_data_length[0] == 1'b0 && udp_rx_cnt == udp_data_length - 1)
+												next_state <= VERIFY_CHECKSUM ;
+											else
+	                      next_state <= REC_DATA ;
+										end
+	 REC_ODD_DATA   : begin
+	                    if (ip_checksum_error)
+												next_state <= REC_ERROR ;
+											else if (udp_rx_cnt == udp_data_length - 1)
+												next_state <= VERIFY_CHECKSUM ;
+											else
+	                      next_state <= REC_ODD_DATA ;
+										end
+	 VERIFY_CHECKSUM :begin
+                      if (udp_checksum_error)
+												next_state <= REC_ERROR ;
+											else if (verify_end)
+												next_state <= REC_END_WAIT ;
+											else if (udp_rx_cnt == 16'hffff)
+												next_state <= IDLE ;
+											else
+												next_state <= VERIFY_CHECKSUM ;
+										end
+	 REC_ERROR      : next_state <= IDLE  ; 
+	 REC_END_WAIT   : begin
+	                    if (udp_rx_cnt == 16'd63)
+                            next_state <= REC_END ;
+                        else
+	                      next_state <= REC_END_WAIT ;
+                       end
+	 REC_END        : next_state <= IDLE  ;
+	 default        : next_state <= IDLE  ;
+	 endcase
+end
+
+
+
+
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+    ram_wr_en <= 1'b0 ;
+  else if ((state == REC_DATA || state == REC_ODD_DATA) && udp_rx_cnt < udp_data_length)
+    ram_wr_en <= 1'b1 ;
+  else
+    ram_wr_en <= 1'b0 ;
+end
+
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+    ram_write_addr <= 11'd0 ;
+  else if (state == REC_DATA || state == REC_ODD_DATA)
+    ram_write_addr <= udp_rx_cnt - 8 ;
+  else
+    ram_write_addr <= 11'd0 ;
+end
+//ip address check
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+	 ip_addr_check_error_d0 <= 1'b0 ;
+  else
+	 ip_addr_check_error_d0 <= ip_addr_check_error ;
+end
+//udp data length 
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+    udp_data_length <= 16'd0 ;
+  else if (state == IDLE)
+    udp_data_length <= upper_layer_data_length ;
+end
+
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+    udp_rec_data_length <= 16'd0 ;
+  else if (state == REC_END)
+    udp_rec_data_length <= udp_data_length ;
+end
+
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+    udp_rx_cnt <= 16'd0 ;
+  else if (state == REC_HEAD || state == REC_DATA  || state == REC_END_WAIT)
+    udp_rx_cnt <= udp_rx_cnt + 1'b1 ;
+  else
+    udp_rx_cnt <= 16'd0 ;
+end
+
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+     udp_rx_data_d0 <= 8'd0 ;
+  else
+     udp_rx_data_d0 <= udp_rx_data ;
+end
+	  
+
+udp_rx_ram_8_2048 udp_receive_ram
+(	
+    .clka(clk),    // input wire clka
+    .wea(ram_wr_en),      // input wire [0 : 0] wea
+    .addra(ram_write_addr),  // input wire [10 : 0] addra
+    .dina(udp_rx_data_d0),    // input wire [7 : 0] dina
+    .clkb(clk),    // input wire clkb
+    .addrb(udp_rec_ram_read_addr),  // input wire [10 : 0] addrb
+    .doutb(udp_rec_ram_rdata)  // output wire [7 : 0] doutb
+	); 
+
+//****************************************************************//
+//verify checksum
+//****************************************************************//
+reg  [16:0] checksum_tmp0 ;
+reg  [16:0] checksum_tmp1 ;
+reg  [16:0] checksum_tmp2 ;
+reg  [17:0] checksum_tmp3 ;
+reg  [18:0] checksum_tmp4 ;
+reg  [31:0] checksum_tmp5 ;
+reg  [31:0] checksum_buf ;
+reg  [31:0] check_out ;
+reg  [31:0] checkout_buf ;
+wire [15:0] checksum ;
+reg  [2:0]  checksum_cnt ;
+
+//checksum function 
+function    [31:0]  checksum_adder
+(
+ input       [31:0]  dataina,
+ input       [31:0]  datainb
+);
+
+begin
+    checksum_adder = dataina + datainb;
+end   
+endfunction 
+
+function    [31:0]  checksum_out
+(
+ input       [31:0]  dataina
+);
+
+begin
+    checksum_out = dataina[15:0]+dataina[31:16];
+end  
+ 
+endfunction 
+
+always @(posedge clk or negedge rst_n)
+begin
+    if(rst_n == 1'b0)
+    begin
+			checksum_tmp0 <= 17'd0 ; 
+			checksum_tmp1 <= 17'd0 ;
+			checksum_tmp2 <= 17'd0 ;
+			checksum_tmp3 <= 18'd0 ;
+			checksum_tmp4 <= 19'd0 ; 
+    end		
+    else if (state == REC_HEAD)
+    begin
+      checksum_tmp0 <= checksum_adder(ip_rec_source_addr[31:16],ip_rec_source_addr[15:0]);  //source ip address
+      checksum_tmp1 <= checksum_adder(ip_rec_destination_addr[31:16],ip_rec_destination_addr[15:0]);     //destination ip address
+      checksum_tmp2 <= checksum_adder({8'd0,net_protocol},udp_data_length);                   //protocol type
+			checksum_tmp3 <= checksum_adder(checksum_tmp0,checksum_tmp1);                   //protocol type
+      checksum_tmp4 <= checksum_adder(checksum_tmp2,checksum_tmp3);
+	 end
+	 else if (state == IDLE)
+	 begin
+			checksum_tmp0 <= 17'd0 ; 
+			checksum_tmp1 <= 17'd0 ;
+			checksum_tmp2 <= 17'd0 ;
+			checksum_tmp3 <= 18'd0 ;
+			checksum_tmp4 <= 19'd0 ; 
+    end	
+end
+
+always @(posedge clk or negedge rst_n)
+begin
+  if(rst_n == 1'b0)
+      checksum_tmp5 <= 32'd0; 
+  else if (state == REC_HEAD || state == REC_DATA)     
+  begin
+     if (udp_rx_cnt[0] == 1'b1)
+      checksum_tmp5 <= checksum_adder({udp_rx_data_d0,udp_rx_data},checksum_buf);	
+  end		
+  else if (state == REC_ODD_DATA)
+      checksum_tmp5 <= checksum_adder({udp_rx_data,8'h00},checksum_tmp5);   //if udp data length is odd, fill with one byte 8'h00
+  else if (state == IDLE)
+			checksum_tmp5 <= 32'd0 ;
+end
+
+always @(posedge clk or negedge rst_n)
+begin
+  if(rst_n == 1'b0)
+      checksum_cnt <= 3'd0 ; 
+  else if (state == 	VERIFY_CHECKSUM)	
+	   checksum_cnt <= checksum_cnt + 1'b1 ;
+  else
+	   checksum_cnt <= 3'd0 ;	
+end
+
+always @(posedge clk or negedge rst_n)
+begin
+  if(rst_n == 1'b0)
+      check_out <= 32'd0; 
+  else if (state == 	VERIFY_CHECKSUM)	
+  begin  
+	 if(checksum_cnt == 3'd0)
+	   check_out <= checksum_adder(checksum_tmp4, checksum_tmp5);
+	 else if (checksum_cnt == 3'd1)
+	   check_out <= checksum_out(check_out) ;
+	 else if (checksum_cnt == 3'd2)
+	   check_out <= checksum_out(check_out) ;	
+  end
+end
+
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+    checksum_buf <= 32'd0 ;
+  else if (state == REC_HEAD || state == REC_DATA)
+    checksum_buf <= checksum_tmp5 ;
+  else
+    checksum_buf <= 32'd0 ;
+end
+
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+    checkout_buf <= 32'd0 ;
+  else if (state == 	VERIFY_CHECKSUM)	
+    checkout_buf <= check_out ;
+  else
+    checkout_buf <= 32'd0 ;
+end
+
+assign checksum = ~checkout_buf[15:0] ;
+//**************************************************//
+//generate udp rx end
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+  begin
+    udp_checksum_error <= 1'b0 ;
+		verify_end <= 1'b0 ;
+  end
+  else if (state == VERIFY_CHECKSUM && checksum_cnt == 3'd4)
+  begin
+    if (checksum == 16'd0)	 
+	 begin
+      udp_checksum_error <= 1'b0 ;
+			verify_end <= 1'b1 ;
+    end
+	 else
+	 begin
+	   udp_checksum_error <= 1'b1 ;
+		 verify_end <= 1'b0 ;
+	 end
+  end
+  else
+  begin
+    udp_checksum_error <= 1'b0 ;
+		verify_end <= 1'b0 ;
+  end
+end 
+
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+    udp_rec_data_valid <= 1'b0 ;
+	else if (state == REC_END_WAIT)
+		udp_rec_data_valid <= 1'b0 ;
+  else if (state == REC_END)
+  begin
+    if (mac_rec_error)
+      udp_rec_data_valid <= 1'b0 ;
+	 else 
+      udp_rec_data_valid <= 1'b1 ;
+  end
+end
+
+	
+endmodule

rtl/ethernet-udp/src/eth/mac/tx/arp_tx.v

@@ -0,0 +1,306 @@
+//////////////////////////////////////////////////////////////////////////////////////
+//Module Name : arp_tx
+//Description : This module is used to send arp data when request arp or reply arp
+//
+//////////////////////////////////////////////////////////////////////////////////////
+`timescale 1 ns/1 ns
+module arp_tx
+       (
+          input                clk                    ,
+          input                rst_n                  ,
+          
+          input  [47:0]        destination_mac_addr   , //destination mac address
+          input  [47:0]        source_mac_addr        , //source mac address
+          input  [31:0]        source_ip_addr         , //source ip address
+          input  [31:0]        destination_ip_addr    , //destination ip address
+          
+          input                mac_data_req,            //mac layer request data
+          input                arp_request_req,         //arp request
+          output reg           arp_reply_ack,           //arp reply ack to arp rx module
+          input                arp_reply_req,           //arp reply request from arp rx module
+          output reg           arp_tx_req,
+          input  [31:0]        arp_rec_source_ip_addr,
+          input  [47:0]        arp_rec_source_mac_addr ,
+          input                mac_send_end,
+          input                mac_tx_ack,
+          
+          output reg           arp_tx_ready,
+          output reg [7:0]     arp_tx_data,
+          output reg           arp_tx_end
+       ) ;
+       
+localparam mac_type         = 16'h0806 ;
+localparam hardware_type    = 16'h0001 ;
+localparam protocol_type    = 16'h0800 ;
+localparam mac_length       = 8'h06    ;
+localparam ip_length        = 8'h04    ;
+
+localparam ARP_REQUEST_CODE = 16'h0001 ;
+localparam ARP_REPLY_CODE   = 16'h0002 ;
+
+
+reg  [15:0]        op ;
+
+reg  [31:0]        arp_destination_ip_addr ;
+reg  [47:0]        arp_destination_mac_addr  ;
+reg  [15:0]        arp_send_cnt ;
+reg  [15:0]        timeout ;
+reg                mac_send_end_d0 ;
+
+parameter IDLE               = 8'b00000001 ;
+parameter ARP_REQUEST_WAIT_0 = 8'b00000010 ;
+parameter ARP_REQUEST_WAIT_1 = 8'b00000100 ;
+parameter ARP_REQUEST        = 8'b00001000 ;
+parameter ARP_REPLY_WAIT_0   = 8'b00010000 ;
+parameter ARP_REPLY_WAIT_1   = 8'b00100000 ;
+parameter ARP_REPLY          = 8'b01000000 ;
+parameter ARP_END            = 8'b10000000 ;
+
+reg [7:0]    state  ;
+reg [7:0]    next_state ;
+
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      state  <=  IDLE  ;
+    else
+      state  <= next_state ;
+  end
+  
+always @(*)
+  begin
+    case(state)
+      IDLE             :
+        begin
+          if (arp_request_req)
+            next_state <= ARP_REQUEST_WAIT_0 ;
+          else if (arp_reply_req)
+            next_state <= ARP_REPLY_WAIT_0  ;
+          else
+            next_state <= IDLE ;
+        end
+	  ARP_REQUEST_WAIT_0 :
+        begin
+          if (mac_tx_ack)
+            next_state <= ARP_REQUEST_WAIT_1     ;
+          else
+            next_state <= ARP_REQUEST_WAIT_0 ;
+        end
+      ARP_REQUEST_WAIT_1 :
+        begin
+          if (mac_data_req)
+            next_state <= ARP_REQUEST     ;
+          else if (timeout == 16'hffff)
+            next_state <= IDLE ;
+          else
+            next_state <= ARP_REQUEST_WAIT_1 ;
+        end
+      ARP_REQUEST      :
+        begin
+          if (arp_tx_end)
+            next_state <= ARP_END     ;
+          else
+            next_state <= ARP_REQUEST ;
+        end
+	  ARP_REPLY_WAIT_0   :
+        begin
+          if (mac_tx_ack)
+            next_state <= ARP_REPLY_WAIT_1     ;
+          else
+            next_state <= ARP_REPLY_WAIT_0 ;
+        end
+      ARP_REPLY_WAIT_1   :
+        begin
+          if (mac_data_req)
+            next_state <= ARP_REPLY     ;
+          else if (timeout == 16'hffff)
+            next_state <= IDLE ;
+          else
+            next_state <= ARP_REPLY_WAIT_1 ;
+        end
+      ARP_REPLY        :
+        begin
+          if (arp_tx_end)
+            next_state <= ARP_END ;
+          else
+            next_state <= ARP_REPLY ;
+        end
+	  ARP_END :
+		  begin
+          if (mac_send_end_d0)
+            next_state <= IDLE ;
+          else
+            next_state <= ARP_END ;
+        end
+      default          :
+        next_state <= IDLE ;
+    endcase
+  end
+ 
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      mac_send_end_d0 <= 1'b0 ;
+    else 
+      mac_send_end_d0 <= mac_send_end ;
+  end  
+ 
+ always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      arp_tx_req <= 1'b0 ;
+    else if (state == ARP_REQUEST_WAIT_0 || state == ARP_REPLY_WAIT_0)
+      arp_tx_req <= 1'b1  ;
+    else
+      arp_tx_req <= 1'b0 ;
+  end 
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      op <= 16'd0 ;
+    else if (state == ARP_REPLY)
+      op <= ARP_REPLY_CODE  ;
+    else
+      op <= ARP_REQUEST_CODE ;
+  end
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      arp_tx_ready <= 1'b0 ;
+    else if (state == ARP_REQUEST_WAIT_1 || state == ARP_REPLY_WAIT_1)
+      arp_tx_ready <= 1'b1 ;
+    else
+      arp_tx_ready <= 1'b0 ;
+  end
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      arp_tx_end <= 1'b0 ;
+    else if ((state == ARP_REQUEST && arp_send_cnt == 13 + 46 ) || (state == ARP_REPLY && arp_send_cnt == 13 + 46 ))
+      arp_tx_end <= 1'b1 ;
+    else
+      arp_tx_end <= 1'b0 ;
+  end
+  
+  
+//timeout counter
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      timeout <= 16'd0 ;
+    else if (state == ARP_REQUEST_WAIT_1 || state == ARP_REPLY_WAIT_1)
+      timeout <= timeout + 1'b1 ;
+    else
+      timeout <= 16'd0 ;
+  end
+  
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      arp_destination_ip_addr  <=  32'd0  ;
+    else if (state == ARP_REQUEST_WAIT_1)
+      arp_destination_ip_addr  <= destination_ip_addr ;
+    else if (state == ARP_REPLY_WAIT_1)
+      arp_destination_ip_addr  <= arp_rec_source_ip_addr ;
+  end
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      arp_destination_mac_addr  <=  48'd0  ;
+    else if (state == ARP_REQUEST_WAIT_1)
+      arp_destination_mac_addr  <= destination_mac_addr ;
+    else if (state == ARP_REPLY_WAIT_1)
+      arp_destination_mac_addr  <= arp_rec_source_mac_addr ;
+  end
+  
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      arp_reply_ack  <=  1'b0 ;
+    else if (state == ARP_REPLY_WAIT_1)
+      arp_reply_ack  <= 1'b1 ;
+    else
+      arp_reply_ack  <=  1'b0 ;
+  end
+  
+  
+  
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      arp_send_cnt  <= 16'd0 ;
+    else if (state == ARP_REQUEST || state == ARP_REPLY)
+      arp_send_cnt <= arp_send_cnt + 1'b1 ;
+    else
+      arp_send_cnt <= 16'd0 ;
+  end
+  
+  
+  
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      arp_tx_data <= 8'd0 ;
+    else if(state == ARP_REQUEST || state == ARP_REPLY)
+      begin
+        case(arp_send_cnt)
+          16'd0   :  arp_tx_data <= arp_destination_mac_addr[47:40]   ;
+          16'd1   :  arp_tx_data <= arp_destination_mac_addr[39:32]   ;
+          16'd2   :  arp_tx_data <= arp_destination_mac_addr[31:24]   ;
+          16'd3   :  arp_tx_data <= arp_destination_mac_addr[23:16]   ;
+          16'd4   :  arp_tx_data <= arp_destination_mac_addr[15:8]    ;
+          16'd5   :  arp_tx_data <= arp_destination_mac_addr[7:0]     ;
+          16'd6   :  arp_tx_data <= source_mac_addr[47:40]            ;
+          16'd7   :  arp_tx_data <= source_mac_addr[39:32]            ;
+          16'd8   :  arp_tx_data <= source_mac_addr[31:24]            ;
+          16'd9   :  arp_tx_data <= source_mac_addr[23:16]            ;
+          16'd10  :  arp_tx_data <= source_mac_addr[15:8]             ;
+          16'd11  :  arp_tx_data <= source_mac_addr[7:0]              ;
+          16'd12  :  arp_tx_data <= mac_type[15:8]                    ;      //frame type
+          16'd13  :  arp_tx_data <= mac_type[7:0]                     ;
+          16'd14  :  arp_tx_data <= hardware_type[15:8]               ;      //hardware type
+          16'd15  :  arp_tx_data <= hardware_type[7:0]                ;
+          16'd16  :  arp_tx_data <= protocol_type[15:8]               ;      //protocol type using IP 0800
+          16'd17  :  arp_tx_data <= protocol_type[7:0]                ;
+          16'd18  :  arp_tx_data <= mac_length                        ;      //MAC address length
+          16'd19  :  arp_tx_data <= ip_length                         ;      //IP address length
+          16'd20  :  arp_tx_data <= op[15:8]                          ;
+          16'd21  :  arp_tx_data <= op[7:0]                           ;
+          16'd22  :  arp_tx_data <= source_mac_addr[47:40]            ;
+          16'd23  :  arp_tx_data <= source_mac_addr[39:32]            ;
+          16'd24  :  arp_tx_data <= source_mac_addr[31:24]            ;
+          16'd25  :  arp_tx_data <= source_mac_addr[23:16]            ;
+          16'd26  :  arp_tx_data <= source_mac_addr[15:8]             ;
+          16'd27  :  arp_tx_data <= source_mac_addr[7:0]              ;
+          16'd28  :  arp_tx_data <= source_ip_addr[31:24]             ;
+          16'd29  :  arp_tx_data <= source_ip_addr[23:16]             ;
+          16'd30  :  arp_tx_data <= source_ip_addr[15:8]              ;
+          16'd31  :  arp_tx_data <= source_ip_addr[7:0]               ;
+          16'd32  :  arp_tx_data <= arp_destination_mac_addr[47:40]   ;
+          16'd33  :  arp_tx_data <= arp_destination_mac_addr[39:32]   ;
+          16'd34  :  arp_tx_data <= arp_destination_mac_addr[31:24]   ;
+          16'd35  :  arp_tx_data <= arp_destination_mac_addr[23:16]   ;
+          16'd36  :  arp_tx_data <= arp_destination_mac_addr[15:8]    ;
+          16'd37  :  arp_tx_data <= arp_destination_mac_addr[7:0]     ;
+          16'd38  :  arp_tx_data <= arp_destination_ip_addr[31:24]    ;
+          16'd39  :  arp_tx_data <= arp_destination_ip_addr[23:16]    ;
+          16'd40  :  arp_tx_data <= arp_destination_ip_addr[15:8]     ;
+          16'd41  :  arp_tx_data <= arp_destination_ip_addr[7:0]      ;
+          default :  arp_tx_data <= 8'd0                              ;
+        endcase
+      end
+    else
+      arp_tx_data  <= 8'd0 ;
+  end
+  
+  
+  
+endmodule

rtl/ethernet-udp/src/eth/mac/tx/ip_tx.v

@@ -0,0 +1,400 @@
+//////////////////////////////////////////////////////////////////////////////////////
+//Module Name : ip_tx
+//Description : This module is used to send ip layer data, generate ip header checksum,
+//              receive data from udp or icmp, then send to mac layer
+//
+//
+//////////////////////////////////////////////////////////////////////////////////////
+`timescale 1 ns/1 ns
+module ip_tx
+       (
+         input                clk                    ,
+         input                rst_n                  ,
+         
+         input  [47:0]        destination_mac_addr   ,  //destination mac address
+         input  [47:0]        source_mac_addr        ,  //source mac address
+         input  [7:0]         TTL,
+         input  [7:0]         ip_send_type,
+         input  [31:0]        source_ip_addr,
+         input  [31:0]        destination_ip_addr,
+         input  [7:0]         upper_layer_data,         //data from udp or icmp
+         output reg           upper_data_req,        //request data from udp or icmp
+         
+         input                mac_tx_ack,
+         input                mac_send_end,
+         input                mac_data_req,
+         input                upper_tx_ready,
+         input                ip_tx_req,
+         input  [15:0]        ip_send_data_length ,
+         
+         output reg           ip_tx_ack,
+         output               ip_tx_busy,
+         output reg           ip_tx_ready,
+         output reg [7:0]     ip_tx_data,
+         output reg           ip_tx_end
+       ) ;
+       
+localparam mac_type      = 16'h0800 ;
+localparam ip_version    = 4'h4     ;  //ipv4
+localparam header_len    = 4'h5     ;  //header length
+
+reg            checksum_finish ;
+reg  [15:0]    identify_code ;
+reg  [15:0]    ip_send_data_length_d0 ;
+reg  [15:0]    ip_send_cnt ;
+reg  [15:0]    timeout ;
+reg  [3:0]     wait_cnt ;
+reg            mac_send_end_d0 ;
+
+parameter IDLE             = 8'b0000_0001 ;
+parameter START            = 8'b0000_0010 ;
+parameter WAIT_DATA_LENGTH = 8'b0000_0100 ;
+parameter GEN_CHECKSUM     = 8'b0000_1000 ;
+parameter SEND_WAIT        = 8'b0001_0000 ;
+parameter WAIT_MAC         = 8'b0010_0000 ;
+parameter IP_SEND          = 8'b0100_0000 ;
+parameter IP_END           = 8'b1000_0000 ;
+
+reg [7:0]    state  ;
+reg [7:0]    next_state ;
+
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      state  <=  IDLE  ;
+    else
+      state  <= next_state ;
+  end
+  
+always @(*)
+  begin
+    case(state)
+      IDLE            :
+        begin
+          if (ip_tx_req)
+            next_state <= START ;
+          else
+            next_state <= IDLE ;
+        end
+      START            :
+        begin
+          if (mac_tx_ack)
+            next_state <= WAIT_DATA_LENGTH ;
+          else
+            next_state <= START ;
+        end  
+      WAIT_DATA_LENGTH   :
+        begin
+          if (wait_cnt == 4'd7)
+            next_state <= GEN_CHECKSUM ;
+          else
+            next_state <= WAIT_DATA_LENGTH ;
+        end
+      GEN_CHECKSUM     :
+        begin
+          if (checksum_finish)
+            next_state <= SEND_WAIT ;
+          else
+            next_state <= GEN_CHECKSUM ;
+        end
+        
+      SEND_WAIT       :
+        begin
+          if (upper_tx_ready)
+            next_state <= WAIT_MAC ;
+          else if (timeout == 16'hffff)
+            next_state <= IDLE ;
+          else
+            next_state <= SEND_WAIT ;
+        end
+      WAIT_MAC         :
+        begin
+          if (mac_data_req)
+            next_state <= IP_SEND ;
+          else if (timeout == 16'hffff)
+            next_state <= IDLE ;
+          else
+            next_state <= WAIT_MAC ;
+        end
+      IP_SEND         :
+        begin
+          if (ip_send_cnt == 14 + ip_send_data_length_d0)
+            next_state <= IP_END ;
+          else
+            next_state <= IP_SEND ;
+        end
+	  IP_END         :
+        begin
+          if (mac_send_end_d0)
+            next_state <= IDLE ;
+          else
+            next_state <= IP_END ;
+        end
+      default          :
+        next_state <= IDLE ;
+    endcase
+  end
+ 
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      mac_send_end_d0 <= 1'b0 ;
+    else 
+      mac_send_end_d0 <= mac_send_end ;
+  end  
+ 
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      ip_tx_ack <= 1'b0 ;
+    else if (state == WAIT_DATA_LENGTH)
+      ip_tx_ack <= 1'b1 ;
+    else
+      ip_tx_ack <= 1'b0 ;
+  end  
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      ip_tx_ready <= 1'b0 ;
+    else if (state == WAIT_MAC)
+      ip_tx_ready <= upper_tx_ready ;
+    else
+      ip_tx_ready <= 1'b0 ;
+  end
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      ip_tx_end <= 1'b0 ;
+    else if ((state == IP_SEND) && (ip_send_cnt == 13 + ip_send_data_length_d0))
+      ip_tx_end <= 1'b1 ;
+    else
+      ip_tx_end <= 1'b0 ;
+  end
+  
+//request data from icmp or udp
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      upper_data_req <= 1'b0 ;
+    else if (state == IP_SEND && ip_send_cnt == 16'd30)
+      upper_data_req <= 1'b1 ;
+    else
+      upper_data_req <= 1'b0 ;
+  end
+  
+//timeout counter
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      timeout <= 16'd0 ;
+    else if (upper_tx_ready)
+      timeout <= 16'd0 ;
+    else if (state == SEND_WAIT || state == WAIT_MAC)
+      timeout <= timeout + 1'b1 ;
+    else
+      timeout <= 16'd0 ;
+  end
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      wait_cnt <= 4'd0 ;
+    else if (state == WAIT_DATA_LENGTH)
+      wait_cnt <= wait_cnt + 1'b1 ;
+    else
+      wait_cnt <= 4'd0 ;
+  end
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      identify_code  <= 16'd0 ;
+    else if (ip_tx_end)
+      identify_code  <= identify_code + 1'b1 ;
+  end
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      ip_send_data_length_d0  <= 16'd0 ;
+    else
+      begin
+        if (ip_send_data_length < 46)
+          ip_send_data_length_d0  <= 16'd46 ;
+        else
+          ip_send_data_length_d0  <= ip_send_data_length ;
+      end
+  end
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      ip_send_cnt  <= 16'd0 ;
+    else if (state == GEN_CHECKSUM || state == IP_SEND)
+      ip_send_cnt <= ip_send_cnt + 1'b1 ;
+    else
+      ip_send_cnt <= 16'd0 ;
+  end
+//checksum generation
+
+reg  [16:0] checksum_tmp0 ;
+reg  [16:0] checksum_tmp1 ;
+reg  [16:0] checksum_tmp2 ;
+reg  [16:0] checksum_tmp3 ;
+reg  [16:0] checksum_tmp4 ;
+reg  [17:0] checksum_tmp5 ;
+reg  [17:0] checksum_tmp6 ;
+reg  [18:0] checksum_tmp7 ;
+reg  [19:0] checksum_tmp8 ;
+reg  [19:0] check_out ;
+reg  [19:0] checkout_buf ;
+reg  [15:0] checksum ;
+
+
+//checksum function
+function    [31:0]  checksum_adder
+  (
+    input       [31:0]  dataina,
+    input       [31:0]  datainb
+  );
+  
+  begin
+    checksum_adder = dataina + datainb;
+  end
+endfunction
+
+function    [31:0]  checksum_out
+  (
+    input       [31:0]  dataina
+  );
+  
+  begin
+    checksum_out = dataina[15:0]+dataina[31:16];
+  end
+  
+endfunction
+
+
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      begin
+        checksum_tmp0 <= 17'd0 ;
+        checksum_tmp1 <= 17'd0 ;
+        checksum_tmp2 <= 17'd0 ;
+        checksum_tmp3 <= 17'd0 ;
+        checksum_tmp4 <= 17'd0 ;
+        checksum_tmp5 <= 18'd0 ;
+        checksum_tmp6 <= 18'd0 ;
+        checksum_tmp7 <= 19'd0 ;
+        checksum_tmp8 <= 20'd0 ;
+        check_out     <= 20'd0 ;
+        checkout_buf  <= 20'd0 ;
+      end
+    else if (state == GEN_CHECKSUM)
+      begin
+        checksum_tmp0 <= checksum_adder(16'h4500,ip_send_data_length);
+        checksum_tmp1 <= checksum_adder(identify_code, 16'h4000) ;
+        checksum_tmp2 <= checksum_adder({TTL,ip_send_type}, 16'h0000) ;
+        checksum_tmp3 <= checksum_adder(source_ip_addr[31:16], source_ip_addr[15:0]) ;
+        checksum_tmp4 <= checksum_adder(destination_ip_addr[31:16], destination_ip_addr[15:0]) ;
+        checksum_tmp5 <= checksum_adder(checksum_tmp0, checksum_tmp1) ;
+        checksum_tmp6 <= checksum_adder(checksum_tmp2, checksum_tmp3) ;
+        checksum_tmp7 <= checksum_adder(checksum_tmp5, checksum_tmp6) ;
+        checksum_tmp8 <= checksum_adder(checksum_tmp4, checksum_tmp7) ;
+        check_out     <= checksum_out(checksum_tmp8) ;
+        checkout_buf  <= checksum_out(check_out) ;
+      end
+    else if (state == IDLE)
+      begin
+        checksum_tmp0 <= 17'd0 ;
+        checksum_tmp1 <= 17'd0 ;
+        checksum_tmp2 <= 17'd0 ;
+        checksum_tmp3 <= 17'd0 ;
+        checksum_tmp4 <= 17'd0 ;
+        checksum_tmp5 <= 18'd0 ;
+        checksum_tmp6 <= 18'd0 ;
+        checksum_tmp7 <= 19'd0 ;
+        checksum_tmp8 <= 20'd0 ;
+        check_out     <= 20'd0 ;
+        checkout_buf  <= 20'd0 ;
+      end
+  end
+  
+  
+  
+  
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      checksum <= 32'd0 ;
+    else if (state == GEN_CHECKSUM)
+      checksum <= ~checkout_buf[15:0] ;
+  end
+//assign checksum = ~checkout_buf[15:0] ;
+//*******************************************************//
+
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      checksum_finish <= 1'b0 ;
+    else if (state == GEN_CHECKSUM && ip_send_cnt == 16'd13)
+      checksum_finish <= 1'b1 ;
+    else
+      checksum_finish <= 1'b0 ;
+  end
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      ip_tx_data <= 8'h00 ;
+    else if (state == IP_SEND)
+      begin
+        case(ip_send_cnt)
+          16'd0   :  ip_tx_data <= destination_mac_addr[47:40]  ;
+          16'd1   :  ip_tx_data <= destination_mac_addr[39:32]  ;
+          16'd2   :  ip_tx_data <= destination_mac_addr[31:24]  ;
+          16'd3   :  ip_tx_data <= destination_mac_addr[23:16]  ;
+          16'd4   :  ip_tx_data <= destination_mac_addr[15:8]   ;
+          16'd5   :  ip_tx_data <= destination_mac_addr[7:0]    ;
+          16'd6   :  ip_tx_data <= source_mac_addr[47:40]       ;
+          16'd7   :  ip_tx_data <= source_mac_addr[39:32]       ;
+          16'd8   :  ip_tx_data <= source_mac_addr[31:24]       ;
+          16'd9   :  ip_tx_data <= source_mac_addr[23:16]       ;
+          16'd10  :  ip_tx_data <= source_mac_addr[15:8]        ;
+          16'd11  :  ip_tx_data <= source_mac_addr[7:0]         ;
+          16'd12  :  ip_tx_data <= mac_type[15:8]               ;
+          16'd13  :  ip_tx_data <= mac_type[7:0]                ;
+          16'd14  :  ip_tx_data <= {ip_version, header_len}     ;
+          16'd15  :  ip_tx_data <= 8'h00                        ;
+          16'd16  :  ip_tx_data <= ip_send_data_length[15:8]    ;
+          16'd17  :  ip_tx_data <= ip_send_data_length[7:0]     ;
+          16'd18  :  ip_tx_data <= identify_code[15:8]          ;
+          16'd19  :  ip_tx_data <= identify_code[7:0]           ;
+          16'd20  :  ip_tx_data <= 8'h40                        ;
+          16'd21  :  ip_tx_data <= 8'h00                        ;
+          16'd22  :  ip_tx_data <= TTL                          ;
+          16'd23  :  ip_tx_data <= ip_send_type                 ;
+          16'd24  :  ip_tx_data <= checksum[15:8]               ;
+          16'd25  :  ip_tx_data <= checksum[7:0]                ;
+          16'd26  :  ip_tx_data <= source_ip_addr[31:24]        ;
+          16'd27  :  ip_tx_data <= source_ip_addr[23:16]        ;
+          16'd28  :  ip_tx_data <= source_ip_addr[15:8]         ;
+          16'd29  :  ip_tx_data <= source_ip_addr[7:0]          ;
+          16'd30  :  ip_tx_data <= destination_ip_addr[31:24]   ;
+          16'd31  :  ip_tx_data <= destination_ip_addr[23:16]   ;
+          16'd32  :  ip_tx_data <= destination_ip_addr[15:8]    ;
+          16'd33  :  ip_tx_data <= destination_ip_addr[7:0]     ;
+          default :  ip_tx_data <= upper_layer_data             ;
+        endcase
+      end
+    else
+      ip_tx_data  <= 8'h00 ;
+  end
+  
+  
+  
+endmodule

rtl/ethernet-udp/src/eth/mac/tx/ip_tx_mode.v

@@ -0,0 +1,194 @@
+//////////////////////////////////////////////////////////////////////////////////////
+//Module Name : ip_tx_mode
+//Description : This module is arbitration for ip layer signal, which from udp and icmp
+//
+//////////////////////////////////////////////////////////////////////////////////////
+`timescale 1 ns/1 ns
+module ip_tx_mode
+       (
+         input                    clk ,
+         input                    rst_n,
+         input                    mac_send_end,
+         
+         
+         input                    udp_tx_req,
+         input                    udp_tx_ready ,
+         input      [7:0]         udp_tx_data,
+         input      [15:0]        udp_send_data_length,
+         output reg               udp_tx_ack,
+         
+         input                    icmp_tx_req,
+         input                    icmp_tx_ready,
+         input      [7:0]         icmp_tx_data,
+         input      [15:0]        icmp_send_data_length,
+         output reg               icmp_tx_ack,
+         
+         input                    ip_tx_ack,
+         output reg               ip_tx_req,
+         output reg               ip_tx_ready,
+         output reg [7:0]         ip_tx_data,
+         output reg [7:0]         ip_send_type,
+         output reg [15:0]        ip_send_data_length
+         
+         
+       );
+       
+localparam ip_udp_type  = 8'h11 ;
+localparam ip_icmp_type = 8'h01 ;
+
+reg [15:0]    timeout ;
+
+parameter IDLE      = 5'b00001 ;
+parameter UDP_WAIT  = 5'b00010 ;
+parameter UDP       = 5'b00100 ;
+parameter ICMP_WAIT = 5'b01000 ;
+parameter ICMP      = 5'b10000 ;
+
+
+reg [4:0]    state  ;
+reg [4:0]    next_state ;
+
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      state  <=  IDLE  ;
+    else
+      state  <= next_state ;
+  end
+  
+always @(*)
+  begin
+    case(state)
+      IDLE        :
+        begin
+          if (udp_tx_req)
+            next_state <= UDP_WAIT ;
+          else if (icmp_tx_req)
+            next_state <= ICMP_WAIT  ;
+          else
+            next_state <= IDLE ;
+        end
+      UDP_WAIT    :
+        begin
+		  if (ip_tx_ack)
+		    next_state <= UDP ;
+		  else
+		    next_state <= UDP_WAIT ;
+        end		
+      UDP         :
+        begin
+          if (mac_send_end)
+            next_state <= IDLE ;
+          else if (timeout == 16'hffff)
+            next_state <= IDLE ;
+          else
+            next_state <= UDP ;
+        end
+	  ICMP_WAIT    :
+        begin
+		  if (ip_tx_ack)
+		    next_state <= ICMP ;
+		  else
+		    next_state <= ICMP_WAIT ;
+        end	
+      ICMP        :
+        begin
+          if (mac_send_end)
+            next_state <= IDLE ;
+          else if (timeout == 16'hffff)
+            next_state <= IDLE ;
+          else
+            next_state <= ICMP ;
+        end
+      default     :
+        next_state <= IDLE ;
+    endcase
+  end
+  
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      timeout <= 16'd0 ;
+    else if (state == UDP || state == ICMP)
+      timeout <= timeout + 1'b1 ;
+    else
+      timeout <= 16'd0 ;
+  end
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      ip_send_data_length <= 16'd0 ;
+    else if (state == ICMP_WAIT || state == ICMP)
+      ip_send_data_length <= icmp_send_data_length ;
+    else
+      ip_send_data_length <= udp_send_data_length + 28 ;
+  end
+
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      ip_tx_req  <= 1'b0  ;
+    else if (state == UDP_WAIT || state == ICMP_WAIT)
+	  ip_tx_req  <= 1'b1  ;
+    else 
+	  ip_tx_req  <= 1'b0  ;
+  end
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      udp_tx_ack  <= 1'b0  ;
+    else if (state == UDP)
+	  udp_tx_ack  <= 1'b1  ;
+    else 
+	  udp_tx_ack  <= 1'b0  ;
+  end
+
+ 
+ always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      icmp_tx_ack  <= 1'b0  ;
+    else if (state == ICMP)
+	  icmp_tx_ack  <= 1'b1  ;
+    else 
+	  icmp_tx_ack  <= 1'b0  ;
+  end
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      begin
+        ip_tx_ready       <= 1'b0 ;
+        ip_tx_data        <= 8'h00 ;
+        ip_send_type      <= ip_udp_type ;
+      end
+    else if (state == UDP)
+      begin
+        ip_tx_ready       <= udp_tx_ready ;
+        ip_tx_data        <= udp_tx_data ;
+        ip_send_type      <= ip_udp_type ;
+        
+      end
+    else if (state == ICMP)
+      begin
+        ip_tx_ready       <= icmp_tx_ready ;
+        ip_tx_data        <= icmp_tx_data ;
+        ip_send_type      <= ip_icmp_type ;
+        
+      end
+    else
+      begin
+        ip_tx_ready       <= 1'b0 ;
+        ip_tx_data        <= 8'h00 ;
+        ip_send_type      <= ip_udp_type ;
+      end
+  end
+  
+  
+  
+endmodule
+
+

rtl/ethernet-udp/src/eth/mac/tx/mac_tx.v

@@ -0,0 +1,256 @@
+//////////////////////////////////////////////////////////////////////////////////////
+//Module Name : mac_tx
+//Description : This module is MAC layer module, which receive data from ARP or IP module,
+//              In this module, CRC checksum is generated
+//
+//////////////////////////////////////////////////////////////////////////////////////
+`timescale 1 ns/1 ns
+module mac_tx
+       (
+           input                  clk,
+           input                  rst_n,
+           
+           input      [31:0]      crc_result ,
+           output reg             crcen,
+           output reg             crcre,
+           output reg [7:0]       crc_din,
+           
+           input                  mac_tx_req,
+           input      [7:0]       mac_frame_data,  //data from ip or arp
+           input                  mac_tx_ready,    //ready from ip or arp
+           input                  mac_tx_end,      //end from ip or arp
+           
+           output reg             mac_tx_ack,
+           output reg [7:0]       mac_tx_data,
+           output reg             mac_send_end,
+           output reg             mac_data_valid,
+           output reg             mac_data_req     //request data from arp or ip
+         
+       ) ;
+       
+       
+reg  [3:0]          mac_tx_cnt    ;
+reg  [31:0]         crc ;
+
+reg  [7:0]          mac_frame_data_dly ;
+reg                 mac_tx_end_dly ;
+reg  [7:0]          mac_tx_data_tmp ;
+reg                 mac_data_valid_tmp ;
+reg  [15:0]         timeout ;
+
+
+//MAC send FSM
+parameter SEND_IDLE         =  6'b000_001  ;
+parameter SEND_START        =  6'b000_010  ;
+parameter SEND_PREAMBLE     =  6'b000_100  ;
+parameter SEND_DATA         =  6'b001_000  ;
+parameter SEND_CRC          =  6'b010_000  ;
+parameter SEND_END          =  6'b100_000  ;
+
+reg [5:0]     send_state      ;
+reg [5:0]     send_next_state ;
+
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      send_state <= SEND_START ;
+    else
+      send_state <= send_next_state ;
+  end
+  
+always @(*)
+  begin
+    case(send_state)
+      SEND_IDLE    :
+	    begin
+		  if (mac_tx_req)
+		    send_next_state <= SEND_START ;
+		  else
+		    send_next_state <= SEND_IDLE ;
+	    end
+      SEND_START     :
+        begin
+          if (mac_tx_ready)
+            send_next_state <= SEND_PREAMBLE ;
+          else
+            send_next_state <= SEND_START ;
+        end
+      SEND_PREAMBLE   :
+        begin
+          if (mac_tx_cnt == 7)
+            send_next_state <= SEND_DATA ;
+          else
+            send_next_state <= SEND_PREAMBLE ;
+        end
+      SEND_DATA       :
+        begin
+          if (mac_tx_end_dly)
+            send_next_state <= SEND_CRC ;
+          else if (timeout == 16'hffff)
+            send_next_state <= SEND_END ;
+          else
+            send_next_state <= SEND_DATA ;
+        end
+      SEND_CRC        :
+        begin
+          if (mac_tx_cnt == 4)
+            send_next_state <= SEND_END ;
+          else
+            send_next_state <= SEND_CRC ;
+        end
+      SEND_END        :
+        send_next_state <= SEND_IDLE  ;
+      default         :
+        send_next_state <= SEND_IDLE  ;
+    endcase
+  end
+  
+ always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      mac_tx_ack <= 1'b0 ;
+    else if (send_state == SEND_START)
+      mac_tx_ack <= 1'b1 ;
+    else
+      mac_tx_ack <= 1'b0 ;
+  end 
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      mac_send_end <= 1'b0 ;
+    else if (send_state == SEND_END)
+      mac_send_end <= 1'b1 ;
+    else
+      mac_send_end <= 1'b0 ;
+  end
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      begin
+        crcre   <= 1'b1 ;
+        crcen   <= 1'b0 ;
+        crc_din <= 8'd0 ;
+      end
+    else if (send_state == SEND_DATA || (send_state == SEND_PREAMBLE && mac_tx_cnt == 7))
+      begin
+        crcre   <= 1'b0 ;
+        crcen   <= 1'b1 ;
+        crc_din <= mac_frame_data ;
+      end
+    else
+      begin
+        crcre   <= 1'b1 ;
+        crcen   <= 1'b0 ;
+        crc_din <= 8'd0 ;
+      end
+  end
+  
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      mac_data_valid_tmp <= 1'b0 ;
+    else if (send_state == SEND_PREAMBLE || send_state == SEND_DATA || (send_state == SEND_CRC && mac_tx_cnt < 4))
+      mac_data_valid_tmp <= 1'b1 ;
+    else
+      mac_data_valid_tmp <= 1'b0 ;
+  end
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      mac_data_valid <= 1'b0 ;
+    else
+      mac_data_valid <= mac_data_valid_tmp ;
+  end
+//request data from arp or ip
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      mac_data_req <= 1'b0 ;
+    else if (send_state == SEND_PREAMBLE && mac_tx_cnt == 3)
+      mac_data_req <= 1'b1 ;
+    else
+      mac_data_req <= 1'b0 ;
+  end
+//timeout counter
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      timeout <= 16'd0 ;
+    else if (send_state == SEND_DATA)
+      timeout <= timeout + 1'b1 ;
+    else
+      timeout <= 16'd0 ;
+  end
+  
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      crc <= 32'hffffffff ;
+    else if (crcen)
+      crc <= crc_result ;
+  end
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      begin
+        mac_frame_data_dly <= 8'd0 ;
+        mac_tx_end_dly     <= 1'b0 ;
+      end
+    else
+      begin
+        mac_frame_data_dly <= mac_frame_data ;
+        mac_tx_end_dly     <= mac_tx_end ;
+      end
+  end
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      mac_tx_cnt <= 4'd0 ;
+    else if (send_state == SEND_PREAMBLE || send_state == SEND_CRC)
+      mac_tx_cnt <= mac_tx_cnt + 1'b1 ;
+    else
+      mac_tx_cnt <= 4'd0 ;
+  end
+//mac send data frame
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      mac_tx_data_tmp <= 8'h00 ;
+    else if (send_state == SEND_PREAMBLE)
+      begin
+        if (mac_tx_cnt < 7)
+          mac_tx_data_tmp <= 8'h55 ;
+        else
+          mac_tx_data_tmp <= 8'hd5 ;
+      end
+    else if (send_state == SEND_DATA)
+      mac_tx_data_tmp <= mac_frame_data_dly ;
+  end
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      mac_tx_data <= 8'h00 ;
+    else if (send_state == SEND_CRC)
+      begin
+        case(mac_tx_cnt)
+          4'd0    : mac_tx_data <= mac_tx_data_tmp ;
+          4'd1    : mac_tx_data <= {~crc[24], ~crc[25], ~crc[26], ~crc[27], ~crc[28], ~crc[29], ~crc[30], ~crc[31]} ;
+          4'd2    : mac_tx_data <= {~crc[16], ~crc[17], ~crc[18], ~crc[19], ~crc[20], ~crc[21], ~crc[22], ~crc[23]} ;
+          4'd3    : mac_tx_data <= {~crc[8], ~crc[9], ~crc[10], ~crc[11], ~crc[12], ~crc[13], ~crc[14], ~crc[15]}   ;
+          4'd4    : mac_tx_data <= {~crc[0], ~crc[1], ~crc[2], ~crc[3], ~crc[4], ~crc[5], ~crc[6], ~crc[7]}   ;
+          default : mac_tx_data <= 8'h00 ;
+        endcase
+      end
+    else
+      mac_tx_data <= mac_tx_data_tmp ;
+  end
+  
+endmodule

rtl/ethernet-udp/src/eth/mac/tx/mac_tx_mode.v

@@ -0,0 +1,174 @@
+//////////////////////////////////////////////////////////////////////////////////////
+//Module Name : mac_tx_mode
+//Description : This module is arbitration for MAC layer signal, which from IP and ARP
+//
+//////////////////////////////////////////////////////////////////////////////////////
+`timescale 1 ns/1 ns
+module mac_tx_mode
+       (
+         input               clk ,
+         input               rst_n,
+         input               mac_send_end,
+         
+         input               arp_tx_req,
+         input               arp_tx_ready ,
+         input      [7:0]    arp_tx_data,
+         input               arp_tx_end,
+         output reg          arp_tx_ack,
+         
+         input               ip_tx_req,
+         input               ip_tx_ready,
+         input      [7:0]    ip_tx_data,
+         input               ip_tx_end,
+         output reg          ip_tx_ack,
+         
+         input               mac_tx_ack,
+         output reg          mac_tx_req,		 
+         output reg          mac_tx_ready,
+         output reg [7:0]    mac_tx_data,
+         output reg          mac_tx_end
+       );
+       
+       
+       
+reg [15:0]    timeout ;
+
+parameter IDLE       = 5'b00001 ;
+parameter ARP_WAIT   = 5'b00010 ;
+parameter ARP        = 5'b00100 ;
+parameter IP_WAIT    = 5'b01000 ;
+parameter IP         = 5'b10000 ;
+
+
+reg [4:0]    state  ;
+reg [4:0]    next_state ;
+
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      state  <=  IDLE  ;
+    else
+      state  <= next_state ;
+  end
+  
+always @(*)
+  begin
+    case(state)
+      IDLE        :
+        begin
+          if (arp_tx_req)
+            next_state <= ARP_WAIT ;
+          else if (ip_tx_req)
+            next_state <= IP_WAIT  ;
+          else
+            next_state <= IDLE ;
+        end
+      ARP_WAIT  :
+        begin
+		  if (mac_tx_ack)
+		    next_state <= ARP ;
+		  else
+		    next_state <= IP ;
+        end		
+      ARP         :
+        begin
+          if (mac_send_end)
+            next_state <= IDLE ;
+          else if (timeout == 16'hffff)
+            next_state <= IDLE ;
+          else
+            next_state <= ARP ;
+        end
+	  IP_WAIT  :
+        begin
+		  if (mac_tx_ack)
+		    next_state <= IP ;
+		  else
+		    next_state <= IP_WAIT ;
+        end	
+      IP          :
+        begin
+          if (mac_send_end)
+            next_state <= IDLE ;
+          else if (timeout == 16'hffff)
+            next_state <= IDLE ;
+          else
+            next_state <= IP ;
+        end
+      default     :
+        next_state <= IDLE ;
+    endcase
+  end
+  
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      timeout <= 16'd0 ;
+    else if (state == ARP || state == IP)
+      timeout <= timeout + 1'b1 ;
+    else
+      timeout <= 16'd0 ;
+  end
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      arp_tx_ack <= 1'b0 ;
+    else if (state == ARP)
+      arp_tx_ack <= 1'b1 ;
+    else
+      arp_tx_ack <= 1'b0 ;
+  end  
+ 
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      ip_tx_ack <= 1'b0 ;
+    else if (state == IP)
+      ip_tx_ack <= 1'b1 ;
+    else
+      ip_tx_ack <= 1'b0 ;
+  end 
+
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      mac_tx_req <= 1'b0 ;
+    else if (state == ARP_WAIT || state == IP_WAIT)
+      mac_tx_req <= 1'b1 ;
+    else
+      mac_tx_req <= 1'b0 ;
+  end   
+
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      begin
+        mac_tx_ready      <= 1'b0  ;
+        mac_tx_data       <= 8'h00 ;
+        mac_tx_end        <= 1'b0  ;
+      end
+    else if (state == ARP)
+      begin
+        mac_tx_ready      <= arp_tx_ready ;
+        mac_tx_data       <= arp_tx_data ;
+        mac_tx_end        <= arp_tx_end ;
+      end
+    else if (state == IP)
+      begin
+        mac_tx_ready      <= ip_tx_ready ;
+        mac_tx_data       <= ip_tx_data ;
+        mac_tx_end        <= ip_tx_end ;
+      end
+    else
+      begin
+        mac_tx_ready      <= 1'b0  ;
+        mac_tx_data       <= 8'h00 ;
+        mac_tx_end        <= 1'b0  ;
+      end
+  end
+  
+endmodule
+
+

rtl/ethernet-udp/src/eth/mac/tx/mac_tx_top.v

@@ -0,0 +1,260 @@
+//////////////////////////////////////////////////////////////////////////////////////
+//Module Name : mac_tx_top
+//Description : MAC TX Top module
+//
+//////////////////////////////////////////////////////////////////////////////////////
+`timescale 1 ns/1 ns
+module mac_tx_top
+       (
+         input                clk                    ,
+         input                rst_n                  ,
+         
+         input  [47:0]        destination_mac_addr   , //destination mac address
+         input  [47:0]        source_mac_addr        ,       //source mac address
+         input  [7:0]         TTL,
+         input  [31:0]        source_ip_addr,
+         input  [31:0]        destination_ip_addr,
+         input  [15:0]        udp_send_source_port,
+         input  [15:0]        udp_send_destination_port,
+         
+         output               arp_reply_ack,
+         input                arp_reply_req,
+         input  [31:0]        arp_rec_source_ip_addr,
+         input  [47:0]        arp_rec_source_mac_addr,
+         input                arp_request_req,
+         
+         
+         (* MARK_DEBUG="true" *)input  [7:0]         ram_wr_data,
+         (* MARK_DEBUG="true" *)input                ram_wr_en,
+         (* MARK_DEBUG="true" *)input                udp_tx_req,
+         (* MARK_DEBUG="true" *)output               udp_ram_data_req,
+         (* MARK_DEBUG="true" *)input  [15:0]        udp_send_data_length,
+         (* MARK_DEBUG="true" *)output               udp_tx_end,
+         (* MARK_DEBUG="true" *)output               almost_full,
+         (* MARK_DEBUG="true" *)output [11:0]        udp_ram_data_count,
+         
+         (* MARK_DEBUG="true" *)output               upper_data_req,
+         input                icmp_tx_ready,
+         input  [7:0]         icmp_tx_data,
+         input                icmp_tx_end,
+         input                icmp_tx_req,
+         output               icmp_tx_ack,
+         input  [15:0]        icmp_send_data_length,
+         
+         (* MARK_DEBUG="true" *)output               mac_data_valid,
+         (* MARK_DEBUG="true" *)output               mac_send_end,
+         (* MARK_DEBUG="true" *)output [7:0]         mac_tx_data
+       ) ;
+       
+       
+wire                  crcen ;
+wire                  crcre ;
+wire [7:0]            crc_din ;
+wire [31:0]           crc_result ;
+
+wire                  mac_data_req ;
+wire [7:0]            mac_frame_data ;
+wire                  mac_tx_ready ;
+wire                  mac_tx_end ;
+
+wire                  ip_tx_ready ;
+wire [7:0]            ip_tx_data ;
+wire                  ip_tx_end ;
+
+wire                  arp_tx_ready ;
+wire [7:0]            arp_tx_data ;
+wire                  arp_tx_end ;
+
+
+wire [15:0]           ip_send_data_length ;
+
+
+wire [7:0]            udp_tx_data ;
+wire                  udp_data_req ;
+wire                  udp_tx_ready ;
+wire                  udp_tx_req_tmp ;
+
+wire                  upper_tx_ready ;
+wire [7:0]            upper_layer_data ;
+
+
+
+
+wire [7:0]            ip_send_type ;
+
+
+wire                  arp_tx_req ;
+wire                  arp_tx_ack ;
+wire                  ip_tx_req  ;
+wire                  ip_tx_ack  ;
+wire                  mac_tx_ack  ;
+wire                  mac_tx_req  ;
+wire                  mac_ip_tx_ack ;
+wire                  mac_arp_tx_ack ;
+
+wire                  udp_tx_ack;
+mac_tx mac0
+       (
+         .clk                        (clk             ),
+         .rst_n                      (rst_n           ),
+         
+         .crc_result                 (crc_result      ),
+         .crcen                      (crcen           ),
+         .crcre                      (crcre           ),
+         .crc_din                    (crc_din         ),
+         
+         .mac_tx_req                 (mac_tx_req      ),
+         .mac_frame_data             (mac_frame_data  ),
+         .mac_tx_ready               (mac_tx_ready    ),
+         .mac_tx_end                 (mac_tx_end      ) ,
+         
+         .mac_tx_ack                 (mac_tx_ack      ),
+         .mac_tx_data                (mac_tx_data     ),
+         .mac_send_end               (mac_send_end    ),
+         .mac_data_valid             (mac_data_valid  ),
+         .mac_data_req               (mac_data_req    )
+         
+       ) ;
+       
+mac_tx_mode mode0
+            (
+             .clk                        (clk               ),
+             .rst_n                      (rst_n             ),
+             .mac_send_end               (mac_send_end      ),
+             
+             .arp_tx_req                 (arp_tx_req        ),
+             .arp_tx_ready               (arp_tx_ready      ),
+             .arp_tx_data                (arp_tx_data       ),
+             .arp_tx_end                 (arp_tx_end        ),
+             .arp_tx_ack                 (mac_arp_tx_ack    ),
+             
+             .ip_tx_req                  (ip_tx_req         ),
+             .ip_tx_ready                (ip_tx_ready       ),
+             .ip_tx_data                 (ip_tx_data        ),
+             .ip_tx_end                  (ip_tx_end         ),
+             .ip_tx_ack                  (mac_ip_tx_ack     ),
+             
+             .mac_tx_ack                 (mac_tx_ack        ),
+             .mac_tx_req                 (mac_tx_req        ),
+             .mac_tx_ready               (mac_tx_ready      ),
+             .mac_tx_data                (mac_frame_data    ),
+             .mac_tx_end                 (mac_tx_end        )
+            );
+            
+crc c0
+    (
+      .Clk                        (clk         ),
+      .Reset                      (crcre       ),
+      .Data_in                    (crc_din     ),
+      .Enable                     (crcen       ),
+      .Crc                        (crc_result  ),
+      .CrcNext                    (            )
+    ) ;
+    
+arp_tx arp_tx0
+       (
+         .clk                        (clk                     ) ,
+         .rst_n                      (rst_n                   ) ,
+                                                             
+         .destination_mac_addr       (destination_mac_addr    ) , //destination mac address
+         .source_mac_addr            (source_mac_addr         ) , //source mac address
+         .source_ip_addr             (source_ip_addr          ) , //source ip address
+         .destination_ip_addr        (destination_ip_addr     ) , //destination ip address
+                                                             
+         .mac_data_req               (mac_data_req            ) ,
+         .mac_send_end               (mac_send_end            ),
+         
+         .mac_tx_ack                 (mac_arp_tx_ack          ),		 
+         .arp_tx_req                 (arp_tx_req              ), 
+         .arp_request_req            (arp_request_req         ) ,         //arp request
+         .arp_reply_ack              (arp_reply_ack           ),
+         .arp_reply_req              (arp_reply_req           ),
+         .arp_rec_source_ip_addr     (arp_rec_source_ip_addr  ),
+         .arp_rec_source_mac_addr    (arp_rec_source_mac_addr ),
+         .arp_tx_ready               (arp_tx_ready            ) ,
+         .arp_tx_data                (arp_tx_data             ) ,
+         .arp_tx_end                 (arp_tx_end              )
+       ) ;
+       
+       
+ip_tx ip0
+      (
+       .clk                          (clk                        ),
+       .rst_n                        (rst_n                      ),
+       .destination_mac_addr         (destination_mac_addr       ), //destination mac address
+       .source_mac_addr              (source_mac_addr            ),       //source mac address
+       .ip_send_data_length          (ip_send_data_length        ),
+       .TTL                          (TTL                        ),
+       .ip_send_type                 (ip_send_type               ),
+       .source_ip_addr               (source_ip_addr             ),
+       .destination_ip_addr          (destination_ip_addr        ),
+       .upper_layer_data             (upper_layer_data           ),
+       .upper_data_req               (upper_data_req             ),
+       .upper_tx_ready               (upper_tx_ready             ),
+       
+       .mac_data_req                 (mac_data_req               ),
+       .mac_send_end                 (mac_send_end               ),		
+       .mac_tx_ack                   (mac_ip_tx_ack              ),
+       
+       .ip_tx_req                    (ip_tx_req                  ),
+       .ip_tx_ack                    (ip_tx_ack                  ),
+       .ip_tx_ready                  (ip_tx_ready                ),
+       .ip_tx_data                   (ip_tx_data                 ),
+       .ip_tx_end                    (ip_tx_end                  )
+        
+      ) ;
+      
+ip_tx_mode ipmode
+           (
+             .clk                          (clk                        ),
+             .rst_n                        (rst_n                      ),
+             .mac_send_end                 (mac_send_end               ),
+             
+             .udp_tx_req                   (udp_tx_req_tmp             ),
+             .udp_tx_ack                   (udp_tx_ack                 ),
+             .udp_tx_ready                 (udp_tx_ready               ),
+             .udp_tx_data                  (udp_tx_data                ),
+             .udp_send_data_length         (udp_send_data_length       ),
+             
+             .icmp_tx_req                  (icmp_tx_req                ),
+             .icmp_tx_ack                  (icmp_tx_ack                ),
+             .icmp_tx_ready                (icmp_tx_ready              ),
+             .icmp_tx_data                 (icmp_tx_data               ),
+             .icmp_send_data_length        (icmp_send_data_length      ),
+             
+             .ip_tx_req                    (ip_tx_req                  ),
+             .ip_tx_ack                    (ip_tx_ack                  ),
+             .ip_tx_ready                  (upper_tx_ready             ),
+             .ip_tx_data                   (upper_layer_data           ),
+             .ip_send_type                 (ip_send_type               ),
+             .ip_send_data_length          (ip_send_data_length        )
+             
+             
+           );
+           
+udp_tx udp0
+       (
+         .clk                            (clk                        ),
+         .rst_n                          (rst_n                      ),
+         .source_ip_addr                 (source_ip_addr             ),
+         .destination_ip_addr            (destination_ip_addr        ),
+         .udp_send_source_port           (udp_send_source_port       ),
+         .udp_send_destination_port      (udp_send_destination_port  ),
+         .udp_send_data_length           (udp_send_data_length       ),
+         .udp_ram_data_req               (udp_ram_data_req           ),
+         .mac_send_end                   (mac_send_end               ),
+         .ip_tx_req                      (udp_tx_req_tmp             ),
+         .ip_tx_ack                      (udp_tx_ack                 ),
+         .ram_wr_data                    (ram_wr_data                ),
+         .ram_wr_en                      (ram_wr_en                  ),
+         .udp_tx_req                     (udp_tx_req                 ),
+         .udp_data_req                   (upper_data_req             ),
+         .udp_tx_ready                   (udp_tx_ready               ),
+         .udp_tx_data                    (udp_tx_data                ),
+         .udp_tx_end                     (udp_tx_end                 ),
+         .almost_full                    (almost_full                ),
+         .udp_ram_data_count             (udp_ram_data_count         )       
+       ) ;
+       
+endmodule
+

rtl/ethernet-udp/src/eth/mac/tx/udp_tx.v

@@ -0,0 +1,632 @@
+//////////////////////////////////////////////////////////////////////////////////////
+//Module Name : udp_tx
+//Description : This module is used to send UDP data and generate UDP checksum
+//
+//////////////////////////////////////////////////////////////////////////////////////
+`timescale 1 ns/1 ns
+module udp_tx
+       (
+          input                    clk,
+          input                    rst_n,
+          
+          input      [31:0]        source_ip_addr,
+          input      [31:0]        destination_ip_addr,
+          
+          input      [15:0]        udp_send_source_port,
+          input      [15:0]        udp_send_destination_port,
+          input      [15:0]        udp_send_data_length,
+          
+          input      [7:0]         ram_wr_data,        //write data to udp tx ram
+          input                    ram_wr_en,         //write en
+          output reg               udp_ram_data_req,      //request data written to ram
+          input                    mac_send_end,      //mac send finished
+          input                    udp_tx_req,
+          output reg               ip_tx_req,         //udp reqest ip
+          input                    ip_tx_ack,         //ip ack for udp transfer
+          input                    udp_data_req,
+          output reg               udp_tx_ready,
+          output reg [7:0]         udp_tx_data,
+          output reg               udp_tx_end,
+          output                   almost_full,
+          output     [11:0]        udp_ram_data_count
+         
+       ) ;
+       
+
+reg                       ram_rd_en ;
+(* MARK_DEBUG="true" *) wire [3:0]                usedw     ;
+reg  [3:0]                fifo_count ;
+
+reg  [7:0]                ram_rdata_d0  ;
+reg  [7:0]                ram_rdata_d1  ;
+reg  [7:0]                ram_wr_data_d0 ;
+reg  [7:0]                ram_wr_data_d1 ;
+
+wire [7:0]                ram_rdata ;
+reg  [5:0]                ram_data_length ;
+
+reg  [15:0]               udp_send_cnt  ;
+reg  [15:0]               udp_data_length ;      //valid data length
+reg  [15:0]               udp_total_data_length ;//data length when transfer
+
+reg [15:0]                timeout ;
+
+reg                       mac_send_end_d0 ;
+
+
+
+parameter IDLE              = 6'b000001 ;
+parameter START             = 6'b000010 ;
+parameter LEN_LATCH         = 6'b000100 ;
+parameter SEND_WAIT         = 6'b001000 ;
+parameter UDP_SEND          = 6'b010000 ;
+parameter UDP_END           = 6'b100000 ;
+
+
+(* MARK_DEBUG="true" *) reg [5:0]    state  ;
+reg [5:0]    next_state ;
+
+
+  reg  [16:0]        checksum_tmp0   ;
+  reg  [16:0]        checksum_tmp1   ;
+  reg  [16:0]        checksum_tmp2   ;
+  reg  [16:0]        checksum_tmp3   ;
+  reg  [16:0]        checksum_tmp4   ;
+  reg  [17:0]        checksum_tmp5   ;
+  reg  [17:0]        checksum_tmp6   ;
+  reg  [18:0]        checksum_tmp7   ;
+  reg  [19:0]        checksum_tmp8   ;
+                                     
+  reg  [31:0]        checksum_tmp9   ;
+                                     
+  reg  [31:0]        checksum_buf    ;
+  reg  [31:0]        check_out       ;
+  reg  [31:0]        checkout_buf    ;
+  wire [15:0]        checksum        ;
+  reg  [15:0]        checksum_cnt    ;
+                                     
+  reg                checksum_wr     ;
+  reg                checksum_rd     ;
+  reg  [31:0]        checksum_in     ;
+  reg                checksum_finish ;
+  reg  [15:0]        checksum_udp_len ;
+  wire [31:0]        checksum_q       ;
+  
+
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      state  <=  IDLE  ;
+    else
+      state  <= next_state ;
+  end
+  
+always @(*)
+  begin
+    case(state)
+      IDLE            :
+        begin
+          if (usedw > 4'd0)
+            next_state <= START ;
+          else
+            next_state <= IDLE ;
+        end		
+      START            :
+        begin
+          next_state <= LEN_LATCH ;
+        end  
+      LEN_LATCH   :
+	    begin
+		  if (ip_tx_ack)
+		    next_state <= SEND_WAIT ;
+		  else
+		    next_state <= LEN_LATCH ;
+		end
+      SEND_WAIT      :
+        begin
+          if (udp_data_req)
+            next_state <= UDP_SEND ;
+          else if (timeout == 16'hffff)
+            next_state <= IDLE ;
+          else
+            next_state <= SEND_WAIT ;
+        end
+        
+      UDP_SEND       :
+        begin
+          if (udp_send_cnt == udp_total_data_length)
+            next_state <= UDP_END ;
+          else
+            next_state <= UDP_SEND ;
+        end
+	  UDP_END       :
+        begin
+          if (mac_send_end_d0)
+            next_state <= IDLE ;
+          else
+            next_state <= UDP_END ;
+        end
+      default        :
+        next_state <= IDLE ;
+    endcase
+  end
+
+
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      fifo_count <= 4'd0 ;
+    else
+      fifo_count <= usedw ;
+  end 
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      checksum_rd <= 1'b0 ;
+    else if (state == IDLE && state != next_state)
+      checksum_rd <= 1'b1 ;
+	else
+	  checksum_rd <= 1'b0 ;
+  end  
+
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      ip_tx_req <= 1'b0 ;
+    else if (state == LEN_LATCH)
+      ip_tx_req <= 1'b1 ;
+	else 
+	  ip_tx_req <= 1'b0 ;
+  end
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      mac_send_end_d0 <= 1'b0 ;
+    else 
+      mac_send_end_d0 <= mac_send_end ;
+  end    
+  
+  
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      udp_tx_ready <= 1'b0 ;
+    else if (state == SEND_WAIT)
+      udp_tx_ready <= 1'b1 ;
+    else
+      udp_tx_ready <= 1'b0 ;
+  end
+  
+  
+  
+  
+//timeout counter
+always @(posedge clk or negedge rst_n)
+  begin
+    if (~rst_n)
+      timeout <= 16'd0 ;
+    else if (state == SEND_WAIT)
+      timeout <= timeout + 1'b1 ;
+    else
+      timeout <= 16'd0 ;
+  end
+ 
+udp_tx_data_fifo tx_data_fifo
+   (
+    .clk          (clk            ),                  // input wire clk
+    .srst         (~rst_n         ),                // input wire srst
+    .din          (ram_wr_data    ),                  // input wire [7 : 0] din
+    .wr_en        (ram_wr_en      ),              // input wire wr_en
+    .rd_en        (ram_rd_en      ),              // input wire rd_en
+    .dout         (ram_rdata      ),                // output wire [7 : 0] dout
+    .full         (               ),                // output wire full
+    .almost_full  (almost_full    ),  // output wire almost_full
+    .empty        (               ),              // output wire empty
+    .data_count   (udp_ram_data_count )    // output wire [11 : 0] data_count
+  );
+
+
+ always @(posedge clk or negedge rst_n)
+    begin
+      if(rst_n == 1'b0)
+        begin
+          ram_wr_data_d0 <= 8'd0 ;
+          ram_wr_data_d1 <= 8'd0 ;
+        end
+      else
+        begin
+          ram_wr_data_d0 <= ram_wr_data ;
+          ram_wr_data_d1 <= ram_wr_data_d0 ;
+        end
+    end
+  //ram signal
+  
+  always @(posedge clk or negedge rst_n)
+    begin
+      if(rst_n == 1'b0)
+        begin
+          ram_rdata_d0 <= 8'd0 ;
+          ram_rdata_d1 <= 8'd0 ;
+        end
+      else
+        begin
+          ram_rdata_d0 <= ram_rdata ;
+          ram_rdata_d1 <= ram_rdata_d0 ;
+        end
+    end
+    
+    
+    
+  always @(posedge clk or negedge rst_n)
+    begin
+      if(rst_n == 1'b0)
+        ram_rd_en <= 1'b0 ;
+      else if (state == UDP_SEND && udp_send_cnt > 4 && udp_send_cnt < udp_data_length - 3)
+        ram_rd_en <= 1'b1 ;
+      else
+        ram_rd_en <= 1'b0 ;
+    end
+    
+    
+  //checksum counter
+  always @(posedge clk or negedge rst_n)
+    begin
+      if (~rst_n)
+        udp_send_cnt  <= 16'd0 ;
+      else if (state == UDP_SEND)
+        udp_send_cnt <= udp_send_cnt + 1'b1 ;
+      else
+        udp_send_cnt <= 16'd0 ;
+    end
+    
+  
+  
+  reg [15:0]   fifo_udp_len ;
+  always @(posedge clk or negedge rst_n)
+   begin
+     if (~rst_n)
+       fifo_udp_len  <= 16'd0 ;
+     else
+       fifo_udp_len <= checksum_q[31:16] ;
+   end
+  //generate udp and ip data length
+  always @(posedge clk or negedge rst_n)
+    begin
+      if(rst_n == 1'b0)
+        begin
+          udp_total_data_length <= 16'd0 ;
+          udp_data_length <= 16'd0 ;
+        end
+      else if (state == LEN_LATCH)
+        begin
+          udp_data_length <= fifo_udp_len ;
+          if (fifo_udp_len < 26)
+            udp_total_data_length <= 26 ;
+          else
+            udp_total_data_length <= fifo_udp_len  ;
+        end
+    end
+    
+  
+  
+  //*****************************************************************************************//
+  //send udp data
+  //*****************************************************************************************//
+  always @(posedge clk or negedge rst_n)
+    begin
+      if (~rst_n)
+        udp_tx_data <= 8'h00  ;
+      else if (state == UDP_SEND)
+        begin
+          case(udp_send_cnt)
+            16'd0   :  udp_tx_data <= udp_send_source_port[15:8] ;
+            16'd1   :  udp_tx_data <= udp_send_source_port[7:0] ;
+            16'd2   :  udp_tx_data <= udp_send_destination_port[15:8] ;
+            16'd3   :  udp_tx_data <= udp_send_destination_port[7:0] ;
+            16'd4   :  udp_tx_data <= udp_data_length[15:8] ;
+            16'd5   :  udp_tx_data <= udp_data_length[7:0] ;
+            16'd6   :  udp_tx_data <= checksum_q[15:8] ;
+            16'd7   :  udp_tx_data <= checksum_q[7:0]  ;
+            default :
+              begin
+                if (udp_data_length < 26)
+                  begin
+                    if (udp_send_cnt <= udp_data_length - 1)
+                      udp_tx_data <= ram_rdata_d0 ;
+                    else
+                      udp_tx_data <= 8'h00 ;
+                  end
+                else
+                  udp_tx_data <= ram_rdata_d0 ;
+              end
+          endcase
+        end
+      else
+        udp_tx_data <= 8'h00 ;
+    end
+  
+    
+  //*****************************************************************************************//
+  //generate udp checksum
+  //*****************************************************************************************//
+  localparam CK_IDLE           = 6'b000001 ;
+  localparam HEADER_CHECKSUM   = 6'b000010 ;
+  localparam GEN_CHECKSUM      = 6'b000100 ;
+  localparam GEN_ODD_CHECKSUM  = 6'b001000 ;
+  localparam GEN_CHECKSUM_END  = 6'b010000 ;
+  localparam CHECKSUM_WAIT     = 6'b100000 ;
+  
+  (* MARK_DEBUG="true" *) reg [5:0]    ck_state  ;
+  reg [5:0]    ck_next_state ;
+  
+  always @(posedge clk or negedge rst_n)
+    begin
+      if (~rst_n)
+        ck_state  <=  IDLE  ;
+      else
+        ck_state  <= ck_next_state ;
+    end
+    
+  always @(*)
+    begin
+      case(ck_state)
+        CK_IDLE            :
+          begin
+            if (udp_tx_req)
+              ck_next_state <= HEADER_CHECKSUM ;
+            else
+              ck_next_state <= CK_IDLE ;
+          end        
+        HEADER_CHECKSUM :
+          begin
+            if (checksum_cnt == 16'd8)
+              begin
+                if (checksum_udp_len == 16'd9)
+                  ck_next_state <= GEN_ODD_CHECKSUM ;
+                else
+                  ck_next_state <= GEN_CHECKSUM ;
+              end
+            else
+              ck_next_state <= HEADER_CHECKSUM ;
+          end
+        GEN_CHECKSUM    :
+          begin
+            if (checksum_udp_len[0] == 1'b0 && checksum_cnt == checksum_udp_len - 9)
+              ck_next_state <= GEN_CHECKSUM_END ;
+            else if (checksum_udp_len[0] == 1'b1 && checksum_cnt == checksum_udp_len - 10)
+              ck_next_state <= GEN_ODD_CHECKSUM ;
+            else
+              ck_next_state <= GEN_CHECKSUM ;
+          end
+        GEN_ODD_CHECKSUM:
+          begin
+            if (checksum_cnt == checksum_udp_len - 9)
+              ck_next_state <= GEN_CHECKSUM_END ;
+            else
+              ck_next_state <= GEN_ODD_CHECKSUM ;
+          end
+        GEN_CHECKSUM_END :
+          begin
+            if (checksum_finish)
+              ck_next_state <= CHECKSUM_WAIT ;
+            else
+              ck_next_state <= GEN_CHECKSUM_END ;
+          end
+        CHECKSUM_WAIT      :
+          begin          
+              ck_next_state <= CK_IDLE ;
+          end      
+        default        :
+          ck_next_state <= CK_IDLE ;
+      endcase
+    end
+  
+  
+  
+  //checksum function
+  function    [31:0]  checksum_adder
+    (
+      input       [31:0]  dataina,
+      input       [31:0]  datainb
+    );
+    
+    begin
+      checksum_adder = dataina + datainb;
+    end
+  endfunction
+  
+  function    [31:0]  checksum_out
+    (
+      input       [31:0]  dataina
+    );
+    
+    begin
+      checksum_out = dataina[15:0]+dataina[31:16];
+    end
+    
+  endfunction
+  
+
+  
+  always @(posedge clk or negedge rst_n)
+    begin
+      if(rst_n == 1'b0)
+        begin
+          checksum_tmp0 <= 17'd0 ;
+          checksum_tmp1 <= 17'd0 ;
+          checksum_tmp2 <= 17'd0 ;
+          checksum_tmp3 <= 17'd0 ;
+          checksum_tmp4 <= 17'd0 ;
+          checksum_tmp5 <= 18'd0 ;
+          checksum_tmp6 <= 18'd0 ;
+          checksum_tmp7 <= 19'd0 ;
+          checksum_tmp8 <= 20'd0 ;
+        end
+      else if (ck_state == HEADER_CHECKSUM)
+        begin
+          checksum_tmp0 <= checksum_adder(source_ip_addr[31:16],source_ip_addr[15:0]);  //source ip address
+          checksum_tmp1 <= checksum_adder(destination_ip_addr[31:16],destination_ip_addr[15:0]);     //destination ip address
+          checksum_tmp2 <= checksum_adder({8'd0,8'd17},checksum_udp_len);                   //protocol type
+          checksum_tmp3 <= checksum_adder(udp_send_source_port,udp_send_destination_port);           //udp data length
+          checksum_tmp4 <= checksum_adder(checksum_udp_len, 16'd0);
+          checksum_tmp5 <= checksum_adder(checksum_tmp0, checksum_tmp1);
+          checksum_tmp6 <= checksum_adder(checksum_tmp2, checksum_tmp3);
+          checksum_tmp7 <= checksum_adder(checksum_tmp5, checksum_tmp6);
+          checksum_tmp8 <= checksum_adder(checksum_tmp4, checksum_tmp7);
+        end
+      else if (ck_state == CK_IDLE)
+        begin
+          checksum_tmp0 <= 17'd0 ;
+          checksum_tmp1 <= 17'd0 ;
+          checksum_tmp2 <= 17'd0 ;
+          checksum_tmp3 <= 17'd0 ;
+          checksum_tmp4 <= 17'd0 ;
+          checksum_tmp5 <= 18'd0 ;
+          checksum_tmp6 <= 18'd0 ;
+          checksum_tmp7 <= 19'd0 ;
+          checksum_tmp8 <= 20'd0 ;
+        end
+        
+    end
+    
+  always @(posedge clk or negedge rst_n)
+    begin
+      if(rst_n == 1'b0)
+        checksum_tmp9 <= 32'd0 ;
+      else if (ck_state == GEN_CHECKSUM)
+        begin
+          if(checksum_cnt[0] == 1'b1)
+            checksum_tmp9 <= checksum_adder({ram_wr_data_d1,ram_wr_data_d0},checksum_buf);
+        end
+      else if (ck_state == GEN_ODD_CHECKSUM)
+        checksum_tmp9 <= checksum_adder({ram_wr_data_d0,8'h00},checksum_tmp9);        //if udp data length is odd, fill with one byte 8'h00
+      else if (ck_state == CK_IDLE)
+        checksum_tmp9 <= 32'd0 ;
+    end
+    
+  always @(posedge clk or negedge rst_n)
+    begin
+      if (~rst_n)
+        checksum_buf <= 32'd0 ;
+      else if (ck_state == GEN_CHECKSUM)
+        checksum_buf <= checksum_tmp9 ;
+      else
+        checksum_buf <= 32'd0 ;
+    end
+    
+  always @(posedge clk or negedge rst_n)
+    begin
+      if(rst_n == 1'b0)
+        checksum_cnt <= 16'd0 ;
+      else if ((ck_state ==  HEADER_CHECKSUM || ck_state ==  GEN_ODD_CHECKSUM || ck_state ==  GEN_CHECKSUM_END) && (ck_state != ck_next_state))
+        checksum_cnt <= 16'd0 ;
+      else if (ck_state ==  GEN_CHECKSUM && ck_next_state == GEN_CHECKSUM_END)
+        checksum_cnt <= 16'd0 ;
+      else if (ck_state ==  HEADER_CHECKSUM || ck_state ==  GEN_CHECKSUM || ck_state ==  GEN_ODD_CHECKSUM || ck_state ==  GEN_CHECKSUM_END)
+        checksum_cnt <= checksum_cnt + 1'b1 ;
+      else
+        checksum_cnt <= 16'd0 ;
+    end
+    
+  always @(posedge clk or negedge rst_n)
+    begin
+      if(rst_n == 1'b0)
+        check_out <= 32'd0;
+      else if (ck_state ==  GEN_CHECKSUM_END)
+        begin
+          if(checksum_cnt == 16'd0)
+            check_out <= checksum_adder(checksum_tmp9, checksum_tmp8);
+          else if (checksum_cnt == 16'd1)
+            check_out <= checksum_out(check_out) ;
+          else if (checksum_cnt == 16'd2)
+            check_out <= checksum_out(check_out) ;
+        end
+    end
+    
+  always @(posedge clk or negedge rst_n)
+    begin
+      if (~rst_n)
+        checkout_buf <= 32'd0 ;
+      else if (ck_state == GEN_CHECKSUM_END)
+        checkout_buf <= ~check_out ;
+    end
+    
+  // assign checksum = ~checkout_buf[15:0] ;
+  
+  
+  always @(posedge clk or negedge rst_n)
+    begin
+      if (~rst_n)
+        checksum_finish <= 1'b0 ;
+      else if (ck_state == GEN_CHECKSUM_END && checksum_cnt == 16'd4)
+        checksum_finish <= 1'b1 ;
+      else
+        checksum_finish <= 1'b0 ;
+    end
+    
+  
+  always @(posedge clk or negedge rst_n)
+    begin
+      if(rst_n == 1'b0)
+        udp_ram_data_req <= 1'b0 ;
+      else if (ck_state == HEADER_CHECKSUM && checksum_cnt == 16'd5)
+        udp_ram_data_req <= 1'b1 ;
+      else
+        udp_ram_data_req <= 1'b0 ;
+    end  
+  
+  
+  always @(posedge clk or negedge rst_n)
+    begin
+      if (~rst_n)
+        checksum_wr <= 1'b0 ;
+      else if (ck_state == CHECKSUM_WAIT)
+        checksum_wr <= 1'b1 ;
+      else
+        checksum_wr <= 1'b0 ;
+    end
+  
+    
+  always @(posedge clk or negedge rst_n)
+    begin
+      if (~rst_n)
+        checksum_udp_len <= 16'd0 ;
+      else if ((ck_state == CK_IDLE) && (ck_state != ck_next_state))
+        checksum_udp_len <= udp_send_data_length + 8 ;
+    end
+  
+  always @(posedge clk or negedge rst_n)
+    begin
+      if (~rst_n)
+        checksum_in <= 32'd0 ;
+      else if (ck_state == CHECKSUM_WAIT)
+        checksum_in <= {checksum_udp_len, checkout_buf[15:0] } ;
+      else
+        checksum_in <= 32'd0 ;
+    end  
+    
+  always @(posedge clk or negedge rst_n)
+    begin
+      if (~rst_n)
+        udp_tx_end <= 1'b0 ;
+      else if (ck_state == CHECKSUM_WAIT)
+        udp_tx_end <= 1'b1 ;
+      else
+        udp_tx_end <= 1'b0 ;
+    end  
+
+udp_checksum_fifo udp_tx_checksum
+(
+  .clk        (clk        ),                // input wire clk
+  .srst       (~rst_n     ),              // input wire srst
+  .din        (checksum_in),                // input wire [31 : 0] din
+  .wr_en      (checksum_wr),            // input wire wr_en
+  .rd_en      (checksum_rd),            // input wire rd_en
+  .dout       (checksum_q ),              // output wire [31 : 0] dout
+  .full       (           ),              // output wire full
+  .empty      (           ),            // output wire empty
+  .data_count (usedw      )  // output wire [3 : 0] data_count
+);
+  
+endmodule

rtl/ethernet-udp/src/eth/reset.v

@@ -0,0 +1,20 @@
+
+module reset(
+	input clk,
+	input key1,
+	output rst_n
+);
+reg[27:0] cnt = 28'd0;
+reg rst_n_reg;
+assign rst_n = rst_n_reg;
+always@(posedge clk)
+   if(key1==1'b0)
+        cnt <= 0;
+    else
+    	if(cnt != 28'h3ffffff)
+	    	cnt <= cnt + 1'd1;
+	    else
+		    cnt <= cnt;
+always@(posedge clk)
+	rst_n_reg <= (cnt == 28'h3ffffff);
+endmodule 

rtl/ethernet-udp/src/eth/util_gmii_to_rgmii.v

@@ -0,0 +1,253 @@
+module util_gmii_to_rgmii (
+  reset,
+  sys_clk,
+  rgmii_td,
+  rgmii_tx_ctl,
+  rgmii_txc,
+  rgmii_rd,
+  rgmii_rx_ctl,
+  gmii_rx_clk,
+  rgmii_rxc,
+  gmii_txd,
+  gmii_tx_en,
+  gmii_tx_er,
+  gmii_tx_clk,
+  gmii_crs,
+  gmii_col,
+  gmii_rxd,
+  gmii_rx_dv,
+  gmii_rx_er,
+  speed_selection,
+  duplex_mode,
+  rgmii_rx_ctl_idelay
+  );
+  input           rgmii_rxc;//add
+  input           reset;
+  input           sys_clk;
+  output  [ 3:0]  rgmii_td;
+  output          rgmii_tx_ctl;
+  output          rgmii_txc;
+  input   [ 3:0]  rgmii_rd;
+  input           rgmii_rx_ctl;
+  output           gmii_rx_clk;
+  input   [ 7:0]  gmii_txd;
+  input           gmii_tx_en;
+  input           gmii_tx_er;
+  output          gmii_tx_clk;
+  output          gmii_crs;
+  output          gmii_col;
+  output  [ 7:0]  gmii_rxd;
+  output          gmii_rx_dv;
+  output          gmii_rx_er;
+  input  [ 1:0]   speed_selection; // 1x gigabit, 01 100Mbps, 00 10mbps
+  input           duplex_mode;     // 1 full, 0 half
+  output          rgmii_rx_ctl_idelay;
+
+  
+  wire gigabit;
+  wire gmii_tx_clk_s;
+  wire gmii_rx_dv_s;
+
+  wire  [ 7:0]    gmii_rxd_s;
+  wire            rgmii_rx_ctl_delay;
+  wire            rgmii_rx_ctl_s;
+  // registers
+  reg             tx_reset_d1;
+  reg             tx_reset_sync;
+  reg             rx_reset_d1;
+  reg   [ 7:0]    gmii_txd_r;
+  reg             gmii_tx_en_r;
+  reg             gmii_tx_er_r;
+  reg   [ 7:0]    gmii_txd_r_d1;
+  reg             gmii_tx_en_r_d1;
+  reg             gmii_tx_er_r_d1;
+
+  reg             rgmii_tx_ctl_r;
+  reg   [ 3:0]    gmii_txd_low;
+  reg             gmii_col;
+  reg             gmii_crs;
+
+  reg  [ 7:0]     gmii_rxd;
+  reg             gmii_rx_dv;
+  reg             gmii_rx_er;
+  wire            gmii_rx_clk_s;
+  reg[1:0] speed_selection_d0;
+  reg[1:0] speed_selection_d1;
+  
+  wire [3:0]      rgmii_rd_idelay;
+  wire [4:0] cntvaluein ;
+  wire [4:0] cntvalueout ;
+  wire  ld ;
+  always @(posedge gmii_rx_clk)
+  begin
+      speed_selection_d0<= speed_selection;
+      speed_selection_d1<= speed_selection_d0;
+  end
+  //assign gigabit        = speed_selection [1];
+  assign gigabit        = 1'b1;
+  assign gmii_tx_clk    = gmii_tx_clk_s;
+  assign gmii_tx_clk_s  = gmii_rx_clk;
+//  assign gmii_rx_clk    =~gmii_rx_clk_s;
+//  assign gmii_rx_clk=speed_selection_d0[1]?gmii_rx_clk_s:gmii_rx_clk_s;
+//  BUFG bufmr_rgmii_rxc(
+//    .I(rgmii_rxc),
+//    .O(gmii_rx_clk)
+//   );
+   assign gmii_rx_clk=rgmii_rxc;
+  always @(posedge gmii_rx_clk)
+  begin
+    gmii_rxd       = gmii_rxd_s;
+    gmii_rx_dv     = gmii_rx_dv_s;
+    gmii_rx_er     = gmii_rx_dv_s ^ rgmii_rx_ctl_s;
+  end
+
+  always @(posedge gmii_tx_clk_s) begin
+    tx_reset_d1    <= reset;
+    tx_reset_sync  <= tx_reset_d1;
+  end
+
+  always @(posedge gmii_tx_clk_s)
+  begin
+    rgmii_tx_ctl_r = gmii_tx_en_r ^ gmii_tx_er_r;
+    gmii_txd_low   = gigabit ? gmii_txd_r[7:4] :  gmii_txd_r[3:0];
+    gmii_col       = duplex_mode ? 1'b0 : (gmii_tx_en_r| gmii_tx_er_r) & ( gmii_rx_dv | gmii_rx_er) ;
+    gmii_crs       = duplex_mode ? 1'b0 : (gmii_tx_en_r| gmii_tx_er_r| gmii_rx_dv | gmii_rx_er);
+  end
+
+  always @(posedge gmii_tx_clk_s) begin
+    if (tx_reset_sync == 1'b1) begin
+      gmii_txd_r   <= 8'h0;
+      gmii_tx_en_r <= 1'b0;
+      gmii_tx_er_r <= 1'b0;
+    end
+    else
+    begin
+      gmii_txd_r   <= gmii_txd;
+      gmii_tx_en_r <= gmii_tx_en;
+      gmii_tx_er_r <= gmii_tx_er;
+      gmii_txd_r_d1   <= gmii_txd_r;
+      gmii_tx_en_r_d1 <= gmii_tx_en_r;
+      gmii_tx_er_r_d1 <= gmii_tx_er_r;
+    end
+  end
+
+
+  ODDR #(
+    .DDR_CLK_EDGE("SAME_EDGE")
+  ) rgmii_txc_out (
+    .Q (rgmii_txc),
+    .C (gmii_tx_clk_s),
+    .CE(1),
+    .D1(1),
+    .D2(0),
+    .R(tx_reset_sync),
+    .S(0));
+
+  generate
+  genvar i;
+  for (i = 0; i < 4; i = i + 1) begin : gen_tx_data
+    ODDR #(
+      .DDR_CLK_EDGE("SAME_EDGE")
+    ) rgmii_td_out (
+      .Q (rgmii_td[i]),
+      .C (gmii_tx_clk_s),
+      .CE(1),
+      .D1(gmii_txd_r_d1[i]),
+      .D2(gmii_txd_low[i]),
+      .R(tx_reset_sync),
+      .S(0));
+  end
+  endgenerate
+
+  ODDR #(
+    .DDR_CLK_EDGE("SAME_EDGE")
+  ) rgmii_tx_ctl_out (
+    .Q (rgmii_tx_ctl),
+    .C (gmii_tx_clk_s),
+    .CE(1),
+    .D1(gmii_tx_en_r_d1),
+    .D2(rgmii_tx_ctl_r),
+    .R(tx_reset_sync),
+    .S(0));
+     
+      generate
+      for (i = 0; i < 4; i = i + 1) begin
+      
+     (* IODELAY_GROUP = "rgmii_idelay_group" *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
+   
+      IDELAYE2 #(
+         .CINVCTRL_SEL("FALSE"),          // Enable dynamic clock inversion (FALSE, TRUE)
+         .DELAY_SRC("IDATAIN"),           // Delay input (IDATAIN, DATAIN)
+         .HIGH_PERFORMANCE_MODE("FALSE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
+         .IDELAY_TYPE("FIXED"),           // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
+         .IDELAY_VALUE(16),                // Input delay tap setting (0-31) May be changed for more stability
+         .PIPE_SEL("FALSE"),              // Select pipelined mode, FALSE, TRUE
+         .REFCLK_FREQUENCY(200.0),        // IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
+         .SIGNAL_PATTERN("DATA")          // DATA, CLOCK input signal
+      )
+      IDELAYE2_inst (
+         .CNTVALUEOUT(), // 5-bit output: Counter value output
+         .DATAOUT(rgmii_rd_idelay[i]),         // 1-bit output: Delayed data output
+         .C(gmii_rx_clk),                     // 1-bit input: Clock input
+         .CE(0),                   // 1-bit input: Active high enable increment/decrement input
+         .CINVCTRL(0),       // 1-bit input: Dynamic clock inversion input
+         .CNTVALUEIN(0),   // 5-bit input: Counter value input
+         .DATAIN(0),           // 1-bit input: Internal delay data input
+         .IDATAIN(rgmii_rd[i]),         // 1-bit input: Data input from the I/O
+         .INC(0),                 // 1-bit input: Increment / Decrement tap delay input
+         .LD(0),                   // 1-bit input: Load IDELAY_VALUE input
+         .LDPIPEEN(0),       // 1-bit input: Enable PIPELINE register to load data input
+         .REGRST(0)            // 1-bit input: Active-high reset tap-delay input
+      );
+      
+        IDDR #(
+          .DDR_CLK_EDGE("SAME_EDGE_PIPELINED")
+        ) rgmii_rx_iddr (
+          .Q1(gmii_rxd_s[i]),
+          .Q2(gmii_rxd_s[i+4]),
+          .C(gmii_rx_clk),
+          .CE(1),
+          .D(rgmii_rd_idelay[i]),
+          .R(0),
+          .S(0));
+      end
+      endgenerate
+    
+    (* IODELAY_GROUP = "rgmii_idelay_group" *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
+        IDELAYE2 #(
+               .CINVCTRL_SEL("FALSE"),          // Enable dynamic clock inversion (FALSE, TRUE)
+               .DELAY_SRC("IDATAIN"),           // Delay input (IDATAIN, DATAIN)
+               .HIGH_PERFORMANCE_MODE("FALSE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
+               .IDELAY_TYPE("FIXED"),           // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
+               .IDELAY_VALUE(16),                // Input delay tap setting (0-31)
+               .PIPE_SEL("FALSE"),              // Select pipelined mode, FALSE, TRUE
+               .REFCLK_FREQUENCY(200.0),        // IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
+               .SIGNAL_PATTERN("DATA")          // DATA, CLOCK input signal
+            )
+            IDELAYE2_ctrl_inst (
+               .CNTVALUEOUT(), // 5-bit output: Counter value output
+               .DATAOUT(rgmii_rx_ctl_idelay),         // 1-bit output: Delayed data output
+               .C(gmii_rx_clk),                     // 1-bit input: Clock input
+               .CE(0),                   // 1-bit input: Active high enable increment/decrement input
+               .CINVCTRL(0),       // 1-bit input: Dynamic clock inversion input
+               .CNTVALUEIN(0),   // 5-bit input: Counter value input
+               .DATAIN(0),           // 1-bit input: Internal delay data input
+               .IDATAIN(rgmii_rx_ctl),         // 1-bit input: Data input from the I/O
+               .INC(0),                 // 1-bit input: Increment / Decrement tap delay input
+               .LD(0),                   // 1-bit input: Load IDELAY_VALUE input
+               .LDPIPEEN(0),       // 1-bit input: Enable PIPELINE register to load data input
+               .REGRST(0)            // 1-bit input: Active-high reset tap-delay input
+            );
+    
+      IDDR #(
+        .DDR_CLK_EDGE("SAME_EDGE_PIPELINED")
+      ) rgmii_rx_ctl_iddr (
+        .Q1(gmii_rx_dv_s),
+        .Q2(rgmii_rx_ctl_s),
+        .C(gmii_rx_clk),
+        .CE(1),
+        .D(rgmii_rx_ctl_idelay),
+        .R(0),
+        .S(0));
+
+endmodule

rtl/ethernet-udp/src/ip/eth_data_fifo/eth_data_fifo.xci

@@ -0,0 +1,461 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "eth_data_fifo",
+    "component_reference": "xilinx.com:ip:fifo_generator:13.2",
+    "ip_revision": "13",
+    "gen_directory": "../../../../ethernet_test.gen/sources_1/ip/eth_data_fifo",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "eth_data_fifo", "resolve_type": "user", "usage": "all" } ],
+        "Fifo_Implementation": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
+        "synchronization_stages": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "synchronization_stages_axi": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "INTERFACE_TYPE": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
+        "Performance_Options": [ { "value": "Standard_FIFO", "resolve_type": "user", "usage": "all" } ],
+        "asymmetric_port_width": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Data_Width": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Input_Depth": [ { "value": "4096", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Output_Data_Width": [ { "value": "8", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Output_Depth": [ { "value": "4096", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Enable_ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Use_Embedded_Registers": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Reset_Pin": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Enable_Reset_Synchronization": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Reset_Type": [ { "value": "Asynchronous_Reset", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Full_Flags_Reset_Value": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Use_Dout_Reset": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Dout_Reset_Value": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "dynamic_power_saving": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Almost_Full_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Almost_Empty_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Valid_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Valid_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Underflow_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Underflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Write_Acknowledge_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Write_Acknowledge_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Overflow_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Overflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "ecc_pipeline_reg": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Use_Extra_Logic": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Data_Count": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Data_Count_Width": [ { "value": "12", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Write_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Write_Data_Count_Width": [ { "value": "12", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Read_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Read_Data_Count_Width": [ { "value": "12", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Disable_Timing_Violations": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Read_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Write_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "usage": "all" } ],
+        "Full_Threshold_Assert_Value": [ { "value": "4094", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Negate_Value": [ { "value": "4093", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "usage": "all" } ],
+        "Empty_Threshold_Assert_Value": [ { "value": "2", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Negate_Value": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "PROTOCOL": [ { "value": "AXI4", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Clock_Type_AXI": [ { "value": "Common_Clock", "resolve_type": "user", "usage": "all" } ],
+        "HAS_ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Clock_Enable_Type": [ { "value": "Slave_Interface_Clock_Enable", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "user", "usage": "all" } ],
+        "ID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "ADDRESS_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "DATA_WIDTH": [ { "value": "64", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "AWUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "WUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "BUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "ARUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "RUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "TDATA_NUM_BYTES": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
+        "TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "TUSER_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Enable_TREADY": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Enable_TLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "HAS_TSTRB": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "TSTRB_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "HAS_TKEEP": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "TKEEP_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "wach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_wach": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_wach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_wach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type_wach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Assert_Value_wach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type_wach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Assert_Value_wach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "wdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_wdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_wdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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rtl/ethernet-udp/src/ip/icmp_rx_ram_8_256/icmp_rx_ram_8_256.xci

@@ -0,0 +1,277 @@
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+        "C_ADDRA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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+        "C_RST_PRIORITY_B": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
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+        "C_HAS_ENB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_REGCEB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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+        "C_WEB_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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+        "C_ADDRB_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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+        "C_HAS_MUX_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MUX_PIPELINE_STAGES": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_SOFTECC_INPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_SOFTECC_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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+        "C_USE_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_ECC_PIPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_LATENCY_A": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_LATENCY_B": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_INJECTERR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SIM_COLLISION_CHECK": [ { "value": "ALL", "resolve_type": "generated", "usage": "all" } ],
+        "C_COMMON_CLK": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DISABLE_WARN_BHV_COLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_SLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_URAM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_RDADDRA_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_RDADDRB_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_DEEPSLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_SHUTDOWN_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_SAFETY_CKT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DISABLE_WARN_BHV_RANGE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_COUNT_36K_BRAM": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_COUNT_18K_BRAM": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
+        "C_EST_POWER_SUMMARY": [ { "value": "Estimated Power for IP     :     2.68455 mW", "resolve_type": "generated", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "artix7" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7a35t" } ],
+        "PACKAGE": [ { "value": "fgg484" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-1" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Flow" } ],
+        "IPREVISION": [ { "value": "11" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../ethernet_test.gen/sources_1/ip/icmp_rx_ram_8_256" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "." } ],
+        "SWVERSION": [ { "value": "2025.1" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
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+        "wea": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
+        "addra": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
+        "dina": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
+        "clkb": [ { "direction": "in", "driver_value": "0" } ],
+        "addrb": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
+        "doutb": [ { "direction": "out", "size_left": "7", "size_right": "0" } ]
+      },
+      "interfaces": {
+        "CLK.ACLK": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI", "value_src": "constant", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "s_aresetn", "value_src": "constant", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
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+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "BRAM_PORTA": {
+          "vlnv": "xilinx.com:interface:bram:1.0",
+          "abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "MEM_ADDRESS_MODE": [ { "value": "BYTE_ADDRESS", "resolve_type": "user", "usage": "all" } ],
+            "MEM_SIZE": [ { "value": "8192", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "ADDR": [ { "physical_name": "addra" } ],
+            "CLK": [ { "physical_name": "clka" } ],
+            "DIN": [ { "physical_name": "dina" } ],
+            "WE": [ { "physical_name": "wea" } ]
+          }
+        },
+        "BRAM_PORTB": {
+          "vlnv": "xilinx.com:interface:bram:1.0",
+          "abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "MEM_ADDRESS_MODE": [ { "value": "BYTE_ADDRESS", "resolve_type": "user", "usage": "all" } ],
+            "MEM_SIZE": [ { "value": "8192", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "ADDR": [ { "physical_name": "addrb" } ],
+            "CLK": [ { "physical_name": "clkb" } ],
+            "DOUT": [ { "physical_name": "doutb" } ]
+          }
+        }
+      },
+      "memory_maps": {
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+          "address_blocks": {
+            "Mem0": {
+              "base_address": "0",
+              "range": "4096",
+              "usage": "memory",
+              "access": "read-write",
+              "parameters": {
+                "OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
+                "OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
+              }
+            }
+          }
+        }
+      }
+    }
+  }
+}

rtl/ethernet-udp/src/ip/len_fifo/len_fifo.xci

@@ -0,0 +1,461 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "len_fifo",
+    "component_reference": "xilinx.com:ip:fifo_generator:13.2",
+    "ip_revision": "13",
+    "gen_directory": "../../../../ethernet_test.gen/sources_1/ip/len_fifo",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "len_fifo", "resolve_type": "user", "usage": "all" } ],
+        "Fifo_Implementation": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
+        "synchronization_stages": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "synchronization_stages_axi": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "INTERFACE_TYPE": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
+        "Performance_Options": [ { "value": "Standard_FIFO", "resolve_type": "user", "usage": "all" } ],
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+        "Input_Depth": [ { "value": "32", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
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+        "Output_Depth": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Enable_ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Use_Embedded_Registers": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Reset_Pin": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Enable_Reset_Synchronization": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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+        "Dout_Reset_Value": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "dynamic_power_saving": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Almost_Full_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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+        "Underflow_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Underflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Write_Acknowledge_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Write_Acknowledge_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Overflow_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Overflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "ecc_pipeline_reg": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Use_Extra_Logic": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Data_Count": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Data_Count_Width": [ { "value": "5", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Write_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Write_Data_Count_Width": [ { "value": "5", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Read_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Read_Data_Count_Width": [ { "value": "5", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Disable_Timing_Violations": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Read_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Write_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "usage": "all" } ],
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+        "Full_Threshold_Negate_Value": [ { "value": "29", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "usage": "all" } ],
+        "Empty_Threshold_Assert_Value": [ { "value": "2", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Negate_Value": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "PROTOCOL": [ { "value": "AXI4", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Clock_Type_AXI": [ { "value": "Common_Clock", "resolve_type": "user", "usage": "all" } ],
+        "HAS_ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Clock_Enable_Type": [ { "value": "Slave_Interface_Clock_Enable", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "user", "usage": "all" } ],
+        "ID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "ADDRESS_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "DATA_WIDTH": [ { "value": "64", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "AWUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "WUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "BUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "ARUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "RUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "TDATA_NUM_BYTES": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
+        "TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "TUSER_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Enable_TREADY": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Enable_TLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "HAS_TSTRB": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "TSTRB_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "HAS_TKEEP": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "TKEEP_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "wach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_wach": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_wach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_wach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type_wach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Assert_Value_wach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type_wach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Assert_Value_wach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "wdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_wdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_wdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_wdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type_wdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Assert_Value_wdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type_wdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Assert_Value_wdch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "wrch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_wrch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_wrch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_wrch": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type_wrch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Assert_Value_wrch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type_wrch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Assert_Value_wrch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "rach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_rach": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_rach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_rach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type_rach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Assert_Value_rach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type_rach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Assert_Value_rach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "rdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_rdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_rdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_rdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type_rdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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+        "Programmable_Empty_Type_rdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Assert_Value_rdch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "axis_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_axis": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_axis": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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+        "Input_Depth_axis": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
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+        "Register_Slice_Mode_wdch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
+        "Register_Slice_Mode_wrch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
+        "Register_Slice_Mode_rach": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
+        "Register_Slice_Mode_rdch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
+        "Register_Slice_Mode_axis": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
+        "Underflow_Flag_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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+        "Add_NGC_Constraint_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Enable_Common_Underflow": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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+        "enable_read_pointer_increment_by2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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+        "Master_interface_Clock_enable_memory_mapped": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Slave_interface_Clock_enable_memory_mapped": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Output_Register_Type": [ { "value": "Embedded_Reg", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_Safety_Circuit": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Enable_ECC_Type": [ { "value": "Hard_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "C_SELECT_XPM": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ]
+      },
+      "model_parameters": {
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+        "C_SELECT_XPM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_COUNT_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DATA_COUNT_WIDTH": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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+        "C_DOUT_RST_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_DOUT_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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+        "C_FAMILY": [ { "value": "artix7", "resolve_type": "generated", "usage": "all" } ],
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+        "C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH": [ { "value": "1022", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH": [ { "value": "1022", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH": [ { "value": "1022", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH": [ { "value": "1022", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS": [ { "value": "1022", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_REG_SLICE_MODE_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_REG_SLICE_MODE_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_REG_SLICE_MODE_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_REG_SLICE_MODE_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_REG_SLICE_MODE_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_REG_SLICE_MODE_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "artix7" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7a35t" } ],
+        "PACKAGE": [ { "value": "fgg484" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-1" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Flow" } ],
+        "IPREVISION": [ { "value": "13" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../ethernet_test.gen/sources_1/ip/len_fifo" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "." } ],
+        "SWVERSION": [ { "value": "2025.1" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "clk": [ { "direction": "in", "driver_value": "0" } ],
+        "rst": [ { "direction": "in", "driver_value": "0" } ],
+        "din": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
+        "wr_en": [ { "direction": "in", "driver_value": "0" } ],
+        "rd_en": [ { "direction": "in", "driver_value": "0" } ],
+        "dout": [ { "direction": "out", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
+        "full": [ { "direction": "out", "driver_value": "0x0" } ],
+        "empty": [ { "direction": "out", "driver_value": "0x1" } ],
+        "data_count": [ { "direction": "out", "size_left": "4", "size_right": "0", "driver_value": "0" } ]
+      },
+      "interfaces": {
+        "core_clk": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "clk" } ]
+          }
+        },
+        "FIFO_WRITE": {
+          "vlnv": "xilinx.com:interface:fifo_write:1.0",
+          "abstraction_type": "xilinx.com:interface:fifo_write_rtl:1.0",
+          "mode": "slave",
+          "port_maps": {
+            "FULL": [ { "physical_name": "full" } ],
+            "WR_DATA": [ { "physical_name": "din" } ],
+            "WR_EN": [ { "physical_name": "wr_en" } ]
+          }
+        },
+        "FIFO_READ": {
+          "vlnv": "xilinx.com:interface:fifo_read:1.0",
+          "abstraction_type": "xilinx.com:interface:fifo_read_rtl:1.0",
+          "mode": "slave",
+          "port_maps": {
+            "EMPTY": [ { "physical_name": "empty" } ],
+            "RD_DATA": [ { "physical_name": "dout" } ],
+            "RD_EN": [ { "physical_name": "rd_en" } ]
+          }
+        }
+      }
+    }
+  }
+}

rtl/ethernet-udp/src/ip/udp_checksum_fifo/udp_checksum_fifo.xci

@@ -0,0 +1,461 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "udp_checksum_fifo",
+    "component_reference": "xilinx.com:ip:fifo_generator:13.2",
+    "ip_revision": "13",
+    "gen_directory": "../../../../ethernet_test.gen/sources_1/ip/udp_checksum_fifo",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "udp_checksum_fifo", "resolve_type": "user", "usage": "all" } ],
+        "Fifo_Implementation": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
+        "synchronization_stages": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "synchronization_stages_axi": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "INTERFACE_TYPE": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
+        "Performance_Options": [ { "value": "Standard_FIFO", "resolve_type": "user", "usage": "all" } ],
+        "asymmetric_port_width": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Data_Width": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Input_Depth": [ { "value": "16", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Output_Data_Width": [ { "value": "32", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Output_Depth": [ { "value": "16", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Enable_ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Use_Embedded_Registers": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Reset_Pin": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Enable_Reset_Synchronization": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Reset_Type": [ { "value": "Synchronous_Reset", "resolve_type": "user", "usage": "all" } ],
+        "Full_Flags_Reset_Value": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Use_Dout_Reset": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Dout_Reset_Value": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "dynamic_power_saving": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Almost_Full_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Almost_Empty_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Valid_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Valid_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Underflow_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Underflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Write_Acknowledge_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Write_Acknowledge_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Overflow_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Overflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "ecc_pipeline_reg": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Use_Extra_Logic": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Data_Count": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Data_Count_Width": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Write_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Write_Data_Count_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Read_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Read_Data_Count_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Disable_Timing_Violations": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Read_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Write_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "usage": "all" } ],
+        "Full_Threshold_Assert_Value": [ { "value": "14", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Negate_Value": [ { "value": "13", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "usage": "all" } ],
+        "Empty_Threshold_Assert_Value": [ { "value": "2", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Negate_Value": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "PROTOCOL": [ { "value": "AXI4", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Clock_Type_AXI": [ { "value": "Common_Clock", "resolve_type": "user", "usage": "all" } ],
+        "HAS_ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Clock_Enable_Type": [ { "value": "Slave_Interface_Clock_Enable", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "user", "usage": "all" } ],
+        "ID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "ADDRESS_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "DATA_WIDTH": [ { "value": "64", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "AWUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "WUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "BUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "ARUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "RUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "TDATA_NUM_BYTES": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
+        "TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "TUSER_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Enable_TREADY": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Enable_TLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "HAS_TSTRB": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "TSTRB_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "HAS_TKEEP": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "TKEEP_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "wach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_wach": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_wach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_wach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type_wach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Assert_Value_wach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type_wach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Assert_Value_wach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "wdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_wdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_wdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_wdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type_wdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Assert_Value_wdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type_wdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Assert_Value_wdch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "wrch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_wrch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_wrch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_wrch": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type_wrch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Assert_Value_wrch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type_wrch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Assert_Value_wrch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "rach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_rach": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_rach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_rach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type_rach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Assert_Value_rach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type_rach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Assert_Value_rach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "rdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_rdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_rdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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+}

rtl/ethernet-udp/src/ip/udp_rx_ram_8_2048/udp_rx_ram_8_2048.xci

@@ -0,0 +1,277 @@
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+        "C_EN_SLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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+        "C_EN_RDADDRA_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_RDADDRB_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_DEEPSLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_SHUTDOWN_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_SAFETY_CKT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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+        "C_COUNT_36K_BRAM": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_COUNT_18K_BRAM": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
+        "C_EST_POWER_SUMMARY": [ { "value": "Estimated Power for IP     :     2.4787 mW", "resolve_type": "generated", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "artix7" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7a35t" } ],
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+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-1" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Flow" } ],
+        "IPREVISION": [ { "value": "11" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../ethernet_test.gen/sources_1/ip/udp_rx_ram_8_2048" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "." } ],
+        "SWVERSION": [ { "value": "2025.1" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
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+        "addra": [ { "direction": "in", "size_left": "10", "size_right": "0", "driver_value": "0" } ],
+        "dina": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
+        "clkb": [ { "direction": "in", "driver_value": "0" } ],
+        "addrb": [ { "direction": "in", "size_left": "10", "size_right": "0", "driver_value": "0" } ],
+        "doutb": [ { "direction": "out", "size_left": "7", "size_right": "0" } ]
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+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI", "value_src": "constant", "usage": "all" } ],
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+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
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+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
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+          "abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
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+            "MEM_SIZE": [ { "value": "8192", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          },
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+            "DIN": [ { "physical_name": "dina" } ],
+            "WE": [ { "physical_name": "wea" } ]
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+          "abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
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+            "MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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+          },
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+            "CLK": [ { "physical_name": "clkb" } ],
+            "DOUT": [ { "physical_name": "doutb" } ]
+          }
+        }
+      },
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+              "range": "4096",
+              "usage": "memory",
+              "access": "read-write",
+              "parameters": {
+                "OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
+                "OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
+              }
+            }
+          }
+        }
+      }
+    }
+  }
+}

rtl/ethernet-udp/src/ip/udp_tx_data_fifo/udp_tx_data_fifo.xci

@@ -0,0 +1,463 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
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+    "ip_revision": "13",
+    "gen_directory": "../../../../ethernet_test.gen/sources_1/ip/udp_tx_data_fifo",
+    "parameters": {
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+        "synchronization_stages_axi": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "INTERFACE_TYPE": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
+        "Performance_Options": [ { "value": "Standard_FIFO", "resolve_type": "user", "usage": "all" } ],
+        "asymmetric_port_width": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Data_Width": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Input_Depth": [ { "value": "4096", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Output_Data_Width": [ { "value": "8", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Output_Depth": [ { "value": "4096", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Enable_ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Use_Embedded_Registers": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Reset_Pin": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Enable_Reset_Synchronization": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Reset_Type": [ { "value": "Synchronous_Reset", "resolve_type": "user", "usage": "all" } ],
+        "Full_Flags_Reset_Value": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Use_Dout_Reset": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Dout_Reset_Value": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "dynamic_power_saving": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Almost_Full_Flag": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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+        "Underflow_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Underflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Write_Acknowledge_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Write_Acknowledge_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Overflow_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Overflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "ecc_pipeline_reg": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Use_Extra_Logic": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Data_Count": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Data_Count_Width": [ { "value": "12", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Write_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Write_Data_Count_Width": [ { "value": "12", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Read_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Read_Data_Count_Width": [ { "value": "12", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Disable_Timing_Violations": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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+            "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "clk" } ]
+          }
+        },
+        "FIFO_WRITE": {
+          "vlnv": "xilinx.com:interface:fifo_write:1.0",
+          "abstraction_type": "xilinx.com:interface:fifo_write_rtl:1.0",
+          "mode": "slave",
+          "port_maps": {
+            "ALMOST_FULL": [ { "physical_name": "almost_full" } ],
+            "FULL": [ { "physical_name": "full" } ],
+            "WR_DATA": [ { "physical_name": "din" } ],
+            "WR_EN": [ { "physical_name": "wr_en" } ]
+          }
+        },
+        "FIFO_READ": {
+          "vlnv": "xilinx.com:interface:fifo_read:1.0",
+          "abstraction_type": "xilinx.com:interface:fifo_read_rtl:1.0",
+          "mode": "slave",
+          "port_maps": {
+            "EMPTY": [ { "physical_name": "empty" } ],
+            "RD_DATA": [ { "physical_name": "dout" } ],
+            "RD_EN": [ { "physical_name": "rd_en" } ]
+          }
+        }
+      }
+    }
+  }
+}

rtl/ethernet-udp/tests/eth_axis/Makefile

@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# FPGA settings
+FPGA_PART = xc7a35tfgg484-1
+FPGA_TOP = ethernet_axis_echo
+FPGA_ARCH = artix7
+
+RTL_DIR = ../../src
+
+# Files for synthesis
+SYN_FILES = ethernet_axis_echo.v
+
+include ../../../../scripts/vivado.mk
+
+SYN_FILES += $(sort $(shell find ../../src -type f \( -name '*.v' -o -name '*.sv' \)))
+
+XCI_FILES = $(sort $(shell find ../../src -type f -name '*.xci'))
+
+XDC_FILES += debug.xdc
+XDC_FILES += ../../../../constraints/ax7a035b.xdc
+
+SIM_TOP = tb_mac_test
+TB_FILES = test_axis_mac_rx.sv
+
+program: $(PROJECT).bit
+	echo "open_hw_manager" > program.tcl
+	echo "connect_hw_server" >> program.tcl
+	echo "open_hw_target" >> program.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+	echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
+	echo "program_hw_devices [current_hw_device]" >> program.tcl
+	echo "exit" >> program.tcl
+	vivado -nojournal -nolog -mode batch -source program.tcl
+
+$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
+	echo "write_cfgmem -force -format mcs -size 16 -interface SPIx4 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
+	echo "exit" >> generate_mcs.tcl
+	vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	for x in .mcs .prm; \
+	do cp $*$$x rev/$*_rev$$COUNT$$x; \
+	echo "Output: rev/$*_rev$$COUNT$$x"; done;

rtl/ethernet-udp/tests/eth_axis/debug.xdc

@@ -0,0 +1,260 @@
+# debug ila
+
+create_debug_core u_ila_0 ila
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
+set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
+set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
+set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
+set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
+set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
+set_property port_width 1 [get_debug_ports u_ila_0/clk]
+connect_debug_port u_ila_0/clk [get_nets [list rgmii_rxc_IBUF_BUFG]]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
+set_property port_width 8 [get_debug_ports u_ila_0/probe0]
+connect_debug_port u_ila_0/probe0 [get_nets [list {arbi_inst/rx_buffer_inst/e10_100_rxd[0]} {arbi_inst/rx_buffer_inst/e10_100_rxd[1]} {arbi_inst/rx_buffer_inst/e10_100_rxd[2]} {arbi_inst/rx_buffer_inst/e10_100_rxd[3]} {arbi_inst/rx_buffer_inst/e10_100_rxd[4]} {arbi_inst/rx_buffer_inst/e10_100_rxd[5]} {arbi_inst/rx_buffer_inst/e10_100_rxd[6]} {arbi_inst/rx_buffer_inst/e10_100_rxd[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
+set_property port_width 8 [get_debug_ports u_ila_0/probe1]
+connect_debug_port u_ila_0/probe1 [get_nets [list {arbi_inst/gmii_rxd[0]} {arbi_inst/gmii_rxd[1]} {arbi_inst/gmii_rxd[2]} {arbi_inst/gmii_rxd[3]} {arbi_inst/gmii_rxd[4]} {arbi_inst/gmii_rxd[5]} {arbi_inst/gmii_rxd[6]} {arbi_inst/gmii_rxd[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
+set_property port_width 8 [get_debug_ports u_ila_0/probe2]
+connect_debug_port u_ila_0/probe2 [get_nets [list {arbi_inst/gmii_txd[0]} {arbi_inst/gmii_txd[1]} {arbi_inst/gmii_txd[2]} {arbi_inst/gmii_txd[3]} {arbi_inst/gmii_txd[4]} {arbi_inst/gmii_txd[5]} {arbi_inst/gmii_txd[6]} {arbi_inst/gmii_txd[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
+set_property port_width 8 [get_debug_ports u_ila_0/probe3]
+connect_debug_port u_ila_0/probe3 [get_nets [list {arbi_inst/e_txd[0]} {arbi_inst/e_txd[1]} {arbi_inst/e_txd[2]} {arbi_inst/e_txd[3]} {arbi_inst/e_txd[4]} {arbi_inst/e_txd[5]} {arbi_inst/e_txd[6]} {arbi_inst/e_txd[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
+set_property port_width 8 [get_debug_ports u_ila_0/probe4]
+connect_debug_port u_ila_0/probe4 [get_nets [list {arbi_inst/e_rxd[0]} {arbi_inst/e_rxd[1]} {arbi_inst/e_rxd[2]} {arbi_inst/e_rxd[3]} {arbi_inst/e_rxd[4]} {arbi_inst/e_rxd[5]} {arbi_inst/e_rxd[6]} {arbi_inst/e_rxd[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
+set_property port_width 16 [get_debug_ports u_ila_0/probe5]
+connect_debug_port u_ila_0/probe5 [get_nets [list {arbi_inst/tx_buffer_inst/tx_data_cnt[0]} {arbi_inst/tx_buffer_inst/tx_data_cnt[1]} {arbi_inst/tx_buffer_inst/tx_data_cnt[2]} {arbi_inst/tx_buffer_inst/tx_data_cnt[3]} {arbi_inst/tx_buffer_inst/tx_data_cnt[4]} {arbi_inst/tx_buffer_inst/tx_data_cnt[5]} {arbi_inst/tx_buffer_inst/tx_data_cnt[6]} {arbi_inst/tx_buffer_inst/tx_data_cnt[7]} {arbi_inst/tx_buffer_inst/tx_data_cnt[8]} {arbi_inst/tx_buffer_inst/tx_data_cnt[9]} {arbi_inst/tx_buffer_inst/tx_data_cnt[10]} {arbi_inst/tx_buffer_inst/tx_data_cnt[11]} {arbi_inst/tx_buffer_inst/tx_data_cnt[12]} {arbi_inst/tx_buffer_inst/tx_data_cnt[13]} {arbi_inst/tx_buffer_inst/tx_data_cnt[14]} {arbi_inst/tx_buffer_inst/tx_data_cnt[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
+set_property port_width 8 [get_debug_ports u_ila_0/probe6]
+connect_debug_port u_ila_0/probe6 [get_nets [list {arbi_inst/tx_buffer_inst/tx_rdata[0]} {arbi_inst/tx_buffer_inst/tx_rdata[1]} {arbi_inst/tx_buffer_inst/tx_rdata[2]} {arbi_inst/tx_buffer_inst/tx_rdata[3]} {arbi_inst/tx_buffer_inst/tx_rdata[4]} {arbi_inst/tx_buffer_inst/tx_rdata[5]} {arbi_inst/tx_buffer_inst/tx_rdata[6]} {arbi_inst/tx_buffer_inst/tx_rdata[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
+set_property port_width 8 [get_debug_ports u_ila_0/probe7]
+connect_debug_port u_ila_0/probe7 [get_nets [list {arbi_inst/tx_buffer_inst/tx_wdata[0]} {arbi_inst/tx_buffer_inst/tx_wdata[1]} {arbi_inst/tx_buffer_inst/tx_wdata[2]} {arbi_inst/tx_buffer_inst/tx_wdata[3]} {arbi_inst/tx_buffer_inst/tx_wdata[4]} {arbi_inst/tx_buffer_inst/tx_wdata[5]} {arbi_inst/tx_buffer_inst/tx_wdata[6]} {arbi_inst/tx_buffer_inst/tx_wdata[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
+set_property port_width 6 [get_debug_ports u_ila_0/probe8]
+connect_debug_port u_ila_0/probe8 [get_nets [list {axis_mac0/mac_top0/mac_tx0/udp0/ck_state[0]} {axis_mac0/mac_top0/mac_tx0/udp0/ck_state[1]} {axis_mac0/mac_top0/mac_tx0/udp0/ck_state[2]} {axis_mac0/mac_top0/mac_tx0/udp0/ck_state[3]} {axis_mac0/mac_top0/mac_tx0/udp0/ck_state[4]} {axis_mac0/mac_top0/mac_tx0/udp0/ck_state[5]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
+set_property port_width 16 [get_debug_ports u_ila_0/probe9]
+connect_debug_port u_ila_0/probe9 [get_nets [list {axis_mac0/udp_rec_data_length[0]} {axis_mac0/udp_rec_data_length[1]} {axis_mac0/udp_rec_data_length[2]} {axis_mac0/udp_rec_data_length[3]} {axis_mac0/udp_rec_data_length[4]} {axis_mac0/udp_rec_data_length[5]} {axis_mac0/udp_rec_data_length[6]} {axis_mac0/udp_rec_data_length[7]} {axis_mac0/udp_rec_data_length[8]} {axis_mac0/udp_rec_data_length[9]} {axis_mac0/udp_rec_data_length[10]} {axis_mac0/udp_rec_data_length[11]} {axis_mac0/udp_rec_data_length[12]} {axis_mac0/udp_rec_data_length[13]} {axis_mac0/udp_rec_data_length[14]} {axis_mac0/udp_rec_data_length[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
+set_property port_width 3 [get_debug_ports u_ila_0/probe10]
+connect_debug_port u_ila_0/probe10 [get_nets [list {axis_mac0/tx_state[0]} {axis_mac0/tx_state[1]} {axis_mac0/tx_state[2]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
+set_property port_width 8 [get_debug_ports u_ila_0/probe11]
+connect_debug_port u_ila_0/probe11 [get_nets [list {axis_mac0/s_axis_tx_tdata[0]} {axis_mac0/s_axis_tx_tdata[1]} {axis_mac0/s_axis_tx_tdata[2]} {axis_mac0/s_axis_tx_tdata[3]} {axis_mac0/s_axis_tx_tdata[4]} {axis_mac0/s_axis_tx_tdata[5]} {axis_mac0/s_axis_tx_tdata[6]} {axis_mac0/s_axis_tx_tdata[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
+set_property port_width 2 [get_debug_ports u_ila_0/probe12]
+connect_debug_port u_ila_0/probe12 [get_nets [list {axis_mac0/rx_state[0]} {axis_mac0/rx_state[1]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
+set_property port_width 16 [get_debug_ports u_ila_0/probe13]
+connect_debug_port u_ila_0/probe13 [get_nets [list {axis_mac0/rx_payload_len[0]} {axis_mac0/rx_payload_len[1]} {axis_mac0/rx_payload_len[2]} {axis_mac0/rx_payload_len[3]} {axis_mac0/rx_payload_len[4]} {axis_mac0/rx_payload_len[5]} {axis_mac0/rx_payload_len[6]} {axis_mac0/rx_payload_len[7]} {axis_mac0/rx_payload_len[8]} {axis_mac0/rx_payload_len[9]} {axis_mac0/rx_payload_len[10]} {axis_mac0/rx_payload_len[11]} {axis_mac0/rx_payload_len[12]} {axis_mac0/rx_payload_len[13]} {axis_mac0/rx_payload_len[14]} {axis_mac0/rx_payload_len[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
+set_property port_width 16 [get_debug_ports u_ila_0/probe14]
+connect_debug_port u_ila_0/probe14 [get_nets [list {axis_mac0/rx_index[0]} {axis_mac0/rx_index[1]} {axis_mac0/rx_index[2]} {axis_mac0/rx_index[3]} {axis_mac0/rx_index[4]} {axis_mac0/rx_index[5]} {axis_mac0/rx_index[6]} {axis_mac0/rx_index[7]} {axis_mac0/rx_index[8]} {axis_mac0/rx_index[9]} {axis_mac0/rx_index[10]} {axis_mac0/rx_index[11]} {axis_mac0/rx_index[12]} {axis_mac0/rx_index[13]} {axis_mac0/rx_index[14]} {axis_mac0/rx_index[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
+set_property port_width 8 [get_debug_ports u_ila_0/probe15]
+connect_debug_port u_ila_0/probe15 [get_nets [list {axis_mac0/m_axis_rx_tdata[0]} {axis_mac0/m_axis_rx_tdata[1]} {axis_mac0/m_axis_rx_tdata[2]} {axis_mac0/m_axis_rx_tdata[3]} {axis_mac0/m_axis_rx_tdata[4]} {axis_mac0/m_axis_rx_tdata[5]} {axis_mac0/m_axis_rx_tdata[6]} {axis_mac0/m_axis_rx_tdata[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
+set_property port_width 16 [get_debug_ports u_ila_0/probe16]
+connect_debug_port u_ila_0/probe16 [get_nets [list {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[0]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[1]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[2]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[3]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[4]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[5]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[6]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[7]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[8]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[9]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[10]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[11]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[12]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[13]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[14]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
+set_property port_width 12 [get_debug_ports u_ila_0/probe17]
+connect_debug_port u_ila_0/probe17 [get_nets [list {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[0]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[1]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[2]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[3]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[4]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[5]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[6]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[7]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[8]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[9]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[10]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[11]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
+set_property port_width 8 [get_debug_ports u_ila_0/probe18]
+connect_debug_port u_ila_0/probe18 [get_nets [list {axis_mac0/mac_top0/mac_tx0/ram_wr_data[0]} {axis_mac0/mac_top0/mac_tx0/ram_wr_data[1]} {axis_mac0/mac_top0/mac_tx0/ram_wr_data[2]} {axis_mac0/mac_top0/mac_tx0/ram_wr_data[3]} {axis_mac0/mac_top0/mac_tx0/ram_wr_data[4]} {axis_mac0/mac_top0/mac_tx0/ram_wr_data[5]} {axis_mac0/mac_top0/mac_tx0/ram_wr_data[6]} {axis_mac0/mac_top0/mac_tx0/ram_wr_data[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
+set_property port_width 8 [get_debug_ports u_ila_0/probe19]
+connect_debug_port u_ila_0/probe19 [get_nets [list {axis_mac0/mac_top0/mac_tx0/mac_tx_data[0]} {axis_mac0/mac_top0/mac_tx0/mac_tx_data[1]} {axis_mac0/mac_top0/mac_tx0/mac_tx_data[2]} {axis_mac0/mac_top0/mac_tx0/mac_tx_data[3]} {axis_mac0/mac_top0/mac_tx0/mac_tx_data[4]} {axis_mac0/mac_top0/mac_tx0/mac_tx_data[5]} {axis_mac0/mac_top0/mac_tx0/mac_tx_data[6]} {axis_mac0/mac_top0/mac_tx0/mac_tx_data[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
+set_property port_width 4 [get_debug_ports u_ila_0/probe20]
+connect_debug_port u_ila_0/probe20 [get_nets [list {axis_mac0/mac_top0/mac_tx0/udp0/usedw[0]} {axis_mac0/mac_top0/mac_tx0/udp0/usedw[1]} {axis_mac0/mac_top0/mac_tx0/udp0/usedw[2]} {axis_mac0/mac_top0/mac_tx0/udp0/usedw[3]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
+set_property port_width 6 [get_debug_ports u_ila_0/probe21]
+connect_debug_port u_ila_0/probe21 [get_nets [list {axis_mac0/mac_top0/mac_tx0/udp0/state[0]} {axis_mac0/mac_top0/mac_tx0/udp0/state[1]} {axis_mac0/mac_top0/mac_tx0/udp0/state[2]} {axis_mac0/mac_top0/mac_tx0/udp0/state[3]} {axis_mac0/mac_top0/mac_tx0/udp0/state[4]} {axis_mac0/mac_top0/mac_tx0/udp0/state[5]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
+set_property port_width 16 [get_debug_ports u_ila_0/probe22]
+connect_debug_port u_ila_0/probe22 [get_nets [list {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[0]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[1]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[2]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[3]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[4]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[5]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[6]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[7]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[8]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[9]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[10]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[11]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[12]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[13]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[14]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
+set_property port_width 11 [get_debug_ports u_ila_0/probe23]
+connect_debug_port u_ila_0/probe23 [get_nets [list {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[0]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[1]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[2]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[3]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[4]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[5]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[6]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[7]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[8]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[9]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[10]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
+set_property port_width 8 [get_debug_ports u_ila_0/probe24]
+connect_debug_port u_ila_0/probe24 [get_nets [list {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[0]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[1]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[2]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[3]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[4]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[5]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[6]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
+set_property port_width 16 [get_debug_ports u_ila_0/probe25]
+connect_debug_port u_ila_0/probe25 [get_nets [list {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[0]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[1]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[2]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[3]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[4]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[5]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[6]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[7]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[8]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[9]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[10]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[11]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[12]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[13]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[14]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
+set_property port_width 8 [get_debug_ports u_ila_0/probe26]
+connect_debug_port u_ila_0/probe26 [get_nets [list {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[0]} {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[1]} {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[2]} {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[3]} {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[4]} {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[5]} {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[6]} {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
+set_property port_width 16 [get_debug_ports u_ila_0/probe27]
+connect_debug_port u_ila_0/probe27 [get_nets [list {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[0]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[1]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[2]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[3]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[4]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[5]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[6]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[7]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[8]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[9]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[10]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[11]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[12]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[13]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[14]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
+set_property port_width 8 [get_debug_ports u_ila_0/probe28]
+connect_debug_port u_ila_0/probe28 [get_nets [list {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[0]} {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[1]} {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[2]} {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[3]} {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[4]} {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[5]} {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[6]} {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
+set_property port_width 11 [get_debug_ports u_ila_0/probe29]
+connect_debug_port u_ila_0/probe29 [get_nets [list {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[0]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[1]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[2]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[3]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[4]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[5]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[6]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[7]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[8]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[9]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[10]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
+set_property port_width 2 [get_debug_ports u_ila_0/probe30]
+connect_debug_port u_ila_0/probe30 [get_nets [list {test_state[0]} {test_state[1]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
+set_property port_width 1 [get_debug_ports u_ila_0/probe31]
+connect_debug_port u_ila_0/probe31 [get_nets [list axis_mac0/mac_top0/mac_tx0/almost_full]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
+set_property port_width 1 [get_debug_ports u_ila_0/probe32]
+connect_debug_port u_ila_0/probe32 [get_nets [list axis_mac0/arp_found]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
+set_property port_width 1 [get_debug_ports u_ila_0/probe33]
+connect_debug_port u_ila_0/probe33 [get_nets [list arbi_inst/rx_buffer_inst/e10_100_rx_dv]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
+set_property port_width 1 [get_debug_ports u_ila_0/probe34]
+connect_debug_port u_ila_0/probe34 [get_nets [list arbi_inst/e_rx_dv]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
+set_property port_width 1 [get_debug_ports u_ila_0/probe35]
+connect_debug_port u_ila_0/probe35 [get_nets [list arbi_inst/e_tx_en]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
+set_property port_width 1 [get_debug_ports u_ila_0/probe36]
+connect_debug_port u_ila_0/probe36 [get_nets [list arbi_inst/gmii_rx_dv]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
+set_property port_width 1 [get_debug_ports u_ila_0/probe37]
+connect_debug_port u_ila_0/probe37 [get_nets [list arbi_inst/rx_buffer_inst/gmii_rx_dv_d0]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
+set_property port_width 1 [get_debug_ports u_ila_0/probe38]
+connect_debug_port u_ila_0/probe38 [get_nets [list arbi_inst/rx_buffer_inst/gmii_rx_dv_d1]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39]
+set_property port_width 1 [get_debug_ports u_ila_0/probe39]
+connect_debug_port u_ila_0/probe39 [get_nets [list arbi_inst/gmii_tx_en]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40]
+set_property port_width 1 [get_debug_ports u_ila_0/probe40]
+connect_debug_port u_ila_0/probe40 [get_nets [list axis_mac0/m_axis_rx_tlast]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41]
+set_property port_width 1 [get_debug_ports u_ila_0/probe41]
+connect_debug_port u_ila_0/probe41 [get_nets [list axis_mac0/m_axis_rx_tready]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42]
+set_property port_width 1 [get_debug_ports u_ila_0/probe42]
+connect_debug_port u_ila_0/probe42 [get_nets [list axis_mac0/m_axis_rx_tvalid]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43]
+set_property port_width 1 [get_debug_ports u_ila_0/probe43]
+connect_debug_port u_ila_0/probe43 [get_nets [list axis_mac0/mac_top0/mac_tx0/mac_data_valid]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44]
+set_property port_width 1 [get_debug_ports u_ila_0/probe44]
+connect_debug_port u_ila_0/probe44 [get_nets [list axis_mac0/mac_top0/mac_tx0/mac_send_end]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45]
+set_property port_width 1 [get_debug_ports u_ila_0/probe45]
+connect_debug_port u_ila_0/probe45 [get_nets [list axis_mac0/mac_top0/mac_rx0/udp0/ram_wr_en]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46]
+set_property port_width 1 [get_debug_ports u_ila_0/probe46]
+connect_debug_port u_ila_0/probe46 [get_nets [list axis_mac0/mac_top0/mac_tx0/ram_wr_en]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47]
+set_property port_width 1 [get_debug_ports u_ila_0/probe47]
+connect_debug_port u_ila_0/probe47 [get_nets [list req_ready]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe48]
+set_property port_width 1 [get_debug_ports u_ila_0/probe48]
+connect_debug_port u_ila_0/probe48 [get_nets [list axis_mac0/req_ready]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe49]
+set_property port_width 1 [get_debug_ports u_ila_0/probe49]
+connect_debug_port u_ila_0/probe49 [get_nets [list axis_mac0/s_axis_tx_tlast]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe50]
+set_property port_width 1 [get_debug_ports u_ila_0/probe50]
+connect_debug_port u_ila_0/probe50 [get_nets [list axis_mac0/s_axis_tx_tready]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe51]
+set_property port_width 1 [get_debug_ports u_ila_0/probe51]
+connect_debug_port u_ila_0/probe51 [get_nets [list axis_mac0/s_axis_tx_tvalid]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe52]
+set_property port_width 1 [get_debug_ports u_ila_0/probe52]
+connect_debug_port u_ila_0/probe52 [get_nets [list axis_mac0/send_req]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe53]
+set_property port_width 1 [get_debug_ports u_ila_0/probe53]
+connect_debug_port u_ila_0/probe53 [get_nets [list send_req]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54]
+set_property port_width 1 [get_debug_ports u_ila_0/probe54]
+connect_debug_port u_ila_0/probe54 [get_nets [list arbi_inst/tx_buffer_inst/tx_rden]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe55]
+set_property port_width 1 [get_debug_ports u_ila_0/probe55]
+connect_debug_port u_ila_0/probe55 [get_nets [list arbi_inst/tx_buffer_inst/tx_wren]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe56]
+set_property port_width 1 [get_debug_ports u_ila_0/probe56]
+connect_debug_port u_ila_0/probe56 [get_nets [list axis_mac0/mac_top0/mac_tx0/udp_ram_data_req]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe57]
+set_property port_width 1 [get_debug_ports u_ila_0/probe57]
+connect_debug_port u_ila_0/probe57 [get_nets [list axis_mac0/mac_top0/mac_rx0/udp_rec_data_valid]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe58]
+set_property port_width 1 [get_debug_ports u_ila_0/probe58]
+connect_debug_port u_ila_0/probe58 [get_nets [list axis_mac0/mac_top0/mac_tx0/udp_tx_end]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe59]
+set_property port_width 1 [get_debug_ports u_ila_0/probe59]
+connect_debug_port u_ila_0/probe59 [get_nets [list axis_mac0/mac_top0/mac_tx0/udp_tx_req]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe60]
+set_property port_width 1 [get_debug_ports u_ila_0/probe60]
+connect_debug_port u_ila_0/probe60 [get_nets [list axis_mac0/mac_top0/mac_tx0/upper_data_req]]
+set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
+set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+connect_debug_port dbg_hub/clk [get_nets rgmii_rxc_IBUF_BUFG]

rtl/ethernet-udp/tests/eth_axis/ethernet_axis_echo.v

@@ -0,0 +1,344 @@
+// project with UDP ethernet echo
+// use axi streams from axis_mac
+// fpga IP: 192.168.0.2
+// host IP: 192.168.0.3
+
+`timescale 1 ns / 1 ns
+
+module ethernet_axis_echo
+(
+    input               sys_clk_p,
+    input               sys_clk_n,
+    input               rst_n,
+    output [3:0]        led,
+    output              e_reset,
+    output              e_mdc,
+    inout               e_mdio,
+    output [3:0]        rgmii_txd,
+    output              rgmii_txctl,
+    output              rgmii_txc,
+    input  [3:0]        rgmii_rxd,
+    input               rgmii_rxctl,
+    input               rgmii_rxc
+);
+
+    // ------------------------------------------------------------
+    // Internal GMII-side signals
+    // ------------------------------------------------------------
+    wire  [7:0] gmii_txd;
+    wire        gmii_tx_en;
+    wire        gmii_tx_er;
+    wire        gmii_tx_clk;
+    wire        gmii_crs;
+    wire        gmii_col;
+    wire  [7:0] gmii_rxd_i;
+    wire        gmii_rx_dv;
+    wire        gmii_rx_er;
+    wire        gmii_rx_clk;
+
+    wire [31:0] pack_total_len;
+
+    wire        e_rx_dv;
+    wire [7:0]  e_rxd;
+    wire        e_tx_en;
+    wire [7:0]  e_txd;
+    wire        e_rst_n;
+    wire        sys_clk;
+
+    wire        duplex_mode;
+
+    assign duplex_mode = 1'b1;
+
+    // ------------------------------------------------------------
+    // System clock buffer
+    // ------------------------------------------------------------
+    IBUFDS sys_clk_ibufgds
+    (
+        .O  (sys_clk),
+        .I  (sys_clk_p),
+        .IB (sys_clk_n)
+    );
+
+    // ------------------------------------------------------------
+    // IDELAYCTRL
+    // ------------------------------------------------------------
+    (* IODELAY_GROUP = "rgmii_idelay_group" *)
+    IDELAYCTRL IDELAYCTRL_inst (
+        .RDY(),
+        .REFCLK(sys_clk),
+        .RST(1'b0)
+    );
+
+    // ------------------------------------------------------------
+    // GMII <-> RGMII conversion
+    // ------------------------------------------------------------
+    util_gmii_to_rgmii util_gmii_to_rgmii_m0
+    (
+        .reset           (1'b0),
+        .rgmii_td        (rgmii_txd),
+        .rgmii_tx_ctl    (rgmii_txctl),
+        .rgmii_txc       (rgmii_txc),
+        .rgmii_rd        (rgmii_rxd),
+        .rgmii_rx_ctl    (rgmii_rxctl),
+        .gmii_rx_clk     (gmii_rx_clk),
+        .gmii_txd        (e_txd),
+        .gmii_tx_en      (e_tx_en),
+        .gmii_tx_er      (1'b0),
+        .gmii_tx_clk     (gmii_tx_clk),
+        .gmii_crs        (gmii_crs),
+        .gmii_col        (gmii_col),
+        .gmii_rxd        (gmii_rxd_i),
+        .rgmii_rxc       (rgmii_rxc),
+        .gmii_rx_dv      (gmii_rx_dv),
+        .gmii_rx_er      (gmii_rx_er),
+        .speed_selection (2'b10),
+        .duplex_mode     (duplex_mode)
+    );
+
+    // ------------------------------------------------------------
+    // GMII arbitration / adaptation
+    // ------------------------------------------------------------
+    gmii_arbi arbi_inst
+    (
+        .clk            (gmii_tx_clk),
+        .rst_n          (rst_n),
+        .speed          (2'b10),
+        .link           (1'b1),
+        .pack_total_len (pack_total_len),
+        .e_rst_n        (e_rst_n),
+        .gmii_rx_dv     (gmii_rx_dv),
+        .gmii_rxd       (gmii_rxd_i),
+        .gmii_tx_en     (gmii_tx_en),
+        .gmii_txd       (gmii_txd),
+        .e_rx_dv        (e_rx_dv),
+        .e_rxd          (e_rxd),
+        .e_tx_en        (e_tx_en),
+        .e_txd          (e_txd)
+    );
+
+    // ------------------------------------------------------------
+    // axis_mac interface
+    // ------------------------------------------------------------
+    (* MARK_DEBUG="true" *)wire        req_ready;
+
+    (* MARK_DEBUG="true" *)reg         send_req;
+    reg  [15:0] data_length;
+
+    reg  [7:0]  s_axis_tx_tdata;
+    reg         s_axis_tx_tvalid;
+    wire        s_axis_tx_tready;
+    reg         s_axis_tx_tlast;
+
+    wire [7:0]  m_axis_rx_tdata;
+    wire        m_axis_rx_tvalid;
+    reg         m_axis_rx_tready;
+    wire        m_axis_rx_tlast;
+
+    // ------------------------------------------------------------
+    // axis_mac
+    // ------------------------------------------------------------
+    axis_mac axis_mac0
+    (
+        .gmii_tx_clk       (gmii_tx_clk),
+        .gmii_rx_clk       (gmii_rx_clk),
+        .rst_n             (e_rst_n),
+
+        .gmii_rx_dv        (e_rx_dv),
+        .gmii_rxd          (e_rxd),
+        .gmii_tx_en        (gmii_tx_en),
+        .gmii_txd          (gmii_txd),
+
+        .send_req          (send_req),
+        .data_length       (data_length),
+        .req_ready         (req_ready),
+
+        .s_axis_tx_tdata   (s_axis_tx_tdata),
+        .s_axis_tx_tvalid  (s_axis_tx_tvalid),
+        .s_axis_tx_tready  (s_axis_tx_tready),
+        .s_axis_tx_tlast   (s_axis_tx_tlast),
+
+        .m_axis_rx_tdata   (m_axis_rx_tdata),
+        .m_axis_rx_tvalid  (m_axis_rx_tvalid),
+        .m_axis_rx_tready  (m_axis_rx_tready),
+        .m_axis_rx_tlast   (m_axis_rx_tlast)
+    );
+
+    // LEDs
+    assign led[0] = req_ready;
+    assign led[1] = !m_axis_rx_tvalid;
+    assign led[2] = !s_axis_tx_tvalid;
+    assign led[3] = e_rst_n;
+
+    // Minimal one-packet echo buffer
+    localparam BUFFER_SIZE = 256;
+    reg [7:0] pkt_mem [0:BUFFER_SIZE-1];
+
+    reg [15:0] rx_wr_ptr;
+    reg [15:0] rx_pkt_len;
+    reg        rx_pkt_pending;
+
+    // TX -> RX acknowledge toggle
+    reg tx_done_toggle;
+    reg tx_done_toggle_rx_d0, tx_done_toggle_rx_d1;
+    wire tx_done_pulse_rx;
+
+    assign tx_done_pulse_rx = tx_done_toggle_rx_d1 ^ tx_done_toggle_rx_d0;
+
+    always @(posedge gmii_rx_clk or negedge e_rst_n) begin
+        if (!e_rst_n) begin
+            tx_done_toggle_rx_d0 <= 1'b0;
+            tx_done_toggle_rx_d1 <= 1'b0;
+        end else begin
+            tx_done_toggle_rx_d0 <= tx_done_toggle;
+            tx_done_toggle_rx_d1 <= tx_done_toggle_rx_d0;
+        end
+    end
+
+    always @(posedge gmii_rx_clk or negedge e_rst_n) begin
+        if (!e_rst_n) begin
+            rx_wr_ptr        <= 16'd0;
+            rx_pkt_len       <= 16'd0;
+            rx_pkt_pending   <= 1'b0;
+            m_axis_rx_tready <= 1'b0;
+        end else begin
+            // pending lock
+            m_axis_rx_tready <= !rx_pkt_pending;
+
+            // tx free
+            if (tx_done_pulse_rx) begin
+                rx_pkt_pending <= 1'b0;
+                rx_wr_ptr      <= 16'd0;
+            end
+
+            if (m_axis_rx_tvalid && m_axis_rx_tready) begin
+                pkt_mem[rx_wr_ptr] <= m_axis_rx_tdata;
+
+                if (m_axis_rx_tlast) begin
+                    rx_pkt_len     <= rx_wr_ptr + 16'd1;
+                    rx_pkt_pending <= 1'b1;
+                end
+
+                rx_wr_ptr <= rx_wr_ptr + 16'd1;
+            end
+        end
+    end
+
+
+    // sync RX pendind to TX domain
+    reg rx_pkt_pending_tx_d0, rx_pkt_pending_tx_d1;
+
+    always @(posedge gmii_tx_clk or negedge e_rst_n) begin
+        if (!e_rst_n) begin
+            rx_pkt_pending_tx_d0 <= 1'b0;
+            rx_pkt_pending_tx_d1 <= 1'b0;
+        end else begin
+            rx_pkt_pending_tx_d0 <= rx_pkt_pending;
+            rx_pkt_pending_tx_d1 <= rx_pkt_pending_tx_d0;
+        end
+    end
+
+    wire rx_pkt_pending_tx = rx_pkt_pending_tx_d1;
+
+    // tx FSM
+    localparam TX_IDLE    = 2'd0;
+    localparam TX_REQ     = 2'd1;
+    localparam TX_STREAM  = 2'd2;
+    localparam TX_TIMEOUT = 2'd3;
+
+    // timeout counter
+    reg [3:0] timeout_cnt;
+
+    (* MARK_DEBUG="true" *) reg [1:0]  test_state;
+    reg        tx_busy;
+    reg [15:0] tx_pkt_len;
+    reg [15:0] tx_rd_ptr;
+
+    always @(posedge gmii_tx_clk or negedge e_rst_n) begin
+        if (!e_rst_n) begin
+            test_state       <= TX_IDLE;
+            tx_busy          <= 1'b0;
+            tx_pkt_len       <= 16'd0;
+            tx_rd_ptr        <= 16'd0;
+
+            send_req         <= 1'b0;
+            data_length      <= 16'd0;
+
+            s_axis_tx_tdata  <= 8'd0;
+            s_axis_tx_tvalid <= 1'b0;
+            s_axis_tx_tlast  <= 1'b0;
+
+            tx_done_toggle   <= 1'b0;
+            timeout_cnt      <= 4'b0;
+        end else begin
+            send_req <= 1'b0;
+
+            case (test_state)
+                TX_IDLE: begin
+                    s_axis_tx_tvalid <= 1'b0;
+                    s_axis_tx_tlast  <= 1'b0;
+                    tx_rd_ptr        <= 16'd0;
+                    tx_busy          <= 1'b0;
+                    timeout_cnt      <= 4'b0;
+
+                    // rx pending and ready to send
+                    if (rx_pkt_pending_tx && req_ready) begin
+                        tx_busy     <= 1'b1;
+                        tx_pkt_len  <= rx_pkt_len;   // length stable while rx_pkt_pending=1
+                        data_length <= rx_pkt_len;
+                        send_req    <= 1'b1;
+                        test_state    <= TX_REQ;
+                    end
+                end
+
+                TX_REQ: begin
+                    // await ready from axis slave
+                    if (s_axis_tx_tready) begin
+                        s_axis_tx_tdata  <= pkt_mem[0];
+                        s_axis_tx_tvalid <= 1'b1;
+                        s_axis_tx_tlast  <= (tx_pkt_len == 16'd1);
+                        tx_rd_ptr        <= 16'd0;
+                        test_state         <= TX_STREAM;
+                    end
+                end
+
+                TX_STREAM: begin
+                    // now ready to send stream
+                    if (s_axis_tx_tvalid && s_axis_tx_tready) begin
+                        if (tx_rd_ptr == tx_pkt_len - 16'd1) begin
+                            // lset
+                            s_axis_tx_tvalid <= 1'b0;
+                            s_axis_tx_tlast  <= 1'b0;
+                            tx_busy          <= 1'b0;
+                            tx_done_toggle   <= ~tx_done_toggle; 
+                            test_state         <= TX_TIMEOUT;
+                        end else begin
+                            tx_rd_ptr        <= tx_rd_ptr + 16'd1;
+                            s_axis_tx_tdata  <= pkt_mem[tx_rd_ptr + 16'd1];
+                            s_axis_tx_tlast  <= (tx_rd_ptr + 16'd1 == tx_pkt_len - 16'd1);
+                        end
+                    end
+                end
+
+                TX_TIMEOUT: begin
+                    // little timeout until signals syncs
+                    timeout_cnt <= timeout_cnt + 1;
+                    if (timeout_cnt == 4'b1111)
+                        test_state <= TX_IDLE;
+                end
+
+                default: begin
+                    test_state <= TX_IDLE;
+                end
+            endcase
+        end
+    end
+
+    // PHY reset generation
+    reset reset_m0
+    (
+        .clk   (sys_clk),
+        .key1  (rst_n),
+        .rst_n (e_reset)
+    );
+
+endmodule

rtl/ethernet-udp/tests/eth_axis/ethernet_axis_echo.xdc

@@ -0,0 +1,346 @@
+# constrains for minimal ethernet stack
+
+create_clock -period 5.000 [get_ports sys_clk_p]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_p]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_n]
+set_property PACKAGE_PIN R4 [get_ports sys_clk_p]
+set_property PACKAGE_PIN T4 [get_ports sys_clk_n]
+
+set_property PACKAGE_PIN F15 [get_ports rst_n]
+set_property IOSTANDARD LVCMOS33 [get_ports rst_n]
+
+set_property PACKAGE_PIN L13 [get_ports {led[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
+set_property PACKAGE_PIN M13 [get_ports {led[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
+set_property PACKAGE_PIN K14 [get_ports {led[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
+set_property PACKAGE_PIN K13 [get_ports {led[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
+#########################ethernet######################
+create_clock -period 8.000 [get_ports rgmii_rxc]
+set_property IOSTANDARD LVCMOS33 [get_ports {rgmii_rxd[*]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {rgmii_txd[*]}]
+set_property SLEW FAST [get_ports {rgmii_txd[*]}]
+
+set_property IOSTANDARD LVCMOS33 [get_ports e_mdc]
+set_property IOSTANDARD LVCMOS33 [get_ports e_mdio]
+set_property IOSTANDARD LVCMOS33 [get_ports e_reset]
+set_property IOSTANDARD LVCMOS33 [get_ports rgmii_rxc]
+set_property IOSTANDARD LVCMOS33 [get_ports rgmii_rxctl]
+set_property IOSTANDARD LVCMOS33 [get_ports rgmii_txc]
+set_property IOSTANDARD LVCMOS33 [get_ports rgmii_txctl]
+set_property SLEW FAST [get_ports rgmii_txc]
+set_property SLEW FAST [get_ports rgmii_txctl]
+
+set_property PACKAGE_PIN P17 [get_ports {rgmii_rxd[3]}]
+set_property PACKAGE_PIN U17 [get_ports {rgmii_rxd[2]}]
+set_property PACKAGE_PIN U18 [get_ports {rgmii_rxd[1]}]
+set_property PACKAGE_PIN P19 [get_ports {rgmii_rxd[0]}]
+set_property PACKAGE_PIN R16 [get_ports {rgmii_txd[3]}]
+set_property PACKAGE_PIN R17 [get_ports {rgmii_txd[2]}]
+set_property PACKAGE_PIN P16 [get_ports {rgmii_txd[1]}]
+set_property PACKAGE_PIN N14 [get_ports {rgmii_txd[0]}]
+set_property PACKAGE_PIN N13 [get_ports e_mdc]
+set_property PACKAGE_PIN P14 [get_ports e_mdio]
+set_property PACKAGE_PIN R14 [get_ports e_reset]
+set_property PACKAGE_PIN V18 [get_ports rgmii_rxc]
+set_property PACKAGE_PIN R19 [get_ports rgmii_rxctl]
+set_property PACKAGE_PIN P15 [get_ports rgmii_txc]
+set_property PACKAGE_PIN N17 [get_ports rgmii_txctl]
+
+
+
+
+connect_debug_port u_ila_0/clk [get_nets [list gmii_tx_clk_IBUF_BUFG]]
+connect_debug_port u_ila_0/probe0 [get_nets [list {dut/mac_top0/mac_tx0/mac_tx_data[0]} {dut/mac_top0/mac_tx0/mac_tx_data[1]} {dut/mac_top0/mac_tx0/mac_tx_data[2]} {dut/mac_top0/mac_tx0/mac_tx_data[3]} {dut/mac_top0/mac_tx0/mac_tx_data[4]} {dut/mac_top0/mac_tx0/mac_tx_data[5]} {dut/mac_top0/mac_tx0/mac_tx_data[6]} {dut/mac_top0/mac_tx0/mac_tx_data[7]}]]
+connect_debug_port u_ila_0/probe1 [get_nets [list {dut/mac_top0/mac_tx0/ram_wr_data[0]} {dut/mac_top0/mac_tx0/ram_wr_data[1]} {dut/mac_top0/mac_tx0/ram_wr_data[2]} {dut/mac_top0/mac_tx0/ram_wr_data[3]} {dut/mac_top0/mac_tx0/ram_wr_data[4]} {dut/mac_top0/mac_tx0/ram_wr_data[5]} {dut/mac_top0/mac_tx0/ram_wr_data[6]} {dut/mac_top0/mac_tx0/ram_wr_data[7]}]]
+connect_debug_port u_ila_0/probe2 [get_nets [list {dut/mac_top0/mac_tx0/udp0/usedw[0]} {dut/mac_top0/mac_tx0/udp0/usedw[1]} {dut/mac_top0/mac_tx0/udp0/usedw[2]} {dut/mac_top0/mac_tx0/udp0/usedw[3]}]]
+connect_debug_port u_ila_0/probe3 [get_nets [list {dut/mac_top0/mac_tx0/udp0/state[0]} {dut/mac_top0/mac_tx0/udp0/state[1]} {dut/mac_top0/mac_tx0/udp0/state[2]} {dut/mac_top0/mac_tx0/udp0/state[3]} {dut/mac_top0/mac_tx0/udp0/state[4]} {dut/mac_top0/mac_tx0/udp0/state[5]}]]
+connect_debug_port u_ila_0/probe4 [get_nets [list {dut/mac_top0/mac_tx0/udp_send_data_length[0]} {dut/mac_top0/mac_tx0/udp_send_data_length[1]} {dut/mac_top0/mac_tx0/udp_send_data_length[2]} {dut/mac_top0/mac_tx0/udp_send_data_length[3]} {dut/mac_top0/mac_tx0/udp_send_data_length[4]} {dut/mac_top0/mac_tx0/udp_send_data_length[5]} {dut/mac_top0/mac_tx0/udp_send_data_length[6]} {dut/mac_top0/mac_tx0/udp_send_data_length[7]} {dut/mac_top0/mac_tx0/udp_send_data_length[8]} {dut/mac_top0/mac_tx0/udp_send_data_length[9]} {dut/mac_top0/mac_tx0/udp_send_data_length[10]} {dut/mac_top0/mac_tx0/udp_send_data_length[11]} {dut/mac_top0/mac_tx0/udp_send_data_length[12]} {dut/mac_top0/mac_tx0/udp_send_data_length[13]} {dut/mac_top0/mac_tx0/udp_send_data_length[14]} {dut/mac_top0/mac_tx0/udp_send_data_length[15]}]]
+connect_debug_port u_ila_0/probe5 [get_nets [list {dut/mac_top0/mac_tx0/udp_ram_data_count[0]} {dut/mac_top0/mac_tx0/udp_ram_data_count[1]} {dut/mac_top0/mac_tx0/udp_ram_data_count[2]} {dut/mac_top0/mac_tx0/udp_ram_data_count[3]} {dut/mac_top0/mac_tx0/udp_ram_data_count[4]} {dut/mac_top0/mac_tx0/udp_ram_data_count[5]} {dut/mac_top0/mac_tx0/udp_ram_data_count[6]} {dut/mac_top0/mac_tx0/udp_ram_data_count[7]} {dut/mac_top0/mac_tx0/udp_ram_data_count[8]} {dut/mac_top0/mac_tx0/udp_ram_data_count[9]} {dut/mac_top0/mac_tx0/udp_ram_data_count[10]} {dut/mac_top0/mac_tx0/udp_ram_data_count[11]}]]
+connect_debug_port u_ila_0/probe6 [get_nets [list {dut/mac_top0/mac_tx0/udp0/ck_state[0]} {dut/mac_top0/mac_tx0/udp0/ck_state[1]} {dut/mac_top0/mac_tx0/udp0/ck_state[2]} {dut/mac_top0/mac_tx0/udp0/ck_state[3]} {dut/mac_top0/mac_tx0/udp0/ck_state[4]} {dut/mac_top0/mac_tx0/udp0/ck_state[5]}]]
+connect_debug_port u_ila_0/probe7 [get_nets [list dut/mac_top0/mac_tx0/almost_full]]
+connect_debug_port u_ila_0/probe8 [get_nets [list dut/mac_top0/mac_tx0/mac_data_valid]]
+connect_debug_port u_ila_0/probe9 [get_nets [list dut/mac_top0/mac_tx0/mac_send_end]]
+connect_debug_port u_ila_0/probe10 [get_nets [list dut/mac_top0/mac_tx0/ram_wr_en]]
+connect_debug_port u_ila_0/probe11 [get_nets [list dut/mac_top0/mac_tx0/udp_ram_data_req]]
+connect_debug_port u_ila_0/probe12 [get_nets [list dut/mac_top0/mac_tx0/udp_tx_end]]
+connect_debug_port u_ila_0/probe13 [get_nets [list dut/mac_top0/mac_tx0/udp_tx_req]]
+connect_debug_port u_ila_0/probe14 [get_nets [list dut/mac_top0/mac_tx0/upper_data_req]]
+connect_debug_port u_ila_1/clk [get_nets [list gmii_rx_clk_IBUF_BUFG]]
+connect_debug_port u_ila_1/probe0 [get_nets [list {dut/udp_rec_data_length[0]} {dut/udp_rec_data_length[1]} {dut/udp_rec_data_length[2]} {dut/udp_rec_data_length[3]} {dut/udp_rec_data_length[4]} {dut/udp_rec_data_length[5]} {dut/udp_rec_data_length[6]} {dut/udp_rec_data_length[7]} {dut/udp_rec_data_length[8]} {dut/udp_rec_data_length[9]} {dut/udp_rec_data_length[10]} {dut/udp_rec_data_length[11]} {dut/udp_rec_data_length[12]} {dut/udp_rec_data_length[13]} {dut/udp_rec_data_length[14]} {dut/udp_rec_data_length[15]}]]
+connect_debug_port u_ila_1/probe1 [get_nets [list {dut/rx_index[0]} {dut/rx_index[1]} {dut/rx_index[2]} {dut/rx_index[3]} {dut/rx_index[4]} {dut/rx_index[5]} {dut/rx_index[6]} {dut/rx_index[7]} {dut/rx_index[8]} {dut/rx_index[9]} {dut/rx_index[10]} {dut/rx_index[11]} {dut/rx_index[12]} {dut/rx_index[13]} {dut/rx_index[14]} {dut/rx_index[15]}]]
+connect_debug_port u_ila_1/probe2 [get_nets [list {dut/m_axis_rx_tdata[0]} {dut/m_axis_rx_tdata[1]} {dut/m_axis_rx_tdata[2]} {dut/m_axis_rx_tdata[3]} {dut/m_axis_rx_tdata[4]} {dut/m_axis_rx_tdata[5]} {dut/m_axis_rx_tdata[6]} {dut/m_axis_rx_tdata[7]}]]
+connect_debug_port u_ila_1/probe3 [get_nets [list {dut/rx_state[0]} {dut/rx_state[1]}]]
+connect_debug_port u_ila_1/probe4 [get_nets [list {dut/rx_payload_len[0]} {dut/rx_payload_len[1]} {dut/rx_payload_len[2]} {dut/rx_payload_len[3]} {dut/rx_payload_len[4]} {dut/rx_payload_len[5]} {dut/rx_payload_len[6]} {dut/rx_payload_len[7]} {dut/rx_payload_len[8]} {dut/rx_payload_len[9]} {dut/rx_payload_len[10]} {dut/rx_payload_len[11]} {dut/rx_payload_len[12]} {dut/rx_payload_len[13]} {dut/rx_payload_len[14]} {dut/rx_payload_len[15]}]]
+connect_debug_port u_ila_1/probe5 [get_nets [list {dut/mac_top0/mac_rx0/ip_total_data_length[0]} {dut/mac_top0/mac_rx0/ip_total_data_length[1]} {dut/mac_top0/mac_rx0/ip_total_data_length[2]} {dut/mac_top0/mac_rx0/ip_total_data_length[3]} {dut/mac_top0/mac_rx0/ip_total_data_length[4]} {dut/mac_top0/mac_rx0/ip_total_data_length[5]} {dut/mac_top0/mac_rx0/ip_total_data_length[6]} {dut/mac_top0/mac_rx0/ip_total_data_length[7]} {dut/mac_top0/mac_rx0/ip_total_data_length[8]} {dut/mac_top0/mac_rx0/ip_total_data_length[9]} {dut/mac_top0/mac_rx0/ip_total_data_length[10]} {dut/mac_top0/mac_rx0/ip_total_data_length[11]} {dut/mac_top0/mac_rx0/ip_total_data_length[12]} {dut/mac_top0/mac_rx0/ip_total_data_length[13]} {dut/mac_top0/mac_rx0/ip_total_data_length[14]} {dut/mac_top0/mac_rx0/ip_total_data_length[15]}]]
+connect_debug_port u_ila_1/probe6 [get_nets [list {dut/mac_top0/mac_rx0/upper_layer_data_length[0]} {dut/mac_top0/mac_rx0/upper_layer_data_length[1]} {dut/mac_top0/mac_rx0/upper_layer_data_length[2]} {dut/mac_top0/mac_rx0/upper_layer_data_length[3]} {dut/mac_top0/mac_rx0/upper_layer_data_length[4]} {dut/mac_top0/mac_rx0/upper_layer_data_length[5]} {dut/mac_top0/mac_rx0/upper_layer_data_length[6]} {dut/mac_top0/mac_rx0/upper_layer_data_length[7]} {dut/mac_top0/mac_rx0/upper_layer_data_length[8]} {dut/mac_top0/mac_rx0/upper_layer_data_length[9]} {dut/mac_top0/mac_rx0/upper_layer_data_length[10]} {dut/mac_top0/mac_rx0/upper_layer_data_length[11]} {dut/mac_top0/mac_rx0/upper_layer_data_length[12]} {dut/mac_top0/mac_rx0/upper_layer_data_length[13]} {dut/mac_top0/mac_rx0/upper_layer_data_length[14]} {dut/mac_top0/mac_rx0/upper_layer_data_length[15]}]]
+connect_debug_port u_ila_1/probe7 [get_nets [list {dut/mac_top0/mac_rx0/udp_rec_ram_read_addr[0]} {dut/mac_top0/mac_rx0/udp_rec_ram_read_addr[1]} {dut/mac_top0/mac_rx0/udp_rec_ram_read_addr[2]} {dut/mac_top0/mac_rx0/udp_rec_ram_read_addr[3]} {dut/mac_top0/mac_rx0/udp_rec_ram_read_addr[4]} {dut/mac_top0/mac_rx0/udp_rec_ram_read_addr[5]} {dut/mac_top0/mac_rx0/udp_rec_ram_read_addr[6]} {dut/mac_top0/mac_rx0/udp_rec_ram_read_addr[7]} {dut/mac_top0/mac_rx0/udp_rec_ram_read_addr[8]} {dut/mac_top0/mac_rx0/udp_rec_ram_read_addr[9]} {dut/mac_top0/mac_rx0/udp_rec_ram_read_addr[10]}]]
+connect_debug_port u_ila_1/probe8 [get_nets [list {dut/mac_top0/mac_rx0/mac_rx_datain[0]} {dut/mac_top0/mac_rx0/mac_rx_datain[1]} {dut/mac_top0/mac_rx0/mac_rx_datain[2]} {dut/mac_top0/mac_rx0/mac_rx_datain[3]} {dut/mac_top0/mac_rx0/mac_rx_datain[4]} {dut/mac_top0/mac_rx0/mac_rx_datain[5]} {dut/mac_top0/mac_rx0/mac_rx_datain[6]} {dut/mac_top0/mac_rx0/mac_rx_datain[7]}]]
+connect_debug_port u_ila_1/probe9 [get_nets [list {dut/mac_top0/mac_rx0/udp_rec_ram_rdata[0]} {dut/mac_top0/mac_rx0/udp_rec_ram_rdata[1]} {dut/mac_top0/mac_rx0/udp_rec_ram_rdata[2]} {dut/mac_top0/mac_rx0/udp_rec_ram_rdata[3]} {dut/mac_top0/mac_rx0/udp_rec_ram_rdata[4]} {dut/mac_top0/mac_rx0/udp_rec_ram_rdata[5]} {dut/mac_top0/mac_rx0/udp_rec_ram_rdata[6]} {dut/mac_top0/mac_rx0/udp_rec_ram_rdata[7]}]]
+connect_debug_port u_ila_1/probe10 [get_nets [list {dut/mac_top0/mac_rx0/mac_rx_dataout[0]} {dut/mac_top0/mac_rx0/mac_rx_dataout[1]} {dut/mac_top0/mac_rx0/mac_rx_dataout[2]} {dut/mac_top0/mac_rx0/mac_rx_dataout[3]} {dut/mac_top0/mac_rx0/mac_rx_dataout[4]} {dut/mac_top0/mac_rx0/mac_rx_dataout[5]} {dut/mac_top0/mac_rx0/mac_rx_dataout[6]} {dut/mac_top0/mac_rx0/mac_rx_dataout[7]}]]
+connect_debug_port u_ila_1/probe11 [get_nets [list {dut/mac_top0/mac_rx0/udp_rec_data_length[0]} {dut/mac_top0/mac_rx0/udp_rec_data_length[1]} {dut/mac_top0/mac_rx0/udp_rec_data_length[2]} {dut/mac_top0/mac_rx0/udp_rec_data_length[3]} {dut/mac_top0/mac_rx0/udp_rec_data_length[4]} {dut/mac_top0/mac_rx0/udp_rec_data_length[5]} {dut/mac_top0/mac_rx0/udp_rec_data_length[6]} {dut/mac_top0/mac_rx0/udp_rec_data_length[7]} {dut/mac_top0/mac_rx0/udp_rec_data_length[8]} {dut/mac_top0/mac_rx0/udp_rec_data_length[9]} {dut/mac_top0/mac_rx0/udp_rec_data_length[10]} {dut/mac_top0/mac_rx0/udp_rec_data_length[11]} {dut/mac_top0/mac_rx0/udp_rec_data_length[12]} {dut/mac_top0/mac_rx0/udp_rec_data_length[13]} {dut/mac_top0/mac_rx0/udp_rec_data_length[14]} {dut/mac_top0/mac_rx0/udp_rec_data_length[15]}]]
+connect_debug_port u_ila_1/probe12 [get_nets [list {dut/mac_top0/mac_rx0/udp0/ram_write_addr[0]} {dut/mac_top0/mac_rx0/udp0/ram_write_addr[1]} {dut/mac_top0/mac_rx0/udp0/ram_write_addr[2]} {dut/mac_top0/mac_rx0/udp0/ram_write_addr[3]} {dut/mac_top0/mac_rx0/udp0/ram_write_addr[4]} {dut/mac_top0/mac_rx0/udp0/ram_write_addr[5]} {dut/mac_top0/mac_rx0/udp0/ram_write_addr[6]} {dut/mac_top0/mac_rx0/udp0/ram_write_addr[7]} {dut/mac_top0/mac_rx0/udp0/ram_write_addr[8]} {dut/mac_top0/mac_rx0/udp0/ram_write_addr[9]} {dut/mac_top0/mac_rx0/udp0/ram_write_addr[10]}]]
+connect_debug_port u_ila_1/probe13 [get_nets [list dut/m_axis_rx_tlast]]
+connect_debug_port u_ila_1/probe14 [get_nets [list dut/m_axis_rx_tvalid]]
+connect_debug_port u_ila_1/probe15 [get_nets [list dut/mac_top0/mac_rx0/udp0/ram_wr_en]]
+connect_debug_port u_ila_1/probe16 [get_nets [list dut/mac_top0/mac_rx0/udp_rec_data_valid]]
+connect_debug_port dbg_hub/clk [get_nets gmii_rx_clk_IBUF_BUFG]
+
+
+
+connect_debug_port u_ila_0/probe4 [get_nets [list {tx_state[0]} {tx_state[1]}]]
+
+connect_debug_port u_ila_0/probe48 [get_nets [list rx_pkt_pulse_tx]]
+
+create_debug_core u_ila_0 ila
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
+set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
+set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
+set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
+set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
+set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
+set_property port_width 1 [get_debug_ports u_ila_0/clk]
+connect_debug_port u_ila_0/clk [get_nets [list rgmii_rxc_IBUF_BUFG]]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
+set_property port_width 8 [get_debug_ports u_ila_0/probe0]
+connect_debug_port u_ila_0/probe0 [get_nets [list {axis_mac0/mac_top0/mac_tx0/ram_wr_data[0]} {axis_mac0/mac_top0/mac_tx0/ram_wr_data[1]} {axis_mac0/mac_top0/mac_tx0/ram_wr_data[2]} {axis_mac0/mac_top0/mac_tx0/ram_wr_data[3]} {axis_mac0/mac_top0/mac_tx0/ram_wr_data[4]} {axis_mac0/mac_top0/mac_tx0/ram_wr_data[5]} {axis_mac0/mac_top0/mac_tx0/ram_wr_data[6]} {axis_mac0/mac_top0/mac_tx0/ram_wr_data[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
+set_property port_width 8 [get_debug_ports u_ila_0/probe1]
+connect_debug_port u_ila_0/probe1 [get_nets [list {axis_mac0/mac_top0/mac_tx0/mac_tx_data[0]} {axis_mac0/mac_top0/mac_tx0/mac_tx_data[1]} {axis_mac0/mac_top0/mac_tx0/mac_tx_data[2]} {axis_mac0/mac_top0/mac_tx0/mac_tx_data[3]} {axis_mac0/mac_top0/mac_tx0/mac_tx_data[4]} {axis_mac0/mac_top0/mac_tx0/mac_tx_data[5]} {axis_mac0/mac_top0/mac_tx0/mac_tx_data[6]} {axis_mac0/mac_top0/mac_tx0/mac_tx_data[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
+set_property port_width 16 [get_debug_ports u_ila_0/probe2]
+connect_debug_port u_ila_0/probe2 [get_nets [list {axis_mac0/rx_payload_len[0]} {axis_mac0/rx_payload_len[1]} {axis_mac0/rx_payload_len[2]} {axis_mac0/rx_payload_len[3]} {axis_mac0/rx_payload_len[4]} {axis_mac0/rx_payload_len[5]} {axis_mac0/rx_payload_len[6]} {axis_mac0/rx_payload_len[7]} {axis_mac0/rx_payload_len[8]} {axis_mac0/rx_payload_len[9]} {axis_mac0/rx_payload_len[10]} {axis_mac0/rx_payload_len[11]} {axis_mac0/rx_payload_len[12]} {axis_mac0/rx_payload_len[13]} {axis_mac0/rx_payload_len[14]} {axis_mac0/rx_payload_len[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
+set_property port_width 16 [get_debug_ports u_ila_0/probe3]
+connect_debug_port u_ila_0/probe3 [get_nets [list {axis_mac0/rx_index[0]} {axis_mac0/rx_index[1]} {axis_mac0/rx_index[2]} {axis_mac0/rx_index[3]} {axis_mac0/rx_index[4]} {axis_mac0/rx_index[5]} {axis_mac0/rx_index[6]} {axis_mac0/rx_index[7]} {axis_mac0/rx_index[8]} {axis_mac0/rx_index[9]} {axis_mac0/rx_index[10]} {axis_mac0/rx_index[11]} {axis_mac0/rx_index[12]} {axis_mac0/rx_index[13]} {axis_mac0/rx_index[14]} {axis_mac0/rx_index[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
+set_property port_width 16 [get_debug_ports u_ila_0/probe4]
+connect_debug_port u_ila_0/probe4 [get_nets [list {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[0]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[1]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[2]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[3]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[4]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[5]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[6]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[7]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[8]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[9]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[10]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[11]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[12]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[13]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[14]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
+set_property port_width 12 [get_debug_ports u_ila_0/probe5]
+connect_debug_port u_ila_0/probe5 [get_nets [list {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[0]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[1]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[2]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[3]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[4]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[5]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[6]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[7]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[8]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[9]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[10]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[11]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
+set_property port_width 11 [get_debug_ports u_ila_0/probe6]
+connect_debug_port u_ila_0/probe6 [get_nets [list {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[0]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[1]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[2]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[3]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[4]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[5]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[6]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[7]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[8]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[9]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[10]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
+set_property port_width 8 [get_debug_ports u_ila_0/probe7]
+connect_debug_port u_ila_0/probe7 [get_nets [list {arbi_inst/e_txd[0]} {arbi_inst/e_txd[1]} {arbi_inst/e_txd[2]} {arbi_inst/e_txd[3]} {arbi_inst/e_txd[4]} {arbi_inst/e_txd[5]} {arbi_inst/e_txd[6]} {arbi_inst/e_txd[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
+set_property port_width 8 [get_debug_ports u_ila_0/probe8]
+connect_debug_port u_ila_0/probe8 [get_nets [list {arbi_inst/tx_buffer_inst/tx_rdata[0]} {arbi_inst/tx_buffer_inst/tx_rdata[1]} {arbi_inst/tx_buffer_inst/tx_rdata[2]} {arbi_inst/tx_buffer_inst/tx_rdata[3]} {arbi_inst/tx_buffer_inst/tx_rdata[4]} {arbi_inst/tx_buffer_inst/tx_rdata[5]} {arbi_inst/tx_buffer_inst/tx_rdata[6]} {arbi_inst/tx_buffer_inst/tx_rdata[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
+set_property port_width 16 [get_debug_ports u_ila_0/probe9]
+connect_debug_port u_ila_0/probe9 [get_nets [list {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[0]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[1]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[2]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[3]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[4]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[5]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[6]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[7]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[8]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[9]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[10]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[11]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[12]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[13]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[14]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
+set_property port_width 8 [get_debug_ports u_ila_0/probe10]
+connect_debug_port u_ila_0/probe10 [get_nets [list {axis_mac0/m_axis_rx_tdata[0]} {axis_mac0/m_axis_rx_tdata[1]} {axis_mac0/m_axis_rx_tdata[2]} {axis_mac0/m_axis_rx_tdata[3]} {axis_mac0/m_axis_rx_tdata[4]} {axis_mac0/m_axis_rx_tdata[5]} {axis_mac0/m_axis_rx_tdata[6]} {axis_mac0/m_axis_rx_tdata[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
+set_property port_width 8 [get_debug_ports u_ila_0/probe11]
+connect_debug_port u_ila_0/probe11 [get_nets [list {arbi_inst/rx_buffer_inst/e10_100_rxd[0]} {arbi_inst/rx_buffer_inst/e10_100_rxd[1]} {arbi_inst/rx_buffer_inst/e10_100_rxd[2]} {arbi_inst/rx_buffer_inst/e10_100_rxd[3]} {arbi_inst/rx_buffer_inst/e10_100_rxd[4]} {arbi_inst/rx_buffer_inst/e10_100_rxd[5]} {arbi_inst/rx_buffer_inst/e10_100_rxd[6]} {arbi_inst/rx_buffer_inst/e10_100_rxd[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
+set_property port_width 8 [get_debug_ports u_ila_0/probe12]
+connect_debug_port u_ila_0/probe12 [get_nets [list {axis_mac0/s_axis_tx_tdata[0]} {axis_mac0/s_axis_tx_tdata[1]} {axis_mac0/s_axis_tx_tdata[2]} {axis_mac0/s_axis_tx_tdata[3]} {axis_mac0/s_axis_tx_tdata[4]} {axis_mac0/s_axis_tx_tdata[5]} {axis_mac0/s_axis_tx_tdata[6]} {axis_mac0/s_axis_tx_tdata[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
+set_property port_width 11 [get_debug_ports u_ila_0/probe13]
+connect_debug_port u_ila_0/probe13 [get_nets [list {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[0]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[1]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[2]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[3]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[4]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[5]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[6]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[7]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[8]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[9]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[10]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
+set_property port_width 8 [get_debug_ports u_ila_0/probe14]
+connect_debug_port u_ila_0/probe14 [get_nets [list {arbi_inst/e_rxd[0]} {arbi_inst/e_rxd[1]} {arbi_inst/e_rxd[2]} {arbi_inst/e_rxd[3]} {arbi_inst/e_rxd[4]} {arbi_inst/e_rxd[5]} {arbi_inst/e_rxd[6]} {arbi_inst/e_rxd[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
+set_property port_width 8 [get_debug_ports u_ila_0/probe15]
+connect_debug_port u_ila_0/probe15 [get_nets [list {arbi_inst/gmii_txd[0]} {arbi_inst/gmii_txd[1]} {arbi_inst/gmii_txd[2]} {arbi_inst/gmii_txd[3]} {arbi_inst/gmii_txd[4]} {arbi_inst/gmii_txd[5]} {arbi_inst/gmii_txd[6]} {arbi_inst/gmii_txd[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
+set_property port_width 16 [get_debug_ports u_ila_0/probe16]
+connect_debug_port u_ila_0/probe16 [get_nets [list {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[0]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[1]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[2]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[3]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[4]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[5]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[6]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[7]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[8]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[9]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[10]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[11]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[12]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[13]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[14]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
+set_property port_width 2 [get_debug_ports u_ila_0/probe17]
+connect_debug_port u_ila_0/probe17 [get_nets [list {test_state[0]} {test_state[1]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
+set_property port_width 8 [get_debug_ports u_ila_0/probe18]
+connect_debug_port u_ila_0/probe18 [get_nets [list {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[0]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[1]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[2]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[3]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[4]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[5]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[6]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
+set_property port_width 6 [get_debug_ports u_ila_0/probe19]
+connect_debug_port u_ila_0/probe19 [get_nets [list {axis_mac0/mac_top0/mac_tx0/udp0/state[0]} {axis_mac0/mac_top0/mac_tx0/udp0/state[1]} {axis_mac0/mac_top0/mac_tx0/udp0/state[2]} {axis_mac0/mac_top0/mac_tx0/udp0/state[3]} {axis_mac0/mac_top0/mac_tx0/udp0/state[4]} {axis_mac0/mac_top0/mac_tx0/udp0/state[5]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
+set_property port_width 8 [get_debug_ports u_ila_0/probe20]
+connect_debug_port u_ila_0/probe20 [get_nets [list {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[0]} {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[1]} {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[2]} {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[3]} {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[4]} {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[5]} {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[6]} {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
+set_property port_width 16 [get_debug_ports u_ila_0/probe21]
+connect_debug_port u_ila_0/probe21 [get_nets [list {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[0]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[1]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[2]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[3]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[4]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[5]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[6]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[7]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[8]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[9]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[10]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[11]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[12]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[13]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[14]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
+set_property port_width 4 [get_debug_ports u_ila_0/probe22]
+connect_debug_port u_ila_0/probe22 [get_nets [list {axis_mac0/mac_top0/mac_tx0/udp0/usedw[0]} {axis_mac0/mac_top0/mac_tx0/udp0/usedw[1]} {axis_mac0/mac_top0/mac_tx0/udp0/usedw[2]} {axis_mac0/mac_top0/mac_tx0/udp0/usedw[3]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
+set_property port_width 6 [get_debug_ports u_ila_0/probe23]
+connect_debug_port u_ila_0/probe23 [get_nets [list {axis_mac0/mac_top0/mac_tx0/udp0/ck_state[0]} {axis_mac0/mac_top0/mac_tx0/udp0/ck_state[1]} {axis_mac0/mac_top0/mac_tx0/udp0/ck_state[2]} {axis_mac0/mac_top0/mac_tx0/udp0/ck_state[3]} {axis_mac0/mac_top0/mac_tx0/udp0/ck_state[4]} {axis_mac0/mac_top0/mac_tx0/udp0/ck_state[5]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
+set_property port_width 8 [get_debug_ports u_ila_0/probe24]
+connect_debug_port u_ila_0/probe24 [get_nets [list {arbi_inst/gmii_rxd[0]} {arbi_inst/gmii_rxd[1]} {arbi_inst/gmii_rxd[2]} {arbi_inst/gmii_rxd[3]} {arbi_inst/gmii_rxd[4]} {arbi_inst/gmii_rxd[5]} {arbi_inst/gmii_rxd[6]} {arbi_inst/gmii_rxd[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
+set_property port_width 2 [get_debug_ports u_ila_0/probe25]
+connect_debug_port u_ila_0/probe25 [get_nets [list {axis_mac0/rx_state[0]} {axis_mac0/rx_state[1]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
+set_property port_width 8 [get_debug_ports u_ila_0/probe26]
+connect_debug_port u_ila_0/probe26 [get_nets [list {arbi_inst/tx_buffer_inst/tx_wdata[0]} {arbi_inst/tx_buffer_inst/tx_wdata[1]} {arbi_inst/tx_buffer_inst/tx_wdata[2]} {arbi_inst/tx_buffer_inst/tx_wdata[3]} {arbi_inst/tx_buffer_inst/tx_wdata[4]} {arbi_inst/tx_buffer_inst/tx_wdata[5]} {arbi_inst/tx_buffer_inst/tx_wdata[6]} {arbi_inst/tx_buffer_inst/tx_wdata[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
+set_property port_width 8 [get_debug_ports u_ila_0/probe27]
+connect_debug_port u_ila_0/probe27 [get_nets [list {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[0]} {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[1]} {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[2]} {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[3]} {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[4]} {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[5]} {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[6]} {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
+set_property port_width 3 [get_debug_ports u_ila_0/probe28]
+connect_debug_port u_ila_0/probe28 [get_nets [list {axis_mac0/tx_state[0]} {axis_mac0/tx_state[1]} {axis_mac0/tx_state[2]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
+set_property port_width 16 [get_debug_ports u_ila_0/probe29]
+connect_debug_port u_ila_0/probe29 [get_nets [list {arbi_inst/tx_buffer_inst/tx_data_cnt[0]} {arbi_inst/tx_buffer_inst/tx_data_cnt[1]} {arbi_inst/tx_buffer_inst/tx_data_cnt[2]} {arbi_inst/tx_buffer_inst/tx_data_cnt[3]} {arbi_inst/tx_buffer_inst/tx_data_cnt[4]} {arbi_inst/tx_buffer_inst/tx_data_cnt[5]} {arbi_inst/tx_buffer_inst/tx_data_cnt[6]} {arbi_inst/tx_buffer_inst/tx_data_cnt[7]} {arbi_inst/tx_buffer_inst/tx_data_cnt[8]} {arbi_inst/tx_buffer_inst/tx_data_cnt[9]} {arbi_inst/tx_buffer_inst/tx_data_cnt[10]} {arbi_inst/tx_buffer_inst/tx_data_cnt[11]} {arbi_inst/tx_buffer_inst/tx_data_cnt[12]} {arbi_inst/tx_buffer_inst/tx_data_cnt[13]} {arbi_inst/tx_buffer_inst/tx_data_cnt[14]} {arbi_inst/tx_buffer_inst/tx_data_cnt[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
+set_property port_width 16 [get_debug_ports u_ila_0/probe30]
+connect_debug_port u_ila_0/probe30 [get_nets [list {axis_mac0/udp_rec_data_length[0]} {axis_mac0/udp_rec_data_length[1]} {axis_mac0/udp_rec_data_length[2]} {axis_mac0/udp_rec_data_length[3]} {axis_mac0/udp_rec_data_length[4]} {axis_mac0/udp_rec_data_length[5]} {axis_mac0/udp_rec_data_length[6]} {axis_mac0/udp_rec_data_length[7]} {axis_mac0/udp_rec_data_length[8]} {axis_mac0/udp_rec_data_length[9]} {axis_mac0/udp_rec_data_length[10]} {axis_mac0/udp_rec_data_length[11]} {axis_mac0/udp_rec_data_length[12]} {axis_mac0/udp_rec_data_length[13]} {axis_mac0/udp_rec_data_length[14]} {axis_mac0/udp_rec_data_length[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
+set_property port_width 1 [get_debug_ports u_ila_0/probe31]
+connect_debug_port u_ila_0/probe31 [get_nets [list axis_mac0/mac_top0/mac_tx0/almost_full]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
+set_property port_width 1 [get_debug_ports u_ila_0/probe32]
+connect_debug_port u_ila_0/probe32 [get_nets [list axis_mac0/arp_found]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
+set_property port_width 1 [get_debug_ports u_ila_0/probe33]
+connect_debug_port u_ila_0/probe33 [get_nets [list arbi_inst/rx_buffer_inst/e10_100_rx_dv]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
+set_property port_width 1 [get_debug_ports u_ila_0/probe34]
+connect_debug_port u_ila_0/probe34 [get_nets [list arbi_inst/e_rx_dv]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
+set_property port_width 1 [get_debug_ports u_ila_0/probe35]
+connect_debug_port u_ila_0/probe35 [get_nets [list arbi_inst/e_tx_en]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
+set_property port_width 1 [get_debug_ports u_ila_0/probe36]
+connect_debug_port u_ila_0/probe36 [get_nets [list arbi_inst/gmii_rx_dv]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
+set_property port_width 1 [get_debug_ports u_ila_0/probe37]
+connect_debug_port u_ila_0/probe37 [get_nets [list arbi_inst/rx_buffer_inst/gmii_rx_dv_d0]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
+set_property port_width 1 [get_debug_ports u_ila_0/probe38]
+connect_debug_port u_ila_0/probe38 [get_nets [list arbi_inst/rx_buffer_inst/gmii_rx_dv_d1]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39]
+set_property port_width 1 [get_debug_ports u_ila_0/probe39]
+connect_debug_port u_ila_0/probe39 [get_nets [list arbi_inst/gmii_tx_en]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40]
+set_property port_width 1 [get_debug_ports u_ila_0/probe40]
+connect_debug_port u_ila_0/probe40 [get_nets [list axis_mac0/m_axis_rx_tlast]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41]
+set_property port_width 1 [get_debug_ports u_ila_0/probe41]
+connect_debug_port u_ila_0/probe41 [get_nets [list axis_mac0/m_axis_rx_tready]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42]
+set_property port_width 1 [get_debug_ports u_ila_0/probe42]
+connect_debug_port u_ila_0/probe42 [get_nets [list axis_mac0/m_axis_rx_tvalid]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43]
+set_property port_width 1 [get_debug_ports u_ila_0/probe43]
+connect_debug_port u_ila_0/probe43 [get_nets [list axis_mac0/mac_top0/mac_tx0/mac_data_valid]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44]
+set_property port_width 1 [get_debug_ports u_ila_0/probe44]
+connect_debug_port u_ila_0/probe44 [get_nets [list axis_mac0/mac_top0/mac_tx0/mac_send_end]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45]
+set_property port_width 1 [get_debug_ports u_ila_0/probe45]
+connect_debug_port u_ila_0/probe45 [get_nets [list axis_mac0/mac_top0/mac_tx0/ram_wr_en]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46]
+set_property port_width 1 [get_debug_ports u_ila_0/probe46]
+connect_debug_port u_ila_0/probe46 [get_nets [list axis_mac0/mac_top0/mac_rx0/udp0/ram_wr_en]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47]
+set_property port_width 1 [get_debug_ports u_ila_0/probe47]
+connect_debug_port u_ila_0/probe47 [get_nets [list req_ready]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe48]
+set_property port_width 1 [get_debug_ports u_ila_0/probe48]
+connect_debug_port u_ila_0/probe48 [get_nets [list axis_mac0/s_axis_tx_tlast]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe49]
+set_property port_width 1 [get_debug_ports u_ila_0/probe49]
+connect_debug_port u_ila_0/probe49 [get_nets [list axis_mac0/s_axis_tx_tready]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe50]
+set_property port_width 1 [get_debug_ports u_ila_0/probe50]
+connect_debug_port u_ila_0/probe50 [get_nets [list axis_mac0/s_axis_tx_tvalid]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe51]
+set_property port_width 1 [get_debug_ports u_ila_0/probe51]
+connect_debug_port u_ila_0/probe51 [get_nets [list send_req]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe52]
+set_property port_width 1 [get_debug_ports u_ila_0/probe52]
+connect_debug_port u_ila_0/probe52 [get_nets [list arbi_inst/tx_buffer_inst/tx_rden]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe53]
+set_property port_width 1 [get_debug_ports u_ila_0/probe53]
+connect_debug_port u_ila_0/probe53 [get_nets [list arbi_inst/tx_buffer_inst/tx_wren]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54]
+set_property port_width 1 [get_debug_ports u_ila_0/probe54]
+connect_debug_port u_ila_0/probe54 [get_nets [list axis_mac0/mac_top0/mac_tx0/udp_ram_data_req]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe55]
+set_property port_width 1 [get_debug_ports u_ila_0/probe55]
+connect_debug_port u_ila_0/probe55 [get_nets [list axis_mac0/mac_top0/mac_rx0/udp_rec_data_valid]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe56]
+set_property port_width 1 [get_debug_ports u_ila_0/probe56]
+connect_debug_port u_ila_0/probe56 [get_nets [list axis_mac0/mac_top0/mac_tx0/udp_tx_end]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe57]
+set_property port_width 1 [get_debug_ports u_ila_0/probe57]
+connect_debug_port u_ila_0/probe57 [get_nets [list axis_mac0/mac_top0/mac_tx0/udp_tx_req]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe58]
+set_property port_width 1 [get_debug_ports u_ila_0/probe58]
+connect_debug_port u_ila_0/probe58 [get_nets [list axis_mac0/mac_top0/mac_tx0/upper_data_req]]
+set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
+set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+connect_debug_port dbg_hub/clk [get_nets rgmii_rxc_IBUF_BUFG]

rtl/ethernet-udp/tests/eth_axis/test_axis_mac_rx.sv

@@ -0,0 +1,259 @@
+`timescale 1ns / 1ps
+
+module tb_mac_test;
+
+    reg         rst_n = 1'b0;
+    reg         gmii_rx_clk = 1'b0;
+    reg         gmii_tx_clk = 1'b0;
+    reg         gmii_rx_dv = 1'b0;
+    reg  [7:0]  gmii_rxd = 8'h00;
+
+    wire        gmii_tx_en;
+    wire [7:0]  gmii_txd;
+
+    // rx axis
+    wire [7:0]  m_axis_rx_tdata;
+    wire        m_axis_rx_tvalid;
+    reg         m_axis_rx_tready = 1'b0;
+    wire        m_axis_rx_tlast;
+
+    // tx axis
+    reg  [7:0]  s_axis_tx_tdata;
+    reg         s_axis_tx_tvalid;
+    wire        s_axis_tx_tready = 1'b0;
+    reg         s_axis_tx_tlast;
+
+    reg send_req;
+    wire req_ready;
+
+    reg [15:0] udp_rec_data_length;
+    
+    int cnt = 0;
+
+
+    // DUT
+    axis_mac dut (
+        .rst_n(rst_n),
+        .gmii_tx_clk(gmii_tx_clk),
+        .gmii_rx_clk(gmii_rx_clk),
+        .gmii_rx_dv(gmii_rx_dv),
+        .gmii_rxd(gmii_rxd),
+        .gmii_tx_en(gmii_tx_en),
+        .gmii_txd(gmii_txd),
+        .m_axis_rx_tdata(m_axis_rx_tdata),
+        .m_axis_rx_tvalid(m_axis_rx_tvalid),
+        .m_axis_rx_tready(m_axis_rx_tready),
+        .m_axis_rx_tlast(m_axis_rx_tlast),
+        .s_axis_tx_tdata(s_axis_tx_tdata),
+        .s_axis_tx_tvalid(s_axis_tx_tvalid),
+        .s_axis_tx_tready(s_axis_tx_tready),
+        .s_axis_tx_tlast(s_axis_tx_tlast),
+        .send_req(send_req),
+        .req_ready(req_ready),
+        .udp_rec_data_length(udp_rec_data_length)
+
+    );
+
+    // Clocks
+    always #4 gmii_rx_clk = ~gmii_rx_clk;
+    always #4 gmii_tx_clk = ~gmii_tx_clk;
+
+    // Helpers
+    task automatic gmii_idle;
+        input integer cycles;
+        integer i;
+        begin
+            gmii_rx_dv <= 1'b0;
+            gmii_rxd   <= 8'h00;
+            for (i = 0; i < cycles; i = i + 1) begin
+                @(posedge gmii_rx_clk);
+            end
+        end
+    endtask
+
+    task automatic send_gmii_byte;
+        input [7:0] b;
+        begin
+            @(posedge gmii_rx_clk);
+            gmii_rx_dv <= 1'b1;
+            gmii_rxd   <= b;
+        end
+    endtask
+
+    task automatic end_gmii_frame;
+        begin
+            @(posedge gmii_rx_clk);
+            gmii_rx_dv <= 1'b0;
+            gmii_rxd   <= 8'h00;
+        end
+    endtask
+
+    task automatic send_gmii_frame;
+        input integer frame_len;
+        input [8*2048-1:0] frame_data_flat;
+        integer i;
+        reg [7:0] current_byte;
+        begin
+            gmii_idle(12);
+
+            for (i = 0; i < frame_len; i = i + 1) begin
+                current_byte = frame_data_flat[i*8 +: 8];
+                send_gmii_byte(current_byte);
+            end
+
+            end_gmii_frame();
+
+            // inter-frame gap
+            gmii_idle(12);
+        end
+    endtask
+
+    reg [7:0] frame_mem [0:2047];
+
+    task automatic send_gmii_frame_mem;
+        input integer frame_len;
+        integer i;
+        begin
+            gmii_idle(12);
+
+            for (i = 0; i < frame_len; i = i + 1) begin
+                send_gmii_byte(frame_mem[i]);
+            end
+
+            end_gmii_frame();
+            gmii_idle(12);
+        end
+    endtask
+
+    // Monitor AXIS RX
+    always @(posedge gmii_rx_clk) begin
+        if (m_axis_rx_tvalid && m_axis_rx_tready) begin
+            $write("%02x ", m_axis_rx_tdata);
+            if (m_axis_rx_tlast)
+                $write("<TLAST>");
+        end
+        cnt = cnt + 1;
+        if (cnt % 8 < 6) begin
+            m_axis_rx_tready = 1'b1;
+        end else m_axis_rx_tready = 1'b0;
+    end
+
+    // Test sequence
+    integer i;
+
+    initial begin
+        // init
+        gmii_rx_dv = 1'b0;
+        gmii_rxd   = 8'h00;
+        rst_n      = 1'b0;
+
+        gmii_idle(200);
+        rst_n = 1'b1;
+        gmii_idle(200);
+
+                
+        frame_mem[0]  = 8'h55;
+        frame_mem[1]  = 8'h55;
+        frame_mem[2]  = 8'h55;
+        frame_mem[3]  = 8'h55;
+        frame_mem[4]  = 8'h55;
+        frame_mem[5]  = 8'h55;
+        frame_mem[6]  = 8'h55;
+        frame_mem[7]  = 8'hd5;
+
+        frame_mem[8]  = 8'h00;
+        frame_mem[9]  = 8'h0a;
+        frame_mem[10] = 8'h35;
+        frame_mem[11] = 8'h01;
+        frame_mem[12] = 8'hfe;
+        frame_mem[13] = 8'hc0;
+
+        frame_mem[14] = 8'h30;
+        frame_mem[15] = 8'h56;
+        frame_mem[16] = 8'h0f;
+        frame_mem[17] = 8'ha0;
+        frame_mem[18] = 8'h12;
+        frame_mem[19] = 8'hec;
+
+        frame_mem[20] = 8'h08;
+        frame_mem[21] = 8'h00;
+
+        frame_mem[22] = 8'h45;
+        frame_mem[23] = 8'h00;
+        frame_mem[24] = 8'h00;
+        frame_mem[25] = 8'h23;
+        frame_mem[26] = 8'h65;
+        frame_mem[27] = 8'hfa;
+        frame_mem[28] = 8'h40;
+        frame_mem[29] = 8'h00;
+        frame_mem[30] = 8'h40;
+        frame_mem[31] = 8'h11;
+        frame_mem[32] = 8'h53;
+        frame_mem[33] = 8'h7a;
+
+        frame_mem[34] = 8'hc0;
+        frame_mem[35] = 8'ha8;
+        frame_mem[36] = 8'h00;
+        frame_mem[37] = 8'h03;
+
+        frame_mem[38] = 8'hc0;
+        frame_mem[39] = 8'ha8;
+        frame_mem[40] = 8'h00;
+        frame_mem[41] = 8'h02;
+
+        frame_mem[42] = 8'hc0;
+        frame_mem[43] = 8'h31;
+        frame_mem[44] = 8'h1f;
+        frame_mem[45] = 8'h90;
+
+        frame_mem[46] = 8'h00;
+        frame_mem[47] = 8'h0f;
+        frame_mem[48] = 8'he4;
+        frame_mem[49] = 8'h7f;
+
+        frame_mem[50] = 8'h6e;
+        frame_mem[51] = 8'h65;
+        frame_mem[52] = 8'h77;
+        frame_mem[53] = 8'h5f;
+        frame_mem[54] = 8'h6d;
+        frame_mem[55] = 8'h73;
+        frame_mem[56] = 8'h67;
+
+        // FCS
+        frame_mem[57] = 8'h00;
+        frame_mem[58] = 8'h00;
+        frame_mem[59] = 8'h00;
+        frame_mem[60] = 8'h00;
+
+        frame_mem[61] = 8'h00;
+        frame_mem[62] = 8'h00;
+        frame_mem[63] = 8'h00;
+        frame_mem[64] = 8'h00;
+
+        frame_mem[65] = 8'h00;
+        frame_mem[66] = 8'h00;
+        frame_mem[67] = 8'h00;
+
+        frame_mem[68] = 8'h8c;
+        frame_mem[69] = 8'ha2;
+        frame_mem[70] = 8'h2e;
+        frame_mem[71] = 8'h26;
+        frame_mem[72] = 8'hdd;
+        send_gmii_frame_mem(73);
+
+        gmii_idle(200);
+        send_gmii_frame_mem(57);
+        gmii_idle(20);
+        send_gmii_frame_mem(57);
+        gmii_idle(200);
+        send_gmii_frame_mem(66);
+        gmii_idle(200);
+        send_gmii_frame_mem(66);
+        send_gmii_frame_mem(66);
+        gmii_idle(200);
+
+        $display("\nSimulation done OK");
+        $finish;
+    end
+
+endmodule

rtl/ethernet-udp/tests/eth_minimal/Makefile

@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# FPGA settings
+FPGA_PART = xc7a35tfgg484-1
+FPGA_TOP = ethernet_test_minimal
+FPGA_ARCH = artix7
+
+RTL_DIR = ../../src
+
+# Files for synthesis
+SYN_FILES = ethernet_test_minimal.v
+
+include ../../../../scripts/vivado.mk
+
+SYN_FILES += $(sort $(shell find ../../src -type f \( -name '*.v' -o -name '*.sv' \)))
+
+XCI_FILES = $(sort $(shell find ../../src -type f -name '*.xci'))
+
+XDC_FILES += debug.xdc
+XDC_FILES += ../../../../constraints/ax7a035b.xdc
+
+program: $(PROJECT).bit
+	echo "open_hw_manager" > program.tcl
+	echo "connect_hw_server" >> program.tcl
+	echo "open_hw_target" >> program.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+	echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
+	echo "program_hw_devices [current_hw_device]" >> program.tcl
+	echo "exit" >> program.tcl
+	vivado -nojournal -nolog -mode batch -source program.tcl
+
+$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
+	echo "write_cfgmem -force -format mcs -size 16 -interface SPIx4 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
+	echo "exit" >> generate_mcs.tcl
+	vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	for x in .mcs .prm; \
+	do cp $*$$x rev/$*_rev$$COUNT$$x; \
+	echo "Output: rev/$*_rev$$COUNT$$x"; done;

rtl/ethernet-udp/tests/eth_minimal/debug.xdc

@@ -0,0 +1,188 @@
+# debug ILA
+
+create_debug_core u_ila_0 ila
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
+set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
+set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
+set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
+set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
+set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
+set_property port_width 1 [get_debug_ports u_ila_0/clk]
+connect_debug_port u_ila_0/clk [get_nets [list rgmii_rxc_IBUF_BUFG]]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
+set_property port_width 9 [get_debug_ports u_ila_0/probe0]
+connect_debug_port u_ila_0/probe0 [get_nets [list {mac_test0/state[0]} {mac_test0/state[1]} {mac_test0/state[2]} {mac_test0/state[3]} {mac_test0/state[4]} {mac_test0/state[5]} {mac_test0/state[6]} {mac_test0/state[7]} {mac_test0/state[8]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
+set_property port_width 8 [get_debug_ports u_ila_0/probe1]
+connect_debug_port u_ila_0/probe1 [get_nets [list {arbi_inst/rx_buffer_inst/e10_100_rxd[0]} {arbi_inst/rx_buffer_inst/e10_100_rxd[1]} {arbi_inst/rx_buffer_inst/e10_100_rxd[2]} {arbi_inst/rx_buffer_inst/e10_100_rxd[3]} {arbi_inst/rx_buffer_inst/e10_100_rxd[4]} {arbi_inst/rx_buffer_inst/e10_100_rxd[5]} {arbi_inst/rx_buffer_inst/e10_100_rxd[6]} {arbi_inst/rx_buffer_inst/e10_100_rxd[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
+set_property port_width 8 [get_debug_ports u_ila_0/probe2]
+connect_debug_port u_ila_0/probe2 [get_nets [list {arbi_inst/tx_buffer_inst/tx_wdata[0]} {arbi_inst/tx_buffer_inst/tx_wdata[1]} {arbi_inst/tx_buffer_inst/tx_wdata[2]} {arbi_inst/tx_buffer_inst/tx_wdata[3]} {arbi_inst/tx_buffer_inst/tx_wdata[4]} {arbi_inst/tx_buffer_inst/tx_wdata[5]} {arbi_inst/tx_buffer_inst/tx_wdata[6]} {arbi_inst/tx_buffer_inst/tx_wdata[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
+set_property port_width 8 [get_debug_ports u_ila_0/probe3]
+connect_debug_port u_ila_0/probe3 [get_nets [list {arbi_inst/tx_buffer_inst/tx_rdata[0]} {arbi_inst/tx_buffer_inst/tx_rdata[1]} {arbi_inst/tx_buffer_inst/tx_rdata[2]} {arbi_inst/tx_buffer_inst/tx_rdata[3]} {arbi_inst/tx_buffer_inst/tx_rdata[4]} {arbi_inst/tx_buffer_inst/tx_rdata[5]} {arbi_inst/tx_buffer_inst/tx_rdata[6]} {arbi_inst/tx_buffer_inst/tx_rdata[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
+set_property port_width 16 [get_debug_ports u_ila_0/probe4]
+connect_debug_port u_ila_0/probe4 [get_nets [list {arbi_inst/tx_buffer_inst/tx_data_cnt[0]} {arbi_inst/tx_buffer_inst/tx_data_cnt[1]} {arbi_inst/tx_buffer_inst/tx_data_cnt[2]} {arbi_inst/tx_buffer_inst/tx_data_cnt[3]} {arbi_inst/tx_buffer_inst/tx_data_cnt[4]} {arbi_inst/tx_buffer_inst/tx_data_cnt[5]} {arbi_inst/tx_buffer_inst/tx_data_cnt[6]} {arbi_inst/tx_buffer_inst/tx_data_cnt[7]} {arbi_inst/tx_buffer_inst/tx_data_cnt[8]} {arbi_inst/tx_buffer_inst/tx_data_cnt[9]} {arbi_inst/tx_buffer_inst/tx_data_cnt[10]} {arbi_inst/tx_buffer_inst/tx_data_cnt[11]} {arbi_inst/tx_buffer_inst/tx_data_cnt[12]} {arbi_inst/tx_buffer_inst/tx_data_cnt[13]} {arbi_inst/tx_buffer_inst/tx_data_cnt[14]} {arbi_inst/tx_buffer_inst/tx_data_cnt[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
+set_property port_width 16 [get_debug_ports u_ila_0/probe5]
+connect_debug_port u_ila_0/probe5 [get_nets [list {mac_test0/mac_top0/mac_tx0/udp_send_data_length[0]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[1]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[2]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[3]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[4]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[5]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[6]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[7]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[8]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[9]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[10]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[11]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[12]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[13]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[14]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
+set_property port_width 12 [get_debug_ports u_ila_0/probe6]
+connect_debug_port u_ila_0/probe6 [get_nets [list {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[0]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[1]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[2]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[3]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[4]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[5]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[6]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[7]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[8]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[9]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[10]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[11]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
+set_property port_width 8 [get_debug_ports u_ila_0/probe7]
+connect_debug_port u_ila_0/probe7 [get_nets [list {mac_test0/mac_top0/mac_tx0/ram_wr_data[0]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[1]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[2]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[3]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[4]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[5]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[6]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
+set_property port_width 8 [get_debug_ports u_ila_0/probe8]
+connect_debug_port u_ila_0/probe8 [get_nets [list {mac_test0/mac_top0/mac_tx0/mac_tx_data[0]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[1]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[2]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[3]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[4]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[5]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[6]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
+set_property port_width 4 [get_debug_ports u_ila_0/probe9]
+connect_debug_port u_ila_0/probe9 [get_nets [list {mac_test0/mac_top0/mac_tx0/udp0/usedw[0]} {mac_test0/mac_top0/mac_tx0/udp0/usedw[1]} {mac_test0/mac_top0/mac_tx0/udp0/usedw[2]} {mac_test0/mac_top0/mac_tx0/udp0/usedw[3]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
+set_property port_width 6 [get_debug_ports u_ila_0/probe10]
+connect_debug_port u_ila_0/probe10 [get_nets [list {mac_test0/mac_top0/mac_tx0/udp0/state[0]} {mac_test0/mac_top0/mac_tx0/udp0/state[1]} {mac_test0/mac_top0/mac_tx0/udp0/state[2]} {mac_test0/mac_top0/mac_tx0/udp0/state[3]} {mac_test0/mac_top0/mac_tx0/udp0/state[4]} {mac_test0/mac_top0/mac_tx0/udp0/state[5]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
+set_property port_width 6 [get_debug_ports u_ila_0/probe11]
+connect_debug_port u_ila_0/probe11 [get_nets [list {mac_test0/mac_top0/mac_tx0/udp0/ck_state[0]} {mac_test0/mac_top0/mac_tx0/udp0/ck_state[1]} {mac_test0/mac_top0/mac_tx0/udp0/ck_state[2]} {mac_test0/mac_top0/mac_tx0/udp0/ck_state[3]} {mac_test0/mac_top0/mac_tx0/udp0/ck_state[4]} {mac_test0/mac_top0/mac_tx0/udp0/ck_state[5]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
+set_property port_width 16 [get_debug_ports u_ila_0/probe12]
+connect_debug_port u_ila_0/probe12 [get_nets [list {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[0]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[1]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[2]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[3]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[4]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[5]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[6]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[7]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[8]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[9]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[10]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[11]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[12]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[13]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[14]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
+set_property port_width 11 [get_debug_ports u_ila_0/probe13]
+connect_debug_port u_ila_0/probe13 [get_nets [list {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[0]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[1]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[2]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[3]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[4]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[5]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[6]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[7]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[8]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[9]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[10]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
+set_property port_width 8 [get_debug_ports u_ila_0/probe14]
+connect_debug_port u_ila_0/probe14 [get_nets [list {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[0]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[1]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[2]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[3]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[4]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[5]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[6]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
+set_property port_width 16 [get_debug_ports u_ila_0/probe15]
+connect_debug_port u_ila_0/probe15 [get_nets [list {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[0]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[1]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[2]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[3]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[4]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[5]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[6]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[7]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[8]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[9]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[10]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[11]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[12]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[13]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[14]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
+set_property port_width 8 [get_debug_ports u_ila_0/probe16]
+connect_debug_port u_ila_0/probe16 [get_nets [list {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[0]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[1]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[2]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[3]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[4]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[5]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[6]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
+set_property port_width 16 [get_debug_ports u_ila_0/probe17]
+connect_debug_port u_ila_0/probe17 [get_nets [list {mac_test0/mac_top0/mac_rx0/ip_total_data_length[0]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[1]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[2]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[3]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[4]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[5]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[6]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[7]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[8]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[9]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[10]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[11]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[12]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[13]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[14]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
+set_property port_width 8 [get_debug_ports u_ila_0/probe18]
+connect_debug_port u_ila_0/probe18 [get_nets [list {mac_test0/mac_top0/mac_rx0/mac_rx_datain[0]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[1]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[2]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[3]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[4]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[5]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[6]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
+set_property port_width 11 [get_debug_ports u_ila_0/probe19]
+connect_debug_port u_ila_0/probe19 [get_nets [list {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[0]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[1]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[2]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[3]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[4]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[5]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[6]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[7]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[8]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[9]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[10]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
+set_property port_width 8 [get_debug_ports u_ila_0/probe20]
+connect_debug_port u_ila_0/probe20 [get_nets [list {arbi_inst/gmii_txd[0]} {arbi_inst/gmii_txd[1]} {arbi_inst/gmii_txd[2]} {arbi_inst/gmii_txd[3]} {arbi_inst/gmii_txd[4]} {arbi_inst/gmii_txd[5]} {arbi_inst/gmii_txd[6]} {arbi_inst/gmii_txd[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
+set_property port_width 8 [get_debug_ports u_ila_0/probe21]
+connect_debug_port u_ila_0/probe21 [get_nets [list {arbi_inst/gmii_rxd[0]} {arbi_inst/gmii_rxd[1]} {arbi_inst/gmii_rxd[2]} {arbi_inst/gmii_rxd[3]} {arbi_inst/gmii_rxd[4]} {arbi_inst/gmii_rxd[5]} {arbi_inst/gmii_rxd[6]} {arbi_inst/gmii_rxd[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
+set_property port_width 8 [get_debug_ports u_ila_0/probe22]
+connect_debug_port u_ila_0/probe22 [get_nets [list {arbi_inst/e_txd[0]} {arbi_inst/e_txd[1]} {arbi_inst/e_txd[2]} {arbi_inst/e_txd[3]} {arbi_inst/e_txd[4]} {arbi_inst/e_txd[5]} {arbi_inst/e_txd[6]} {arbi_inst/e_txd[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
+set_property port_width 8 [get_debug_ports u_ila_0/probe23]
+connect_debug_port u_ila_0/probe23 [get_nets [list {arbi_inst/e_rxd[0]} {arbi_inst/e_rxd[1]} {arbi_inst/e_rxd[2]} {arbi_inst/e_rxd[3]} {arbi_inst/e_rxd[4]} {arbi_inst/e_rxd[5]} {arbi_inst/e_rxd[6]} {arbi_inst/e_rxd[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
+set_property port_width 1 [get_debug_ports u_ila_0/probe24]
+connect_debug_port u_ila_0/probe24 [get_nets [list mac_test0/mac_top0/mac_tx0/almost_full]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
+set_property port_width 1 [get_debug_ports u_ila_0/probe25]
+connect_debug_port u_ila_0/probe25 [get_nets [list arbi_inst/rx_buffer_inst/e10_100_rx_dv]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
+set_property port_width 1 [get_debug_ports u_ila_0/probe26]
+connect_debug_port u_ila_0/probe26 [get_nets [list arbi_inst/e_rx_dv]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
+set_property port_width 1 [get_debug_ports u_ila_0/probe27]
+connect_debug_port u_ila_0/probe27 [get_nets [list arbi_inst/e_tx_en]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
+set_property port_width 1 [get_debug_ports u_ila_0/probe28]
+connect_debug_port u_ila_0/probe28 [get_nets [list arbi_inst/gmii_rx_dv]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
+set_property port_width 1 [get_debug_ports u_ila_0/probe29]
+connect_debug_port u_ila_0/probe29 [get_nets [list arbi_inst/rx_buffer_inst/gmii_rx_dv_d0]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
+set_property port_width 1 [get_debug_ports u_ila_0/probe30]
+connect_debug_port u_ila_0/probe30 [get_nets [list arbi_inst/rx_buffer_inst/gmii_rx_dv_d1]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
+set_property port_width 1 [get_debug_ports u_ila_0/probe31]
+connect_debug_port u_ila_0/probe31 [get_nets [list arbi_inst/gmii_tx_en]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
+set_property port_width 1 [get_debug_ports u_ila_0/probe32]
+connect_debug_port u_ila_0/probe32 [get_nets [list mac_test0/mac_top0/mac_tx0/mac_data_valid]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
+set_property port_width 1 [get_debug_ports u_ila_0/probe33]
+connect_debug_port u_ila_0/probe33 [get_nets [list mac_test0/mac_top0/mac_tx0/mac_send_end]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
+set_property port_width 1 [get_debug_ports u_ila_0/probe34]
+connect_debug_port u_ila_0/probe34 [get_nets [list mac_test0/mac_top0/mac_rx0/udp0/ram_wr_en]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
+set_property port_width 1 [get_debug_ports u_ila_0/probe35]
+connect_debug_port u_ila_0/probe35 [get_nets [list mac_test0/mac_top0/mac_tx0/ram_wr_en]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
+set_property port_width 1 [get_debug_ports u_ila_0/probe36]
+connect_debug_port u_ila_0/probe36 [get_nets [list arbi_inst/tx_buffer_inst/tx_rden]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
+set_property port_width 1 [get_debug_ports u_ila_0/probe37]
+connect_debug_port u_ila_0/probe37 [get_nets [list arbi_inst/tx_buffer_inst/tx_wren]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
+set_property port_width 1 [get_debug_ports u_ila_0/probe38]
+connect_debug_port u_ila_0/probe38 [get_nets [list mac_test0/mac_top0/mac_tx0/udp_ram_data_req]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39]
+set_property port_width 1 [get_debug_ports u_ila_0/probe39]
+connect_debug_port u_ila_0/probe39 [get_nets [list mac_test0/mac_top0/mac_rx0/udp_rec_data_valid]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40]
+set_property port_width 1 [get_debug_ports u_ila_0/probe40]
+connect_debug_port u_ila_0/probe40 [get_nets [list mac_test0/mac_top0/mac_tx0/udp_tx_end]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41]
+set_property port_width 1 [get_debug_ports u_ila_0/probe41]
+connect_debug_port u_ila_0/probe41 [get_nets [list mac_test0/mac_top0/mac_tx0/udp_tx_req]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42]
+set_property port_width 1 [get_debug_ports u_ila_0/probe42]
+connect_debug_port u_ila_0/probe42 [get_nets [list mac_test0/mac_top0/mac_tx0/upper_data_req]]
+set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
+set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+connect_debug_port dbg_hub/clk [get_nets rgmii_rxc_IBUF_BUFG]

rtl/ethernet-udp/tests/eth_minimal/ethernet_test_minimal.v

@@ -0,0 +1,134 @@
+module ethernet_test_minimal
+(
+input               sys_clk_p,                       //system clock positive
+input               sys_clk_n,                       //system clock negative 
+input               rst_n,                           //reset ,low active
+output [3:0]        led,                             //display network rate status
+output              e_reset,                         //phy reset
+output              e_mdc,                           //phy emdio clock
+inout               e_mdio,                          //phy emdio data
+output[3:0]         rgmii_txd,                       //phy data send
+output              rgmii_txctl,                     //phy data send control
+output              rgmii_txc,                       //Clock for sending data
+input[3:0]          rgmii_rxd,                       //recieve data
+input               rgmii_rxctl,                     //Control signal for receiving data
+input               rgmii_rxc                        //Clock for recieving data
+);
+wire   [ 7:0]       gmii_txd;                       //gmii data                
+wire                gmii_tx_en;                     //gmii send enable
+wire                gmii_tx_er;
+wire                gmii_tx_clk;                    //gmii send clock
+wire                gmii_crs;
+wire                gmii_col;
+wire   [ 7:0]       gmii_rxd;                       //gmii recieving data                    
+wire                gmii_rx_dv;                     //gmii recieving data valid
+wire                gmii_rx_er;
+wire                gmii_rx_clk;                    //gmii recieve clock
+wire  [ 1:0]        speed_selection;                // 1x gigabit, 01 100Mbps, 00 10mbps
+wire                duplex_mode;                    // 1 full, 0 half
+wire                rgmii_rxcpll;
+
+wire  [31:0]        pack_total_len ;                //package length
+
+wire [1:0]          speed      ;                    //net speed select
+wire                link       ;                    //link status
+wire                e_rx_dv    ;
+wire [7:0]          e_rxd      ;
+wire                e_tx_en    ;
+wire [7:0]          e_txd      ;
+wire                e_rst_n    ; 
+wire                sys_clk    ;
+
+
+assign duplex_mode = 1'b1;
+
+
+/*************************************************************************
+generate single end clock
+**************************************************************************/
+IBUFDS sys_clk_ibufgds
+(
+.O                              (sys_clk                 ),
+.I                              (sys_clk_p               ),
+.IB                             (sys_clk_n               )
+); 
+
+(* IODELAY_GROUP = "rgmii_idelay_group" *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
+
+IDELAYCTRL IDELAYCTRL_inst (
+.RDY(),       // 1-bit output: Ready output
+.REFCLK(sys_clk), // 1-bit input: Reference clock input
+.RST(1'b0)        // 1-bit input: Active high reset input
+);
+/*************************************************************************
+GMII and RGMII data conversion
+****************************************************************************/
+util_gmii_to_rgmii util_gmii_to_rgmii_m0
+(
+.reset              (1'b0                   ),
+.rgmii_td           (rgmii_txd              ),
+.rgmii_tx_ctl       (rgmii_txctl            ),
+.rgmii_txc          (rgmii_txc              ),
+.rgmii_rd           (rgmii_rxd              ),
+.rgmii_rx_ctl       (rgmii_rxctl            ),
+.gmii_rx_clk        (gmii_rx_clk            ),
+.gmii_txd           (e_txd                  ),
+.gmii_tx_en         (e_tx_en                ),
+.gmii_tx_er         (1'b0                   ),
+.gmii_tx_clk        (gmii_tx_clk            ),
+.gmii_crs           (gmii_crs               ),
+.gmii_col           (gmii_col               ),
+.gmii_rxd           (gmii_rxd               ),
+.rgmii_rxc          (rgmii_rxc              ),//add
+.gmii_rx_dv         (gmii_rx_dv             ),
+.gmii_rx_er         (gmii_rx_er             ),
+.speed_selection    (2'b10                  ),
+.duplex_mode        (duplex_mode            )
+);
+/*************************************************************************
+Different conversion of GMII data according to different network speeds
+****************************************************************************/
+
+gmii_arbi arbi_inst
+(
+.clk                (gmii_tx_clk            ),
+.rst_n              (rst_n                  ),
+.speed              (2'b10                  ),  
+.link               (1'b1                  ), 
+.pack_total_len     (pack_total_len         ), 
+.e_rst_n            (e_rst_n                ),
+.gmii_rx_dv         (gmii_rx_dv             ),
+.gmii_rxd           (gmii_rxd               ),
+.gmii_tx_en         (gmii_tx_en             ),
+.gmii_txd           (gmii_txd               ), 
+.e_rx_dv            (e_rx_dv                ),
+.e_rxd              (e_rxd                  ),
+.e_tx_en            (e_tx_en                ),
+.e_txd              (e_txd                  ) 
+);
+
+
+/*************************************************************************
+Mac layer protocol test
+****************************************************************************/
+mac_test mac_test0
+(
+.gmii_tx_clk        (gmii_tx_clk            ),
+.gmii_rx_clk        (gmii_rx_clk            ) ,
+.rst_n              (e_rst_n                ),
+.pack_total_len     (pack_total_len         ),
+.gmii_rx_dv         (e_rx_dv                ),
+.gmii_rxd           (e_rxd                  ),
+.gmii_tx_en         (gmii_tx_en             ),
+.gmii_txd           (gmii_txd               )
+); 
+/*************************************************************************
+Generate PHY reset signal
+****************************************************************************/
+reset reset_m0
+(
+.clk                (sys_clk                ),
+.key1               (rst_n                  ),
+.rst_n              (e_reset                )
+);
+endmodule

rtl/ethernet-udp/tests/eth_minimal/ethernet_test_minimal.xdc

@@ -0,0 +1,241 @@
+# constrains for minimal ethernet stack
+
+create_clock -period 5.000 [get_ports sys_clk_p]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_p]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_n]
+set_property PACKAGE_PIN R4 [get_ports sys_clk_p]
+set_property PACKAGE_PIN T4 [get_ports sys_clk_n]
+
+set_property PACKAGE_PIN F15 [get_ports rst_n]
+set_property IOSTANDARD LVCMOS33 [get_ports rst_n]
+
+set_property PACKAGE_PIN L13 [get_ports {led[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
+set_property PACKAGE_PIN M13 [get_ports {led[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
+set_property PACKAGE_PIN K14 [get_ports {led[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
+set_property PACKAGE_PIN K13 [get_ports {led[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
+#########################ethernet######################
+create_clock -period 8.000 [get_ports rgmii_rxc]
+set_property IOSTANDARD LVCMOS33 [get_ports {rgmii_rxd[*]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {rgmii_txd[*]}]
+set_property SLEW FAST [get_ports {rgmii_txd[*]}]
+
+set_property IOSTANDARD LVCMOS33 [get_ports e_mdc]
+set_property IOSTANDARD LVCMOS33 [get_ports e_mdio]
+set_property IOSTANDARD LVCMOS33 [get_ports e_reset]
+set_property IOSTANDARD LVCMOS33 [get_ports rgmii_rxc]
+set_property IOSTANDARD LVCMOS33 [get_ports rgmii_rxctl]
+set_property IOSTANDARD LVCMOS33 [get_ports rgmii_txc]
+set_property IOSTANDARD LVCMOS33 [get_ports rgmii_txctl]
+set_property SLEW FAST [get_ports rgmii_txc]
+set_property SLEW FAST [get_ports rgmii_txctl]
+
+set_property PACKAGE_PIN P17 [get_ports {rgmii_rxd[3]}]
+set_property PACKAGE_PIN U17 [get_ports {rgmii_rxd[2]}]
+set_property PACKAGE_PIN U18 [get_ports {rgmii_rxd[1]}]
+set_property PACKAGE_PIN P19 [get_ports {rgmii_rxd[0]}]
+set_property PACKAGE_PIN R16 [get_ports {rgmii_txd[3]}]
+set_property PACKAGE_PIN R17 [get_ports {rgmii_txd[2]}]
+set_property PACKAGE_PIN P16 [get_ports {rgmii_txd[1]}]
+set_property PACKAGE_PIN N14 [get_ports {rgmii_txd[0]}]
+set_property PACKAGE_PIN N13 [get_ports e_mdc]
+set_property PACKAGE_PIN P14 [get_ports e_mdio]
+set_property PACKAGE_PIN R14 [get_ports e_reset]
+set_property PACKAGE_PIN V18 [get_ports rgmii_rxc]
+set_property PACKAGE_PIN R19 [get_ports rgmii_rxctl]
+set_property PACKAGE_PIN P15 [get_ports rgmii_txc]
+set_property PACKAGE_PIN N17 [get_ports rgmii_txctl]
+
+
+
+
+
+create_debug_core u_ila_0 ila
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
+set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
+set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
+set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
+set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
+set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
+set_property port_width 1 [get_debug_ports u_ila_0/clk]
+connect_debug_port u_ila_0/clk [get_nets [list rgmii_rxc_IBUF_BUFG]]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
+set_property port_width 9 [get_debug_ports u_ila_0/probe0]
+connect_debug_port u_ila_0/probe0 [get_nets [list {mac_test0/state[0]} {mac_test0/state[1]} {mac_test0/state[2]} {mac_test0/state[3]} {mac_test0/state[4]} {mac_test0/state[5]} {mac_test0/state[6]} {mac_test0/state[7]} {mac_test0/state[8]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
+set_property port_width 8 [get_debug_ports u_ila_0/probe1]
+connect_debug_port u_ila_0/probe1 [get_nets [list {arbi_inst/rx_buffer_inst/e10_100_rxd[0]} {arbi_inst/rx_buffer_inst/e10_100_rxd[1]} {arbi_inst/rx_buffer_inst/e10_100_rxd[2]} {arbi_inst/rx_buffer_inst/e10_100_rxd[3]} {arbi_inst/rx_buffer_inst/e10_100_rxd[4]} {arbi_inst/rx_buffer_inst/e10_100_rxd[5]} {arbi_inst/rx_buffer_inst/e10_100_rxd[6]} {arbi_inst/rx_buffer_inst/e10_100_rxd[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
+set_property port_width 8 [get_debug_ports u_ila_0/probe2]
+connect_debug_port u_ila_0/probe2 [get_nets [list {arbi_inst/gmii_txd[0]} {arbi_inst/gmii_txd[1]} {arbi_inst/gmii_txd[2]} {arbi_inst/gmii_txd[3]} {arbi_inst/gmii_txd[4]} {arbi_inst/gmii_txd[5]} {arbi_inst/gmii_txd[6]} {arbi_inst/gmii_txd[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
+set_property port_width 8 [get_debug_ports u_ila_0/probe3]
+connect_debug_port u_ila_0/probe3 [get_nets [list {arbi_inst/gmii_rxd[0]} {arbi_inst/gmii_rxd[1]} {arbi_inst/gmii_rxd[2]} {arbi_inst/gmii_rxd[3]} {arbi_inst/gmii_rxd[4]} {arbi_inst/gmii_rxd[5]} {arbi_inst/gmii_rxd[6]} {arbi_inst/gmii_rxd[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
+set_property port_width 8 [get_debug_ports u_ila_0/probe4]
+connect_debug_port u_ila_0/probe4 [get_nets [list {arbi_inst/e_txd[0]} {arbi_inst/e_txd[1]} {arbi_inst/e_txd[2]} {arbi_inst/e_txd[3]} {arbi_inst/e_txd[4]} {arbi_inst/e_txd[5]} {arbi_inst/e_txd[6]} {arbi_inst/e_txd[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
+set_property port_width 8 [get_debug_ports u_ila_0/probe5]
+connect_debug_port u_ila_0/probe5 [get_nets [list {arbi_inst/e_rxd[0]} {arbi_inst/e_rxd[1]} {arbi_inst/e_rxd[2]} {arbi_inst/e_rxd[3]} {arbi_inst/e_rxd[4]} {arbi_inst/e_rxd[5]} {arbi_inst/e_rxd[6]} {arbi_inst/e_rxd[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
+set_property port_width 8 [get_debug_ports u_ila_0/probe6]
+connect_debug_port u_ila_0/probe6 [get_nets [list {arbi_inst/tx_buffer_inst/tx_wdata[0]} {arbi_inst/tx_buffer_inst/tx_wdata[1]} {arbi_inst/tx_buffer_inst/tx_wdata[2]} {arbi_inst/tx_buffer_inst/tx_wdata[3]} {arbi_inst/tx_buffer_inst/tx_wdata[4]} {arbi_inst/tx_buffer_inst/tx_wdata[5]} {arbi_inst/tx_buffer_inst/tx_wdata[6]} {arbi_inst/tx_buffer_inst/tx_wdata[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
+set_property port_width 8 [get_debug_ports u_ila_0/probe7]
+connect_debug_port u_ila_0/probe7 [get_nets [list {arbi_inst/tx_buffer_inst/tx_rdata[0]} {arbi_inst/tx_buffer_inst/tx_rdata[1]} {arbi_inst/tx_buffer_inst/tx_rdata[2]} {arbi_inst/tx_buffer_inst/tx_rdata[3]} {arbi_inst/tx_buffer_inst/tx_rdata[4]} {arbi_inst/tx_buffer_inst/tx_rdata[5]} {arbi_inst/tx_buffer_inst/tx_rdata[6]} {arbi_inst/tx_buffer_inst/tx_rdata[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
+set_property port_width 16 [get_debug_ports u_ila_0/probe8]
+connect_debug_port u_ila_0/probe8 [get_nets [list {arbi_inst/tx_buffer_inst/tx_data_cnt[0]} {arbi_inst/tx_buffer_inst/tx_data_cnt[1]} {arbi_inst/tx_buffer_inst/tx_data_cnt[2]} {arbi_inst/tx_buffer_inst/tx_data_cnt[3]} {arbi_inst/tx_buffer_inst/tx_data_cnt[4]} {arbi_inst/tx_buffer_inst/tx_data_cnt[5]} {arbi_inst/tx_buffer_inst/tx_data_cnt[6]} {arbi_inst/tx_buffer_inst/tx_data_cnt[7]} {arbi_inst/tx_buffer_inst/tx_data_cnt[8]} {arbi_inst/tx_buffer_inst/tx_data_cnt[9]} {arbi_inst/tx_buffer_inst/tx_data_cnt[10]} {arbi_inst/tx_buffer_inst/tx_data_cnt[11]} {arbi_inst/tx_buffer_inst/tx_data_cnt[12]} {arbi_inst/tx_buffer_inst/tx_data_cnt[13]} {arbi_inst/tx_buffer_inst/tx_data_cnt[14]} {arbi_inst/tx_buffer_inst/tx_data_cnt[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
+set_property port_width 6 [get_debug_ports u_ila_0/probe9]
+connect_debug_port u_ila_0/probe9 [get_nets [list {mac_test0/mac_top0/mac_tx0/udp0/ck_state[0]} {mac_test0/mac_top0/mac_tx0/udp0/ck_state[1]} {mac_test0/mac_top0/mac_tx0/udp0/ck_state[2]} {mac_test0/mac_top0/mac_tx0/udp0/ck_state[3]} {mac_test0/mac_top0/mac_tx0/udp0/ck_state[4]} {mac_test0/mac_top0/mac_tx0/udp0/ck_state[5]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
+set_property port_width 16 [get_debug_ports u_ila_0/probe10]
+connect_debug_port u_ila_0/probe10 [get_nets [list {mac_test0/mac_top0/mac_tx0/udp_send_data_length[0]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[1]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[2]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[3]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[4]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[5]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[6]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[7]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[8]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[9]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[10]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[11]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[12]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[13]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[14]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
+set_property port_width 8 [get_debug_ports u_ila_0/probe11]
+connect_debug_port u_ila_0/probe11 [get_nets [list {mac_test0/mac_top0/mac_tx0/ram_wr_data[0]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[1]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[2]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[3]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[4]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[5]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[6]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
+set_property port_width 8 [get_debug_ports u_ila_0/probe12]
+connect_debug_port u_ila_0/probe12 [get_nets [list {mac_test0/mac_top0/mac_tx0/mac_tx_data[0]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[1]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[2]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[3]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[4]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[5]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[6]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
+set_property port_width 4 [get_debug_ports u_ila_0/probe13]
+connect_debug_port u_ila_0/probe13 [get_nets [list {mac_test0/mac_top0/mac_tx0/udp0/usedw[0]} {mac_test0/mac_top0/mac_tx0/udp0/usedw[1]} {mac_test0/mac_top0/mac_tx0/udp0/usedw[2]} {mac_test0/mac_top0/mac_tx0/udp0/usedw[3]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
+set_property port_width 6 [get_debug_ports u_ila_0/probe14]
+connect_debug_port u_ila_0/probe14 [get_nets [list {mac_test0/mac_top0/mac_tx0/udp0/state[0]} {mac_test0/mac_top0/mac_tx0/udp0/state[1]} {mac_test0/mac_top0/mac_tx0/udp0/state[2]} {mac_test0/mac_top0/mac_tx0/udp0/state[3]} {mac_test0/mac_top0/mac_tx0/udp0/state[4]} {mac_test0/mac_top0/mac_tx0/udp0/state[5]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
+set_property port_width 12 [get_debug_ports u_ila_0/probe15]
+connect_debug_port u_ila_0/probe15 [get_nets [list {mac_test0/mac_top0/mac_tx0/udp0/dbg_fifo_count[0]} {mac_test0/mac_top0/mac_tx0/udp0/dbg_fifo_count[1]} {mac_test0/mac_top0/mac_tx0/udp0/dbg_fifo_count[2]} {mac_test0/mac_top0/mac_tx0/udp0/dbg_fifo_count[3]} {mac_test0/mac_top0/mac_tx0/udp0/dbg_fifo_count[4]} {mac_test0/mac_top0/mac_tx0/udp0/dbg_fifo_count[5]} {mac_test0/mac_top0/mac_tx0/udp0/dbg_fifo_count[6]} {mac_test0/mac_top0/mac_tx0/udp0/dbg_fifo_count[7]} {mac_test0/mac_top0/mac_tx0/udp0/dbg_fifo_count[8]} {mac_test0/mac_top0/mac_tx0/udp0/dbg_fifo_count[9]} {mac_test0/mac_top0/mac_tx0/udp0/dbg_fifo_count[10]} {mac_test0/mac_top0/mac_tx0/udp0/dbg_fifo_count[11]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
+set_property port_width 16 [get_debug_ports u_ila_0/probe16]
+connect_debug_port u_ila_0/probe16 [get_nets [list {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[0]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[1]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[2]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[3]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[4]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[5]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[6]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[7]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[8]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[9]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[10]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[11]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[12]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[13]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[14]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
+set_property port_width 11 [get_debug_ports u_ila_0/probe17]
+connect_debug_port u_ila_0/probe17 [get_nets [list {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[0]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[1]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[2]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[3]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[4]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[5]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[6]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[7]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[8]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[9]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[10]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
+set_property port_width 8 [get_debug_ports u_ila_0/probe18]
+connect_debug_port u_ila_0/probe18 [get_nets [list {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[0]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[1]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[2]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[3]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[4]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[5]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[6]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
+set_property port_width 16 [get_debug_ports u_ila_0/probe19]
+connect_debug_port u_ila_0/probe19 [get_nets [list {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[0]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[1]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[2]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[3]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[4]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[5]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[6]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[7]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[8]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[9]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[10]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[11]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[12]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[13]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[14]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
+set_property port_width 8 [get_debug_ports u_ila_0/probe20]
+connect_debug_port u_ila_0/probe20 [get_nets [list {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[0]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[1]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[2]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[3]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[4]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[5]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[6]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
+set_property port_width 16 [get_debug_ports u_ila_0/probe21]
+connect_debug_port u_ila_0/probe21 [get_nets [list {mac_test0/mac_top0/mac_rx0/ip_total_data_length[0]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[1]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[2]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[3]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[4]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[5]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[6]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[7]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[8]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[9]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[10]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[11]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[12]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[13]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[14]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
+set_property port_width 8 [get_debug_ports u_ila_0/probe22]
+connect_debug_port u_ila_0/probe22 [get_nets [list {mac_test0/mac_top0/mac_rx0/mac_rx_datain[0]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[1]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[2]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[3]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[4]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[5]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[6]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
+set_property port_width 11 [get_debug_ports u_ila_0/probe23]
+connect_debug_port u_ila_0/probe23 [get_nets [list {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[0]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[1]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[2]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[3]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[4]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[5]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[6]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[7]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[8]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[9]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[10]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
+set_property port_width 1 [get_debug_ports u_ila_0/probe24]
+connect_debug_port u_ila_0/probe24 [get_nets [list mac_test0/mac_top0/mac_tx0/almost_full]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
+set_property port_width 1 [get_debug_ports u_ila_0/probe25]
+connect_debug_port u_ila_0/probe25 [get_nets [list arbi_inst/rx_buffer_inst/e10_100_rx_dv]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
+set_property port_width 1 [get_debug_ports u_ila_0/probe26]
+connect_debug_port u_ila_0/probe26 [get_nets [list arbi_inst/e_rx_dv]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
+set_property port_width 1 [get_debug_ports u_ila_0/probe27]
+connect_debug_port u_ila_0/probe27 [get_nets [list arbi_inst/e_tx_en]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
+set_property port_width 1 [get_debug_ports u_ila_0/probe28]
+connect_debug_port u_ila_0/probe28 [get_nets [list arbi_inst/gmii_rx_dv]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
+set_property port_width 1 [get_debug_ports u_ila_0/probe29]
+connect_debug_port u_ila_0/probe29 [get_nets [list arbi_inst/rx_buffer_inst/gmii_rx_dv_d0]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
+set_property port_width 1 [get_debug_ports u_ila_0/probe30]
+connect_debug_port u_ila_0/probe30 [get_nets [list arbi_inst/rx_buffer_inst/gmii_rx_dv_d1]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
+set_property port_width 1 [get_debug_ports u_ila_0/probe31]
+connect_debug_port u_ila_0/probe31 [get_nets [list arbi_inst/gmii_tx_en]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
+set_property port_width 1 [get_debug_ports u_ila_0/probe32]
+connect_debug_port u_ila_0/probe32 [get_nets [list mac_test0/mac_top0/mac_tx0/mac_data_valid]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
+set_property port_width 1 [get_debug_ports u_ila_0/probe33]
+connect_debug_port u_ila_0/probe33 [get_nets [list mac_test0/mac_top0/mac_tx0/mac_send_end]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
+set_property port_width 1 [get_debug_ports u_ila_0/probe34]
+connect_debug_port u_ila_0/probe34 [get_nets [list mac_test0/mac_top0/mac_tx0/ram_wr_en]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
+set_property port_width 1 [get_debug_ports u_ila_0/probe35]
+connect_debug_port u_ila_0/probe35 [get_nets [list mac_test0/mac_top0/mac_rx0/udp0/ram_wr_en]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
+set_property port_width 1 [get_debug_ports u_ila_0/probe36]
+connect_debug_port u_ila_0/probe36 [get_nets [list arbi_inst/tx_buffer_inst/tx_rden]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
+set_property port_width 1 [get_debug_ports u_ila_0/probe37]
+connect_debug_port u_ila_0/probe37 [get_nets [list arbi_inst/tx_buffer_inst/tx_wren]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
+set_property port_width 1 [get_debug_ports u_ila_0/probe38]
+connect_debug_port u_ila_0/probe38 [get_nets [list mac_test0/mac_top0/mac_tx0/udp_ram_data_req]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39]
+set_property port_width 1 [get_debug_ports u_ila_0/probe39]
+connect_debug_port u_ila_0/probe39 [get_nets [list mac_test0/mac_top0/mac_rx0/udp_rec_data_valid]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40]
+set_property port_width 1 [get_debug_ports u_ila_0/probe40]
+connect_debug_port u_ila_0/probe40 [get_nets [list mac_test0/mac_top0/mac_tx0/udp_tx_end]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41]
+set_property port_width 1 [get_debug_ports u_ila_0/probe41]
+connect_debug_port u_ila_0/probe41 [get_nets [list mac_test0/mac_top0/mac_tx0/udp_tx_req]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42]
+set_property port_width 1 [get_debug_ports u_ila_0/probe42]
+connect_debug_port u_ila_0/probe42 [get_nets [list mac_test0/mac_top0/mac_tx0/upper_data_req]]
+set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
+set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+connect_debug_port dbg_hub/clk [get_nets rgmii_rxc_IBUF_BUFG]

rtl/sampler/src/sampler.sv

@@ -1,72 +0,0 @@
-`timescale 1ns / 1ps
-
-
-
-module sampler
-#(
-    parameter DATA_WIDTH = 12,
-    parameter PACK_FACTOR = 3,
-    parameter PROCESS_MODE = 1
-    )
-(
-    input clk_in,
-    input rst,
-    input [DATA_WIDTH-1:0] data_in,
-    input out_of_range,
-
-    output logic [DATA_WIDTH*PACK_FACTOR-1:0]  m_axis_tdata,
-    output logic                              m_axis_tvalid
-    );
-    logic [DATA_WIDTH-1:0] data_converted;
-    logic out_of_range_reg;
-
-    always @( posedge clk_in) begin
-        if (rst) begin
-            data_converted <= '0;
-        end else begin
-            out_of_range_reg <= out_of_range;
-            if (PROCESS_MODE) begin
-                if (data_in == 12'b100000000000) begin
-                    data_converted <= data_in;
-                end else begin
-                    data_converted <= data_in[DATA_WIDTH-1]  ? {1'b1, (~data_in[DATA_WIDTH-2:0] + 1'b1)} : data_in; 
-                    
-                end
-            end else begin
-                data_converted <= data_in; 
-            end
-        end
-    end 
-    
-         
-    logic [DATA_WIDTH*PACK_FACTOR-1:0] buffer;
-    logic buffer_ready;
-
-    logic [$clog2(PACK_FACTOR):0] cnt;
-    
-    always @(posedge clk_in) begin
-        if (rst) begin
-            buffer <= '0;
-            cnt <= -1; //
-            buffer_ready <= 0;
-        end
-        else begin
-            buffer_ready <= 0;
-            if (!out_of_range_reg) begin
-                buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
-                if (cnt == PACK_FACTOR-1) begin
-                    cnt <= 0;
-                    buffer_ready <= 1;
-                    buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
-                end
-                else begin
-                    cnt <= cnt + 1;
-                end
-            end
-        end
-    end
-    
-    assign m_axis_tdata = buffer;
-    assign m_axis_tvalid = buffer_ready;
-    
-endmodule

rtl/sampler/tests/sampler_tb_advanced.sv

@@ -1,120 +0,0 @@
-`timescale 1ns / 1ps
-
-module sampler_tb;
-
-    parameter DATA_WIDTH = 12;
-    parameter PACK_FACTOR = 3;
-    parameter PROCESS_MODE = 1;
-    parameter CLK_PERIOD = 15.3846;  // 65 MHz
-
-    logic clk;
-    logic rst;
-    logic [DATA_WIDTH-1:0] data_in;
-    logic out_of_range;
-    logic [DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata;
-    logic m_axis_tvalid;
-
-    sampler #(
-        .DATA_WIDTH(DATA_WIDTH),
-        .PACK_FACTOR(PACK_FACTOR),
-        .PROCESS_MODE(PROCESS_MODE)
-    ) dut (
-        .clk_in(clk),
-        .rst(rst),
-        .data_in(data_in),
-        .out_of_range(out_of_range),
-        .m_axis_tdata(m_axis_tdata),
-        .m_axis_tvalid(m_axis_tvalid)
-    );
-
-    initial begin
-        clk = 0;
-        forever #(CLK_PERIOD/2) clk = ~clk;
-    end
-
-    task send(input [DATA_WIDTH-1:0] word, input bit oor);
-        @(posedge clk);
-        data_in <= word;
-        out_of_range <= oor;
-        $display("Send: %h (%0d) OOR=%b", word, word, oor);
-    endtask
-
-    initial begin
-        $display("\n=== SAMPLER TEST (MODE=%0d) ===\n", PROCESS_MODE);
-        
-        // Reset
-        rst = 1;
-        out_of_range = 0;
-        data_in = 0;
-//        send(12'h001, 0);
-        repeat(5) @(posedge clk);
-        rst = 0;
-        send(12'h001, 0);
-        repeat(1) @(posedge clk);
-        
-        // 1. Positive
-        $display("\n--- Positive numbers ---");
-//        send(12'h001, 0);
-        send(12'h002, 0);
-        send(12'h003, 0);
-        
-        send(12'h004, 0);
-        send(12'h005, 0);
-        send(12'h806, 0);
-        
-        // 2. Negative
-        $display("\n--- Negative numbers ---");
-        send(12'hFFF, 0);  // -1
-        send(12'hFFE, 0);  // -2
-        send(12'hFFD, 0);  // -3
-        
-        send(12'h800, 0);  // -2048
-        send(12'h801, 0);  // -2047
-        send(12'h802, 0);  // -2046
-        
-        // 3. Boundary
-        $display("\n--- Boundary values ---");
-        send(12'h000, 0);  // 0
-        send(12'h001, 0);  // 1
-        send(12'h7FF, 0);  // 2047 (max positive)
-        
-        send(12'h7FE, 0);  // 2046
-        send(12'h800, 0);  // -2048 (min negative)
-        send(12'hFFF, 0);  // -1
-        
-        // 4. Out of range tests
-        $display("\n--- Out of range tests ---");
-        
-
-        send(12'h00A, 0);
-        send(12'h00B, 1);  // 
-        send(12'h00C, 0);
-        send(12'h00D, 0);
-        send(12'h00E, 0);
-        send(12'h00F, 0);  
-        
-        send(12'h010, 0);
-        send(12'h011, 0);
-        send(12'h012, 1);  // 
-        
-        send(12'h013, 0);
-        send(12'h014, 0);
-        send(12'h015, 0); 
-        
-        repeat(10) @(posedge clk);
-        $display("\n=== TEST FINISHED ===");
-        $finish;
-    end
-
-    // Results
-    always @(posedge clk) begin
-        if (m_axis_tvalid) begin
-            $display("\n>>> PACKET RECEIVED at %0t ns:", $time);
-            $display("    Full: %h", m_axis_tdata);
-            $display("    Word0: %h", m_axis_tdata[11:0]);
-            $display("    Word1: %h", m_axis_tdata[23:12]);
-            $display("    Word2: %h\n", m_axis_tdata[35:24]);
-        end
-    end
-
-endmodule

rtl/sampler/tests/sampler_tb_basic.sv

@@ -1,67 +0,0 @@
-`timescale 1ns / 1ps
-
-module sampler_tb;
-
-    parameter DATA_WIDTH = 12;
-    parameter PACK_FACTOR = 3;
-    parameter PROCESS_MODE = 0;
-    
-    parameter CLK_PERIOD = 15.3846; 
-
-    logic clk;
-    logic rst;
-    logic [DATA_WIDTH-1:0] data_in;
-    logic out_of_range;
-
-    logic [DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata;
-    logic m_axis_tvalid;
-
-    // DUT
-    sampler #(
-        .DATA_WIDTH(DATA_WIDTH),
-        .PACK_FACTOR(PACK_FACTOR),
-        .PROCESS_MODE(PROCESS_MODE)
-    ) dut (
-        .clk_in(clk),
-        .rst(rst),
-        .data_in(data_in),
-        .out_of_range(out_of_range),
-        .m_axis_tdata(m_axis_tdata),
-        .m_axis_tvalid(m_axis_tvalid)
-    );
-
-    // clock
-     initial begin
-        clk = 0;
-        forever #(CLK_PERIOD/2) clk = ~clk;
-    end
-
-    integer i;
-
-    initial begin
-        clk = 0;
-        rst = 1;
-        data_in = 0;
-        out_of_range = 0;
-
-        #20;
-        rst = 0;
-        repeat(5) @(posedge clk);
-
-        for (i = 1; i < 20; i++) begin
-            @(posedge clk);
-
-            data_in <= i;
-        end
-
-        #50;
-        $finish;
-    end
-
-    always @(posedge clk) begin
-        if (m_axis_tvalid) begin
-            $display("TIME=%0t PACKED DATA = %h", $time, m_axis_tdata);
-        end
-    end
-
-endmodule

scripts/vivado.mk

@@ -0,0 +1,187 @@
+# SPDX-License-Identifier: MIT
+###################################################################
+#
+# Xilinx Vivado FPGA Makefile
+#
+# Copyright (c) 2016-2025 Alex Forencich
+#
+###################################################################
+#
+# Parameters:
+# FPGA_TOP - Top module name
+# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
+# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
+# SYN_FILES - list of source files
+# INC_FILES - list of include files
+# XDC_FILES - list of timing constraint files
+# XCI_FILES - list of IP XCI files
+# IP_TCL_FILES - list of IP TCL files (sourced during project creation)
+# CONFIG_TCL_FILES - list of config TCL files (sourced before each build)
+#
+# Note: both SYN_FILES and INC_FILES support file list files.  File list
+# files are files with a .f extension that contain a list of additional
+# files to include, one path relative to the .f file location per line.
+# The .f files are processed recursively, and then the complete file list
+# is de-duplicated, with later files in the list taking precedence.
+#
+# Example:
+#
+# FPGA_TOP = fpga
+# FPGA_FAMILY = VirtexUltrascale
+# FPGA_DEVICE = xcvu095-ffva2104-2-e
+# SYN_FILES = rtl/fpga.v
+# XDC_FILES = fpga.xdc
+# XCI_FILES = ip/pcspma.xci
+# include ../common/vivado.mk
+#
+###################################################################
+
+# phony targets
+.PHONY: fpga vivado sim sim-gui simclean tmpclean clean distclean
+
+# prevent make from deleting intermediate files and reports
+.PRECIOUS: %.xpr %.bit %.bin %.ltx %.xsa %.mcs %.prm
+.SECONDARY:
+
+
+FPGA_TOP ?= $(FPGA_TOP)
+PROJECT ?= $(FPGA_TOP)
+# XDC_FILES ?= $(PROJECT).xdc
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+SYN_FILES := $(call uniq_base,$(call process_f_files,$(SYN_FILES)))
+INC_FILES := $(call uniq_base,$(call process_f_files,$(INC_FILES)))
+
+# simulation parameters
+SIM_TOP ?= $(FPGA_TOP)_tb
+TB_FILES ?=
+SIM_FILES ?= $(SYN_FILES) $(TB_FILES)
+SIM_DEFS ?= $(DEFS)
+SIM_RUNTIME ?= all
+
+
+###################################################################
+# Main Targets
+#
+# all: build everything (fpga)
+# fpga: build FPGA config
+# vivado: open project in Vivado
+# tmpclean: remove intermediate files
+# clean: remove output files and project files
+# distclean: remove archived output files
+###################################################################
+
+all: fpga
+
+fpga: $(PROJECT).bit
+
+vivado: $(PROJECT).xpr
+	vivado $(PROJECT).xpr
+
+tmpclean::
+	-rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
+	-rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
+
+clean:: tmpclean
+	-rm -rf *.bit *.bin *.ltx *.xsa program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
+	-rm -rf *_utilization.rpt *_utilization_hierarchical.rpt
+
+distclean:: clean
+	-rm -rf rev
+
+###################################################################
+# Target implementations
+###################################################################
+
+# Vivado project file
+
+# create fresh project if Makefile or IP files have changed
+create_project.tcl: Makefile $(XCI_FILES) $(IP_TCL_FILES)
+	rm -rf defines.v
+	touch defines.v
+	for x in $(DEFS); do echo '`define' $$x >> defines.v; done
+	echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@
+	echo "add_files -fileset sources_1 defines.v $(SYN_FILES)" >> $@
+	echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@
+	echo "add_files -fileset constrs_1 $(XDC_FILES)" >> $@
+	for x in $(XCI_FILES); do echo "import_ip $$x" >> $@; done
+	for x in $(IP_TCL_FILES); do echo "source $$x" >> $@; done
+	for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
+	if [ -n "$(TB_FILES)" ]; then \
+		echo "add_files -fileset sim_1 defines.v $(TB_FILES)" >> $@; \
+		echo "set_property top $(SIM_TOP) [get_filesets sim_1]" >> $@; \
+		echo "set_property top_lib xil_defaultlib [get_filesets sim_1]" >> $@; \
+	fi
+	echo "update_compile_order -fileset sources_1" >> $@
+	echo "update_compile_order -fileset sim_1" >> $@
+
+# source config TCL scripts if any source file has changed
+update_config.tcl: $(CONFIG_TCL_FILES) $(SYN_FILES) $(INC_FILES) $(XDC_FILES)
+	echo "open_project -quiet $(PROJECT).xpr" > $@
+	for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
+
+$(PROJECT).xpr: create_project.tcl update_config.tcl
+	vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x)
+
+# synthesis run
+$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES) $(INC_FILES) $(XDC_FILES) | $(PROJECT).xpr
+	echo "open_project $(PROJECT).xpr" > run_synth.tcl
+	echo "reset_run synth_1" >> run_synth.tcl
+	echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
+	echo "wait_on_run synth_1" >> run_synth.tcl
+	vivado -nojournal -nolog -mode batch -source run_synth.tcl
+
+# implementation run
+$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp
+	echo "open_project $(PROJECT).xpr" > run_impl.tcl
+	echo "reset_run impl_1" >> run_impl.tcl
+	echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
+	echo "wait_on_run impl_1" >> run_impl.tcl
+	echo "open_run impl_1" >> run_impl.tcl
+	echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl
+	echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl
+	vivado -nojournal -nolog -mode batch -source run_impl.tcl
+
+# output files (including potentially bit, bin, ltx, and xsa)
+$(PROJECT).bit $(PROJECT).bin $(PROJECT).ltx $(PROJECT).xsa: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp
+	echo "open_project $(PROJECT).xpr" > generate_bit.tcl
+	echo "open_run impl_1" >> generate_bit.tcl
+	echo "write_bitstream -force -bin_file $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl
+	echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl
+	echo "write_hw_platform -fixed -force -include_bit $(PROJECT).xsa" >> generate_bit.tcl
+	vivado -nojournal -nolog -mode batch -source generate_bit.tcl
+	ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit .
+	ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bin .
+	if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \
+	cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bin rev/$(PROJECT)_rev$$COUNT.bin; \
+	if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi; \
+	if [ -e $(PROJECT).xsa ]; then cp -pv $(PROJECT).xsa rev/$(PROJECT)_rev$$COUNT.xsa; fi
+
+###################################################################
+# Simulation targets
+###################################################################
+
+gen_ip:
+	echo "open_project $(PROJECT).xpr" > gen_ip.tcl
+	echo "generate_target all [get_ips *]" >> gen_ip.tcl
+	vivado -mode batch -source gen_ip.tcl
+
+
+sim: $(PROJECT).xpr gen_ip
+	echo "open_project $(PROJECT).xpr" > run_sim.tcl
+	echo "update_compile_order -fileset sources_1" >> run_sim.tcl
+	echo "update_compile_order -fileset sim_1" >> run_sim.tcl
+	echo "launch_simulation" >> run_sim.tcl
+	vivado -mode batch -source run_sim.tcl
+
+simclean:
+	-rm -rf xsim.dir *.wdb *.pb *.jou *.log *.vcd *.ltx
+	-rm -f defines_sim.v

software/console.py

@@ -0,0 +1,94 @@
+import argparse
+import socket
+
+
+def run_debug(args, sock):
+    """Debug run: send fixed values to test eth+ctrl on fpga."""
+    print(f"DEBUG MODE: ip={args.ip} send_port={args.send_port}")
+
+    dest = (args.ip, args.send_port)
+
+    # reset
+    sock.sendto(0x0f00.to_bytes(2), dest)
+    print("Sent soft_reset!")
+
+    # config data
+    sock.sendto(format_ctrl_data(0x12345678, 0x9abcdef0,
+                0x0bea, 0xdead, dac_bits=args.dac_bits), dest)
+    print("Config data sent!")
+
+    sock.sendto(0xf000.to_bytes(2), dest)
+    print("Sent start!")
+
+
+def format_ctrl_data(pulse_width: int, pulse_period: int,
+                     pulse_height: int, pulse_num: int, dac_bits: int = 16) -> bytes:
+    """Format data packet for set_data command."""
+    output = bytearray()
+
+    output += 0b10001000.to_bytes(1, 'little')
+
+    # no negative please
+    assert pulse_width > 0, "pulse_width should be positive"
+    assert pulse_period > 0, "pulse_period should be positive"
+    assert pulse_num > 0, "pulse_num should be positive"
+    assert pulse_height > 0, "pulse_height should be positive"
+
+    # overflow check
+    assert pulse_width < 2**32-1, "pulse_width too high"
+    assert pulse_period < 2**32-1, "pulse_period too high"
+    assert pulse_num < 2**16-1, "pulse_num too high"
+    assert pulse_height < 2**dac_bits-1, "pulse_height too high"
+
+    output += pulse_width.to_bytes(4, 'little')
+    output += pulse_period.to_bytes(4, 'little')
+    output += pulse_num.to_bytes(2, 'little')
+    output += pulse_height.to_bytes(2, 'little')
+
+    assert len(output) == 13, "Config data should be 96 bits + 8 bit header"
+    return output
+
+
+def run(args, sock):
+    pass
+
+
+def main():
+    parser = argparse.ArgumentParser(
+        description="Консоль для рефлектометра"
+    )
+
+    parser.add_argument("--debug", action='store_true',
+                        help="отладочная отправка пакета soft_reset, пакета с данными и пакета start")
+
+    parser.add_argument("--ip", type=str, default="192.168.0.2",
+                        help="IP рефлектометра, по умолчанию 192.168.0.2")
+
+    parser.add_argument("--send-port", type=int, default=8080,
+                        help="Порт для отправки команд")
+
+    parser.add_argument("--recv-port", type=int,
+                        default=8080, help="Порт для приема данных")
+
+    parser.add_argument("--dac-bits", type=int, default=12,
+                        help="Битность ЦАП (влияет на максимальный pulse_height)")
+
+    # передача параметров через аргументы
+    for arg in ("pulse_width", "pulse_period", "pulse_num", "pulse_height"):
+        parser.add_argument(f"--{arg}", type=int,
+                            default=0, help=f"Задать {arg}")
+
+    args = parser.parse_args()
+
+    sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)
+
+    if args.debug:
+        run_debug(args, sock)
+    else:
+        run(args, sock)
+
+    sock.close()
+
+
+if __name__ == "__main__":
+    main()