infra: update constraints to use unified ones for board and additional for debug nodes

.gitignore

@@ -1 +1,15 @@
 **build**
+
+# vivado project exclude
+**.hw
+**.ip_user_files
+**.cache
+**.gen
+**.runs
+**.sim
+**.srcs
+*.jou
+*.log
+*.rpt
+*.dcp
+.Xil

constraints/ax7a035b.xdc

@@ -0,0 +1,124 @@
+# === iostandard ===
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+
+# === SPI flash config ===
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
+set_property CONFIG_MODE SPIx4 [current_design]
+set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
+
+# === clock config ===
+create_clock -period 5.000 [get_ports sys_clk_p]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_p]
+set_property PACKAGE_PIN R4 [get_ports sys_clk_p]
+set_property PACKAGE_PIN T4 [get_ports sys_clk_n]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_n]
+
+
+# === reset button ===
+set_property PACKAGE_PIN F15 [get_ports rst_n]
+set_property IOSTANDARD LVCMOS33 [get_ports rst_n]
+
+# === status leds ===
+set_property PACKAGE_PIN L13 [get_ports {led[0]}]
+set_property PACKAGE_PIN M13 [get_ports {led[1]}]
+set_property PACKAGE_PIN K14 [get_ports {led[2]}]
+set_property PACKAGE_PIN K13 [get_ports {led[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[*]}]
+
+# === 1Gb ethernet PHY ===
+set_property PACKAGE_PIN P15 [get_ports rgmii_txc]
+set_property PACKAGE_PIN N14 [get_ports {rgmii_txd[0]}]
+set_property PACKAGE_PIN P16 [get_ports {rgmii_txd[1]}]
+set_property PACKAGE_PIN R17 [get_ports {rgmii_txd[2]}]
+set_property PACKAGE_PIN R16 [get_ports {rgmii_txd[3]}]
+set_property PACKAGE_PIN N17 [get_ports rgmii_txctl]
+set_property PACKAGE_PIN V18 [get_ports rgmii_rxc]
+set_property PACKAGE_PIN P19 [get_ports {rgmii_rxd[0]}]
+set_property PACKAGE_PIN U18 [get_ports {rgmii_rxd[1]}]
+set_property PACKAGE_PIN U17 [get_ports {rgmii_rxd[2]}]
+set_property PACKAGE_PIN P17 [get_ports {rgmii_rxd[3]}]
+set_property PACKAGE_PIN R19 [get_ports rgmii_rxctl]
+set_property PACKAGE_PIN N13 [get_ports e_mdc]
+set_property PACKAGE_PIN P14 [get_ports e_mdio]
+set_property PACKAGE_PIN R14 [get_ports e_reset]
+
+set_property IOSTANDARD LVCMOS33 [get_ports rgmii_txc]
+set_property IOSTANDARD LVCMOS33 [get_ports {rgmii_txd[*]}]
+set_property IOSTANDARD LVCMOS33 [get_ports rgmii_txctl]
+set_property IOSTANDARD LVCMOS33 [get_ports rgmii_rxc]
+set_property IOSTANDARD LVCMOS33 [get_ports {rgmii_rxd[*]}]
+set_property IOSTANDARD LVCMOS33 [get_ports rgmii_rxctl]
+set_property IOSTANDARD LVCMOS33 [get_ports e_mdc]
+set_property IOSTANDARD LVCMOS33 [get_ports e_mdio]
+set_property IOSTANDARD LVCMOS33 [get_ports e_reset]
+
+set_property SLEW FAST [get_ports rgmii_txc]
+set_property SLEW FAST [get_ports rgmii_txctl]
+set_property SLEW FAST [get_ports {rgmii_txd[*]}]
+create_clock -period 8.000 [get_ports rgmii_rxc]
+
+# === ADC an9238 (J11 header) ===
+set_property PACKAGE_PIN G21 [get_ports ch2_clk]
+set_property PACKAGE_PIN G22 [get_ports ch2_data[0]]
+set_property PACKAGE_PIN C22 [get_ports ch2_data[1]]
+set_property PACKAGE_PIN B22 [get_ports ch2_data[2]]
+set_property PACKAGE_PIN F19 [get_ports ch2_data[3]]
+set_property PACKAGE_PIN F20 [get_ports ch2_data[4]]
+set_property PACKAGE_PIN D20 [get_ports ch2_data[5]]
+set_property PACKAGE_PIN C20 [get_ports ch2_data[6]]
+set_property PACKAGE_PIN A18 [get_ports ch2_data[7]]
+set_property PACKAGE_PIN A19 [get_ports ch2_data[8]]
+set_property PACKAGE_PIN B20 [get_ports ch2_data[9]]
+set_property PACKAGE_PIN A20 [get_ports ch2_data[10]]
+set_property PACKAGE_PIN F18 [get_ports ch2_data[11]]
+set_property PACKAGE_PIN E18 [get_ports ch2_otr]
+set_property PACKAGE_PIN C18 [get_ports ch1_data[1]]
+set_property PACKAGE_PIN C19 [get_ports ch1_data[0]]
+set_property PACKAGE_PIN B17 [get_ports ch1_data[3]]
+set_property PACKAGE_PIN B18 [get_ports ch1_data[2]]
+set_property PACKAGE_PIN D17 [get_ports ch1_data[5]]
+set_property PACKAGE_PIN C17 [get_ports ch1_data[4]]
+set_property PACKAGE_PIN A15 [get_ports ch1_data[7]]
+set_property PACKAGE_PIN A16 [get_ports ch1_data[6]]
+set_property PACKAGE_PIN B15 [get_ports ch1_data[9]]
+set_property PACKAGE_PIN B16 [get_ports ch1_data[8]]
+set_property PACKAGE_PIN A13 [get_ports ch1_data[11]]
+set_property PACKAGE_PIN A14 [get_ports ch1_data[10]]
+set_property PACKAGE_PIN E16 [get_ports ch1_clk]
+set_property PACKAGE_PIN D16 [get_ports ch1_otr]
+
+set_property IOSTANDARD LVCMOS33 [get_ports ch2_clk]
+set_property IOSTANDARD LVCMOS33 [get_ports {ch2_data[*]}]
+set_property IOSTANDARD LVCMOS33 [get_ports ch2_otr]
+set_property IOSTANDARD LVCMOS33 [get_ports {ch1_data[*]}]
+set_property IOSTANDARD LVCMOS33 [get_ports ch1_clk]
+set_property IOSTANDARD LVCMOS33 [get_ports ch1_otr]
+
+set_property SLEW FAST [get_ports {ch2_clk ch1_clk}]
+
+# === DAC an9767 (J13 header) ===
+set_property PACKAGE_PIN AA9 [get_ports p2_clk]
+set_property PACKAGE_PIN AB10 [get_ports p2_wrt]
+set_property PACKAGE_PIN U16 [get_ports p2_data[13]]
+set_property PACKAGE_PIN T16 [get_ports p2_data[12]]
+set_property PACKAGE_PIN AA13 [get_ports p2_data[11]]
+set_property PACKAGE_PIN AB13 [get_ports p2_data[10]]
+set_property PACKAGE_PIN AB11 [get_ports p2_data[9]]
+set_property PACKAGE_PIN AB12 [get_ports p2_data[8]]
+set_property PACKAGE_PIN Y13 [get_ports p2_data[7]]
+set_property PACKAGE_PIN AA14 [get_ports p2_data[6]]
+set_property PACKAGE_PIN W14 [get_ports p2_data[5]]
+set_property PACKAGE_PIN Y14 [get_ports p2_data[4]]
+set_property PACKAGE_PIN Y16 [get_ports p2_data[3]]
+set_property PACKAGE_PIN AA16 [get_ports p2_data[2]]
+set_property PACKAGE_PIN AB16 [get_ports p2_data[1]]
+set_property PACKAGE_PIN AB17 [get_ports p2_data[0]]
+
+set_property IOSTANDARD LVCMOS33 [get_ports p2_clk]
+set_property IOSTANDARD LVCMOS33 [get_ports p2_wrt]
+set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[*]}]
+
+set_property SLEW FAST [get_ports {p2_clk}]
+
+

rtl/ethernet-udp/README.md

@@ -0,0 +1,54 @@
+# Ethernet UDP Stack
+
+Полный стек для Ethernet. Имеется поддержка ARP, ICMP (ping), и UDP. 
+- Рассчитан на скорость 1 ГБит/с
+- IP адреса устанавливаются заранее в axis_mac.sv
+- ARP и ICMP работают автоматически после инициализации модуля
+- Получаемые пейлоады по UDP выводятся через AXIS Master, когда получатель будет ready
+- Для отправки пейлоада по UDP используется сигнал-импульс send_req, который можно подать, когда модуль req_ready, после этого по готовности AXIS Slave можно начинать передавать данные пакета. Отправка следующего пакета будет доступна, когда данные предыдущего начнут отправляться (тоже сигнал req_ready).
+- Для прием имеется небольшая память на 2Кб. Пакет сначала помещается в нее и может быть отправлен по AXIS как только получатель готов. Если получатель не успевает принять полученный UDP пакет, то он может быть перезатерт новым.
+- Для отправки есть FIFO глубиной 2Кб. После запроса на отправку (send_req), при наполнении этого FIFO считается checksum пакета. Когда все data_length байт записаны - начинается отправка пакетов. Когда первые байты ушли - можно начинать передачу байт следующего пакета.
+## Структура src
+```
+├── eth - исходный код ethernet модуля
+│   ├── arbi - арбитер RGMII <-> GMII
+│   │   ├── gmii_arbi.v
+│   │   ├── gmii_rx_buffer.v
+│   │   └── gmii_tx_buffer.v
+│   ├── axis_mac.sv - обертка для AXIS
+│   ├── mac - основные файлы MAC части
+│   │   ├── arp_cache.v
+│   │   ├── crc.v
+│   │   ├── icmp_reply.v
+│   │   ├── mac_test.v
+│   │   ├── mac_top.v
+│   │   ├── rx - прием
+│   │   │   ├── arp_rx.v
+│   │   │   ├── ip_rx.v
+│   │   │   ├── mac_rx_top.v
+│   │   │   ├── mac_rx.v
+│   │   │   └── udp_rx.v
+│   │   └── tx - отправка
+│   │       ├── arp_tx.v
+│   │       ├── ip_tx_mode.v
+│   │       ├── ip_tx.v
+│   │       ├── mac_tx_mode.v
+│   │       ├── mac_tx_top.v
+│   │       ├── mac_tx.v
+│   │       └── udp_tx.v
+│   ├── reset.v
+│   └── util_gmii_to_rgmii.v
+└── ip: XCI файлы ip блоков 
+```
+
+## Тесты
+В tests есть Testbench, эмулирующий прием и отправку пакетов (test_axis_mac_rx.sv), а также имеются следующие тестовые проекты для отладки на ПЛИС AX7A035B:
+- Симуляция запускается в eth_axis через ```make sim```
+- eth_minimal - минимальный проект для теста PHY части. По умолчанию просто отправляет UDP пакет с фиксированным содержимым Hello ALINX на заданный IP. Если отправить UDP - то начнется трансляция пейлоада из принятого пакета.
+- eth_axis - проект с axis_mac и своеобразным echo-loopback. Начинает с ARP запроса, если получает ответ - то готов к работе. Можно отправлять UDP и получать эхо в ответ.
+
+## Сборка
+- Для сборки используется make
+- Собрать все вплоть до битстрима: ```make all```
+- Создать (если нету) и открыть вивадовский проект: ```make vivado```
+- По умолчанию в проектах используются IP 192.168.0.2 для платы и 192.168.0.3 для хоста, порт 8080 и на отправку, и на получение

rtl/ethernet-udp/src/eth/axis_mac.sv

@@ -0,0 +1,435 @@
+// ethernet MAC with axi stream IO with UDP
+
+`timescale 1 ns / 1 ns
+
+module axis_mac
+(
+    input                rst_n,
+    input                gmii_tx_clk,
+    input                gmii_rx_clk,
+    input                gmii_rx_dv,
+    input  [7:0]         gmii_rxd,
+
+    output reg           gmii_tx_en,
+    output reg [7:0]     gmii_txd,
+
+    // AXI-stream RX output (clock domain = gmii_rx_clk)
+    (* MARK_DEBUG="true" *)output reg  [7:0]    m_axis_rx_tdata,
+    (* MARK_DEBUG="true" *)output reg           m_axis_rx_tvalid,
+    (* MARK_DEBUG="true" *)input  wire          m_axis_rx_tready,
+    (* MARK_DEBUG="true" *)output reg           m_axis_rx_tlast,
+    (* MARK_DEBUG="true" *)output wire [15:0]   udp_rec_data_length,
+
+    // tx part
+    (* MARK_DEBUG="true" *)input  wire        send_req,
+    input  wire [15:0] data_length,
+    (* MARK_DEBUG="true" *)output reg         req_ready,
+
+    (* MARK_DEBUG="true" *)input  wire [7:0]  s_axis_tx_tdata,
+    (* MARK_DEBUG="true" *)input  wire        s_axis_tx_tvalid,
+    (* MARK_DEBUG="true" *)output reg         s_axis_tx_tready,
+    (* MARK_DEBUG="true" *)input  wire        s_axis_tx_tlast
+);
+
+    // ----------------------------------------------------------------
+    // GMII RX input registering
+    // ----------------------------------------------------------------
+    reg        gmii_rx_dv_d0;
+    reg [7:0]  gmii_rxd_d0;
+
+    always @(posedge gmii_rx_clk or negedge rst_n) begin
+        if (!rst_n) begin
+            gmii_rx_dv_d0 <= 1'b0;
+            gmii_rxd_d0   <= 8'd0;
+        end else begin
+            gmii_rx_dv_d0 <= gmii_rx_dv;
+            gmii_rxd_d0   <= gmii_rxd;
+        end
+    end
+
+    // ----------------------------------------------------------------
+    // TX path from mac_top
+    // ----------------------------------------------------------------
+    wire       gmii_tx_en_tmp;
+    wire [7:0] gmii_txd_tmp;
+
+    always @(posedge gmii_tx_clk or negedge rst_n) begin
+        if (!rst_n) begin
+            gmii_tx_en <= 1'b0;
+            gmii_txd   <= 8'd0;
+        end else begin
+            gmii_tx_en <= gmii_tx_en_tmp;
+            gmii_txd   <= gmii_txd_tmp;
+        end
+    end
+
+    // TX signals
+    reg  [7:0]  tx_ram_wr_data;
+    reg         tx_ram_wr_en;
+    reg  [15:0] udp_send_data_length;
+    reg         udp_tx_req;
+    reg         arp_request_req;
+    wire        mac_send_end;
+
+    wire        udp_ram_data_req;
+    wire        udp_tx_end;
+    wire        almost_full;
+    (* MARK_DEBUG="true" *)wire        arp_found;
+    wire        mac_not_exist;
+    wire [15:0] udp_ram_data_count;
+
+    // RX signals
+    reg  [10:0] udp_rec_ram_read_addr;
+    wire [7:0]  udp_rec_ram_rdata;
+    
+    wire        udp_rec_data_valid;
+
+    mac_top mac_top0 (
+        .gmii_tx_clk               (gmii_tx_clk),
+        .gmii_rx_clk               (gmii_rx_clk),
+        .rst_n                     (rst_n),
+
+        .source_mac_addr           (48'h00_0a_35_01_fe_c0),
+        .TTL                       (8'h80),
+        .source_ip_addr            (32'hc0a80002),   // 192.168.0.2
+        .destination_ip_addr       (32'hc0a80003),   // 192.168.0.3
+        .udp_send_source_port      (16'h1f90),       // 8080
+        .udp_send_destination_port (16'h1f90),       // 8080
+
+        .ram_wr_data               (tx_ram_wr_data),
+        .ram_wr_en                 (tx_ram_wr_en),
+        .udp_ram_data_req          (udp_ram_data_req),
+        .udp_send_data_length      (udp_send_data_length),
+        .udp_tx_end                (udp_tx_end),
+        .almost_full               (almost_full),
+
+        .udp_tx_req                (udp_tx_req),
+        .arp_request_req           (arp_request_req),
+
+        .mac_send_end              (mac_send_end),
+        .mac_data_valid            (gmii_tx_en_tmp),
+        .mac_tx_data               (gmii_txd_tmp),
+
+        .rx_dv                     (gmii_rx_dv_d0),
+        .mac_rx_datain             (gmii_rxd_d0),
+
+        .udp_rec_ram_rdata         (udp_rec_ram_rdata),
+        .udp_rec_ram_read_addr     (udp_rec_ram_read_addr),
+        .udp_rec_data_length       (udp_rec_data_length),
+        .udp_rec_data_valid        (udp_rec_data_valid),
+
+        .arp_found                 (arp_found),
+        .mac_not_exist             (mac_not_exist)
+    );
+
+    // Detect "new packet ready" on udp_rec_data_valid rising edge
+    reg udp_rec_data_valid_d0;
+
+    always @(posedge gmii_rx_clk or negedge rst_n) begin
+        if (!rst_n)
+            udp_rec_data_valid_d0 <= 1'b0;
+        else
+            udp_rec_data_valid_d0 <= udp_rec_data_valid;
+    end
+
+    wire udp_pkt_done = udp_rec_data_valid & ~udp_rec_data_valid_d0;
+
+    // ----------------------------------------------------------------
+    // RX RAM -> AXI-stream bridge
+    //
+    // Assumption:
+    //   udp_rec_data_length includes 8-byte UDP header,
+    //   so payload length = udp_rec_data_length - 8
+    //
+    // This implementation is simple and safe:
+    // - start on udp_pkt_done
+    // - read bytes 0 .. payload_len-1 from RX RAM
+    // - output them on AXIS
+    //
+    // ----------------------------------------------------------------
+    localparam RX_IDLE  = 2'd0;
+    localparam RX_NOTREADY  = 2'd1;
+    localparam RX_START  = 2'd2;
+    localparam RX_DATA  = 2'd3;
+
+    (* MARK_DEBUG="true" *) reg [1:0]  rx_state;
+    (* MARK_DEBUG="true" *) reg [15:0] rx_payload_len;
+    (* MARK_DEBUG="true" *) reg [15:0] rx_index;
+
+    always @(posedge gmii_rx_clk or negedge rst_n) begin
+        if (!rst_n) begin
+            rx_state              <= RX_IDLE;
+            rx_payload_len        <= 16'd0;
+            rx_index              <= 16'd0;
+            udp_rec_ram_read_addr <= 11'd0;
+
+            m_axis_rx_tdata       <= 8'd0;
+            m_axis_rx_tvalid      <= 1'b0;
+            m_axis_rx_tlast       <= 1'b0;
+
+        end else begin
+            case (rx_state)
+                RX_IDLE: begin
+                    m_axis_rx_tvalid <= 1'b0;
+                    m_axis_rx_tlast  <= 1'b0;
+                    rx_index         <= 16'd0;
+                    udp_rec_ram_read_addr <= 11'd0;
+
+                    if (udp_pkt_done) begin
+                        // protect against pathological short values
+                        if (udp_rec_data_length > 16'd8) begin
+                            rx_payload_len        <= udp_rec_data_length - 16'd8;
+                            udp_rec_ram_read_addr <= 11'd0;   // issue read for byte 0
+                            rx_state              <= RX_NOTREADY;
+                        end else begin
+                            rx_payload_len <= 16'd0;
+                            rx_state       <= RX_IDLE;
+                        end
+                    end
+                end
+
+                // one cycle for synchronous BRAM read latency
+                RX_NOTREADY: begin
+                    m_axis_rx_tvalid <= 1'b0;
+                    m_axis_rx_tlast  <= 1'b0;
+
+                    if (m_axis_rx_tready)
+                        rx_state         <= RX_START;
+                end
+
+                RX_START: begin
+                    if (m_axis_rx_tready) begin
+                        // put current data
+                        // end of data?
+                        if (rx_index == (rx_payload_len - 1)) begin
+                            rx_state <= RX_IDLE;
+                        end else begin 
+                            rx_state <= RX_DATA;
+                        end
+
+                        // always increment pointer
+                        rx_index <= rx_index + 1'b1;
+                        udp_rec_ram_read_addr <= rx_index + 1'b1; // next byte
+                    end else begin 
+                        rx_state <= RX_NOTREADY;
+
+                    end
+                end
+
+                RX_DATA: begin
+                    // hold valid until accepted
+                    if (!m_axis_rx_tready) begin
+                        // take a break while not ready
+                        m_axis_rx_tvalid <= m_axis_rx_tvalid;
+                        m_axis_rx_tlast  <= m_axis_rx_tlast;
+                        rx_state         <= RX_NOTREADY;
+                        // reset increment
+                        rx_index <= rx_index - 1'b1;
+                        udp_rec_ram_read_addr <= rx_index - 1'b1;
+                    end else begin
+                        // present current byte from RAM
+                        m_axis_rx_tdata  <= udp_rec_ram_rdata;
+                        m_axis_rx_tvalid <= 1'b1;
+                        m_axis_rx_tlast  <= (rx_index == (rx_payload_len));
+                        if (rx_index == (rx_payload_len)) begin
+                            // last byte accepted immediately if ready=1,
+                            // otherwise valid/last remain asserted until ready
+                            rx_state <= RX_IDLE;
+                        end
+
+                        rx_index <= rx_index + 1'b1;
+                        udp_rec_ram_read_addr <= rx_index + 1'b1; // next byte
+                    end
+                end
+
+                default: begin
+                    rx_state         <= RX_IDLE;
+                    m_axis_rx_tvalid <= 1'b0;
+                    m_axis_rx_tlast  <= 1'b0;
+                end
+            endcase
+        end
+    end
+
+    // ----------------------------------------------------------------
+    // TX FSM
+    // Semantics:
+    //   - send_req/data_length form a packet send request
+    //   - udp_tx_req is held HIGH until udp_ram_data_req pulses
+    //   - udp_ram_data_req is a pulse - start feeding payload now to RAM
+    //   - AXIS ready is asserted only during payload write phase
+    // ----------------------------------------------------------------
+    
+    
+    localparam TX_IDLE         = 3'd0;
+    localparam TX_ARP_REQ      = 3'd1;
+    localparam TX_ARP_SEND     = 3'd2;
+    localparam TX_WAIT_ARP     = 3'd3;
+    localparam TX_WAIT_RAM_REQ = 3'd4;
+    localparam TX_STREAM       = 3'd5;
+    localparam TX_WAIT_DRAIN   = 3'd6;
+
+    (* MARK_DEBUG="true" *)reg [2:0]  tx_state;
+    
+    assign arp_request_req  = (tx_state == TX_ARP_REQ) ;
+
+    reg [15:0] tx_req_len;
+    reg [15:0] tx_bytes_written;
+    reg [15:0] tx_release_threshold;
+
+    reg        tx_req_inflight;
+    
+    // register for long arp timeout, if no got no response
+    reg [31:0] arp_delay;
+    reg arp_cached;
+
+    always @(posedge gmii_tx_clk or negedge rst_n) begin
+        if (!rst_n) begin
+            tx_state             <= TX_IDLE;
+
+            tx_ram_wr_data       <= 8'd0;
+            arp_cached           <= 1'b0;
+            tx_ram_wr_en         <= 1'b0;
+            udp_send_data_length <= 16'd0;
+            udp_tx_req           <= 1'b0;
+            arp_delay            <= 32'b0;
+
+            s_axis_tx_tready     <= 1'b0;
+            req_ready            <= 1'b0;
+
+            tx_req_len           <= 16'd0;
+            tx_bytes_written     <= 16'd0;
+            tx_release_threshold <= 16'd0;
+
+            tx_req_inflight      <= 1'b0;
+        end else begin
+            // defaults
+            tx_ram_wr_en    <= 1'b0;
+
+            case (tx_state)
+                // Ready to accept a new packet request
+                TX_IDLE: begin
+                    udp_tx_req       <= 1'b0;
+                    s_axis_tx_tready <= 1'b0;
+                    tx_bytes_written <= 16'd0;
+                    tx_req_inflight  <= 1'b0;
+
+                    req_ready <= arp_cached && !almost_full;
+
+                    if (send_req && req_ready) begin
+                        tx_req_len           <= data_length;
+                        udp_send_data_length <= data_length;
+                        tx_req_inflight      <= 1'b1;
+
+                        // threshold for allowing next packet
+                        // to be written to the RAM
+                        if (data_length > 16'd16)
+                            tx_release_threshold <= data_length - 16'd16;
+                        else
+                            tx_release_threshold <= 16'd0;
+
+                            tx_state <= TX_WAIT_RAM_REQ;
+                    end
+                    
+                    // arp check
+                    if (!arp_cached) begin
+                        tx_state <= TX_ARP_REQ;
+                    end
+                end
+
+                // Pulse ARP request
+                TX_ARP_REQ: begin
+                    req_ready        <= 1'b0;
+                    s_axis_tx_tready <= 1'b0;
+                    udp_tx_req       <= 1'b0;
+                    
+                    arp_delay        <= 32'ha000000;
+                    tx_state         <= TX_ARP_SEND;
+                end
+
+                // Wait until ARP is resolved
+                TX_ARP_SEND: begin
+                    req_ready        <= 1'b0;
+                    s_axis_tx_tready <= 1'b0;
+                    udp_tx_req       <= 1'b0;
+
+                    // sent
+                    if (mac_send_end)
+                        tx_state <= TX_WAIT_ARP;
+                end
+                
+                // wait for ARP response
+                TX_WAIT_ARP: begin
+                    if (arp_found) begin
+                        arp_cached <= 1'b1;
+                        tx_state <= TX_IDLE;
+                    end
+                    
+                    // timeout to not spam ARPs
+                    if (arp_delay == 32'b0) begin
+                        // re-try
+                        tx_state <= TX_ARP_REQ;
+                    end else begin
+                        // wait
+                        arp_delay = arp_delay - 32'b1;
+                    end 
+                    
+                end
+
+                // Hold udp_tx_req until udp_ram_data_req pulse arrives
+                TX_WAIT_RAM_REQ: begin
+                    req_ready        <= 1'b0;
+                    udp_tx_req       <= 1'b1;
+
+                    if (udp_ram_data_req) begin
+                        udp_tx_req       <= 1'b0;
+                        s_axis_tx_tready <= 1'b1;
+                        tx_state         <= TX_STREAM;
+                    end
+                end
+
+                // Accept AXIS bytes and write them into TX RAM
+                TX_STREAM: begin
+                    req_ready  <= 1'b0;
+                    udp_tx_req <= 1'b0;
+
+                    // keep ready high while receiving payload bytes
+                    s_axis_tx_tready <= (tx_bytes_written < tx_req_len);
+
+                    if (s_axis_tx_tvalid && s_axis_tx_tready) begin
+                        tx_ram_wr_data <= s_axis_tx_tdata;
+                        tx_ram_wr_en   <= 1'b1;
+
+                        tx_bytes_written <= tx_bytes_written + 1'b1;
+
+                        if (tx_bytes_written + 1'b1 >= tx_req_len) begin
+                            s_axis_tx_tready <= 1'b0;
+                            tx_state         <= TX_WAIT_DRAIN;
+                        end
+                    end
+                end
+
+                // Packet payload is already in RAM.
+                // Wait until TX RAM starts draining enough to allow
+                // the next request.
+                TX_WAIT_DRAIN: begin
+                    s_axis_tx_tready <= 1'b0;
+                    udp_tx_req       <= 1'b0;
+
+                    if (udp_ram_data_count <= tx_release_threshold)
+                        tx_state <= TX_IDLE;
+
+                end
+
+                default: begin
+                    tx_state         <= TX_IDLE;
+                    tx_ram_wr_en     <= 1'b0;
+                    udp_tx_req       <= 1'b0;
+                    s_axis_tx_tready <= 1'b0;
+                    req_ready        <= 1'b0;
+                end
+            endcase
+        end
+    end
+
+endmodule

rtl/ethernet-udp/src/eth/mac/mac_test.v

@@ -4,7 +4,7 @@
 //Description :
 //
 //////////////////////////////////////////////////////////////////////////////////////
-//`define TEST_SPEED
+`define TEST_SPEED
 `timescale 1 ns/1 ns
 module mac_test
 (
@@ -74,7 +74,7 @@ parameter WAIT          = 9'b010_000_000 ;
 parameter CHECK_ARP     = 9'b100_000_000 ;
 
 
-reg [8:0]    state  ;
+(* MARK_DEBUG="true" *)  reg [8:0]    state  ;
 reg [8:0]    next_state ;
 reg  [15:0]  ram_cnt ;
 reg    almost_full_d0 ;
@@ -278,7 +278,7 @@ always@(posedge gmii_rx_clk or negedge rst_n)
 		udp_send_data_length <= udp_rec_data_length - 8  ;
 	 else
 	 `ifdef TEST_SPEED 
-       udp_send_data_length <= 16'd1000 ;	 
+       udp_send_data_length <= 16'd100 ;	 
 	 `else	 
 	   udp_send_data_length <= 4*UDP_DEPTH ;
 	 `endif

rtl/ethernet-udp/src/eth/mac/mac_top.v

@@ -1,8 +1,6 @@
-//////////////////////////////////////////////////////////////////////////////////////
-//Module Name : mac_top
-//Description :
-//
-//////////////////////////////////////////////////////////////////////////////////////
+// Top module for base ethernet operations
+// inheireted from Alinx
+
 `timescale 1 ns/1 ns
 module mac_top
        (
@@ -37,6 +35,7 @@ module mac_top
          input  [10:0]        udp_rec_ram_read_addr,
          output [15:0]        udp_rec_data_length,
          output               udp_rec_data_valid,
+         output [11:0]        udp_ram_data_count,
          
          output               arp_found,
          output               mac_not_exist
@@ -81,6 +80,7 @@ mac_tx_top mac_tx0
             .arp_rec_source_ip_addr      (arp_rec_source_ip_addr ),
             .arp_rec_source_mac_addr     (arp_rec_source_mac_addr ),
             .arp_request_req             (arp_request_req ),
+            .udp_ram_data_count          (udp_ram_data_count ),
             
             
             .ram_wr_data                 (ram_wr_data) ,

rtl/ethernet-udp/src/eth/mac/tx/mac_tx_top.v

@@ -31,8 +31,9 @@ module mac_tx_top
          (* MARK_DEBUG="true" *)input  [15:0]        udp_send_data_length,
          (* MARK_DEBUG="true" *)output               udp_tx_end,
          (* MARK_DEBUG="true" *)output               almost_full,
+         (* MARK_DEBUG="true" *)output [11:0]        udp_ram_data_count,
          
-         output               upper_data_req,
+         (* MARK_DEBUG="true" *)output               upper_data_req,
          input                icmp_tx_ready,
          input  [7:0]         icmp_tx_data,
          input                icmp_tx_end,
@@ -251,7 +252,8 @@ udp_tx udp0
          .udp_tx_ready                   (udp_tx_ready               ),
          .udp_tx_data                    (udp_tx_data                ),
          .udp_tx_end                     (udp_tx_end                 ),
-         .almost_full                    (almost_full                )        
+         .almost_full                    (almost_full                ),
+         .udp_ram_data_count             (udp_ram_data_count         )       
        ) ;
        
 endmodule

rtl/ethernet-udp/src/eth/mac/tx/udp_tx.v

@@ -27,13 +27,14 @@ module udp_tx
           output reg               udp_tx_ready,
           output reg [7:0]         udp_tx_data,
           output reg               udp_tx_end,
-          output                   almost_full
+          output                   almost_full,
+          output     [11:0]        udp_ram_data_count
          
        ) ;
        
 
 reg                       ram_rd_en ;
-wire [3:0]                usedw     ;
+(* MARK_DEBUG="true" *) wire [3:0]                usedw     ;
 reg  [3:0]                fifo_count ;
 
 reg  [7:0]                ram_rdata_d0  ;
@@ -62,7 +63,7 @@ parameter UDP_SEND          = 6'b010000 ;
 parameter UDP_END           = 6'b100000 ;
 
 
-reg [5:0]    state  ;
+(* MARK_DEBUG="true" *) reg [5:0]    state  ;
 reg [5:0]    next_state ;
 
 
@@ -222,7 +223,7 @@ udp_tx_data_fifo tx_data_fifo
     .full         (               ),                // output wire full
     .almost_full  (almost_full    ),  // output wire almost_full
     .empty        (               ),              // output wire empty
-    .data_count   (               )    // output wire [11 : 0] data_count
+    .data_count   (udp_ram_data_count )    // output wire [11 : 0] data_count
   );
 
 
@@ -356,7 +357,7 @@ udp_tx_data_fifo tx_data_fifo
   localparam GEN_CHECKSUM_END  = 6'b010000 ;
   localparam CHECKSUM_WAIT     = 6'b100000 ;
   
-  reg [5:0]    ck_state  ;
+  (* MARK_DEBUG="true" *) reg [5:0]    ck_state  ;
   reg [5:0]    ck_next_state ;
   
   always @(posedge clk or negedge rst_n)

rtl/ethernet-udp/src/eth/util_gmii_to_rgmii.v

@@ -180,7 +180,7 @@ module util_gmii_to_rgmii (
          .DELAY_SRC("IDATAIN"),           // Delay input (IDATAIN, DATAIN)
          .HIGH_PERFORMANCE_MODE("FALSE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
          .IDELAY_TYPE("FIXED"),           // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
-         .IDELAY_VALUE(16),                // Input delay tap setting (0-31)
+         .IDELAY_VALUE(16),                // Input delay tap setting (0-31) May be changed for more stability
          .PIPE_SEL("FALSE"),              // Select pipelined mode, FALSE, TRUE
          .REFCLK_FREQUENCY(200.0),        // IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
          .SIGNAL_PATTERN("DATA")          // DATA, CLOCK input signal

rtl/ethernet-udp/tests/eth_axis/Makefile

@@ -8,13 +8,13 @@
 
 # FPGA settings
 FPGA_PART = xc7a35tfgg484-1
-FPGA_TOP = ethernet_test_minimal
+FPGA_TOP = ethernet_axis_echo
 FPGA_ARCH = artix7
 
 RTL_DIR = ../../src
 
 # Files for synthesis
-SYN_FILES = ethernet_test_minimal.v
+SYN_FILES = ethernet_axis_echo.v
 
 include ../../../../scripts/vivado.mk
 
@@ -22,6 +22,12 @@ SYN_FILES += $(sort $(shell find ../../src -type f \( -name '*.v' -o -name '*.sv
 
 XCI_FILES = $(sort $(shell find ../../src -type f -name '*.xci'))
 
+XDC_FILES += debug.xdc
+XDC_FILES += ../../../../constraints/ax7a035b.xdc
+
+SIM_TOP = tb_mac_test
+TB_FILES = test_axis_mac_rx.sv
+
 program: $(PROJECT).bit
 	echo "open_hw_manager" > program.tcl
 	echo "connect_hw_server" >> program.tcl

rtl/ethernet-udp/tests/eth_axis/debug.xdc

@@ -0,0 +1,260 @@
+# debug ila
+
+create_debug_core u_ila_0 ila
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
+set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
+set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
+set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
+set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
+set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
+set_property port_width 1 [get_debug_ports u_ila_0/clk]
+connect_debug_port u_ila_0/clk [get_nets [list rgmii_rxc_IBUF_BUFG]]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
+set_property port_width 8 [get_debug_ports u_ila_0/probe0]
+connect_debug_port u_ila_0/probe0 [get_nets [list {arbi_inst/rx_buffer_inst/e10_100_rxd[0]} {arbi_inst/rx_buffer_inst/e10_100_rxd[1]} {arbi_inst/rx_buffer_inst/e10_100_rxd[2]} {arbi_inst/rx_buffer_inst/e10_100_rxd[3]} {arbi_inst/rx_buffer_inst/e10_100_rxd[4]} {arbi_inst/rx_buffer_inst/e10_100_rxd[5]} {arbi_inst/rx_buffer_inst/e10_100_rxd[6]} {arbi_inst/rx_buffer_inst/e10_100_rxd[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
+set_property port_width 8 [get_debug_ports u_ila_0/probe1]
+connect_debug_port u_ila_0/probe1 [get_nets [list {arbi_inst/gmii_rxd[0]} {arbi_inst/gmii_rxd[1]} {arbi_inst/gmii_rxd[2]} {arbi_inst/gmii_rxd[3]} {arbi_inst/gmii_rxd[4]} {arbi_inst/gmii_rxd[5]} {arbi_inst/gmii_rxd[6]} {arbi_inst/gmii_rxd[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
+set_property port_width 8 [get_debug_ports u_ila_0/probe2]
+connect_debug_port u_ila_0/probe2 [get_nets [list {arbi_inst/gmii_txd[0]} {arbi_inst/gmii_txd[1]} {arbi_inst/gmii_txd[2]} {arbi_inst/gmii_txd[3]} {arbi_inst/gmii_txd[4]} {arbi_inst/gmii_txd[5]} {arbi_inst/gmii_txd[6]} {arbi_inst/gmii_txd[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
+set_property port_width 8 [get_debug_ports u_ila_0/probe3]
+connect_debug_port u_ila_0/probe3 [get_nets [list {arbi_inst/e_txd[0]} {arbi_inst/e_txd[1]} {arbi_inst/e_txd[2]} {arbi_inst/e_txd[3]} {arbi_inst/e_txd[4]} {arbi_inst/e_txd[5]} {arbi_inst/e_txd[6]} {arbi_inst/e_txd[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
+set_property port_width 8 [get_debug_ports u_ila_0/probe4]
+connect_debug_port u_ila_0/probe4 [get_nets [list {arbi_inst/e_rxd[0]} {arbi_inst/e_rxd[1]} {arbi_inst/e_rxd[2]} {arbi_inst/e_rxd[3]} {arbi_inst/e_rxd[4]} {arbi_inst/e_rxd[5]} {arbi_inst/e_rxd[6]} {arbi_inst/e_rxd[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
+set_property port_width 16 [get_debug_ports u_ila_0/probe5]
+connect_debug_port u_ila_0/probe5 [get_nets [list {arbi_inst/tx_buffer_inst/tx_data_cnt[0]} {arbi_inst/tx_buffer_inst/tx_data_cnt[1]} {arbi_inst/tx_buffer_inst/tx_data_cnt[2]} {arbi_inst/tx_buffer_inst/tx_data_cnt[3]} {arbi_inst/tx_buffer_inst/tx_data_cnt[4]} {arbi_inst/tx_buffer_inst/tx_data_cnt[5]} {arbi_inst/tx_buffer_inst/tx_data_cnt[6]} {arbi_inst/tx_buffer_inst/tx_data_cnt[7]} {arbi_inst/tx_buffer_inst/tx_data_cnt[8]} {arbi_inst/tx_buffer_inst/tx_data_cnt[9]} {arbi_inst/tx_buffer_inst/tx_data_cnt[10]} {arbi_inst/tx_buffer_inst/tx_data_cnt[11]} {arbi_inst/tx_buffer_inst/tx_data_cnt[12]} {arbi_inst/tx_buffer_inst/tx_data_cnt[13]} {arbi_inst/tx_buffer_inst/tx_data_cnt[14]} {arbi_inst/tx_buffer_inst/tx_data_cnt[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
+set_property port_width 8 [get_debug_ports u_ila_0/probe6]
+connect_debug_port u_ila_0/probe6 [get_nets [list {arbi_inst/tx_buffer_inst/tx_rdata[0]} {arbi_inst/tx_buffer_inst/tx_rdata[1]} {arbi_inst/tx_buffer_inst/tx_rdata[2]} {arbi_inst/tx_buffer_inst/tx_rdata[3]} {arbi_inst/tx_buffer_inst/tx_rdata[4]} {arbi_inst/tx_buffer_inst/tx_rdata[5]} {arbi_inst/tx_buffer_inst/tx_rdata[6]} {arbi_inst/tx_buffer_inst/tx_rdata[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
+set_property port_width 8 [get_debug_ports u_ila_0/probe7]
+connect_debug_port u_ila_0/probe7 [get_nets [list {arbi_inst/tx_buffer_inst/tx_wdata[0]} {arbi_inst/tx_buffer_inst/tx_wdata[1]} {arbi_inst/tx_buffer_inst/tx_wdata[2]} {arbi_inst/tx_buffer_inst/tx_wdata[3]} {arbi_inst/tx_buffer_inst/tx_wdata[4]} {arbi_inst/tx_buffer_inst/tx_wdata[5]} {arbi_inst/tx_buffer_inst/tx_wdata[6]} {arbi_inst/tx_buffer_inst/tx_wdata[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
+set_property port_width 6 [get_debug_ports u_ila_0/probe8]
+connect_debug_port u_ila_0/probe8 [get_nets [list {axis_mac0/mac_top0/mac_tx0/udp0/ck_state[0]} {axis_mac0/mac_top0/mac_tx0/udp0/ck_state[1]} {axis_mac0/mac_top0/mac_tx0/udp0/ck_state[2]} {axis_mac0/mac_top0/mac_tx0/udp0/ck_state[3]} {axis_mac0/mac_top0/mac_tx0/udp0/ck_state[4]} {axis_mac0/mac_top0/mac_tx0/udp0/ck_state[5]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
+set_property port_width 16 [get_debug_ports u_ila_0/probe9]
+connect_debug_port u_ila_0/probe9 [get_nets [list {axis_mac0/udp_rec_data_length[0]} {axis_mac0/udp_rec_data_length[1]} {axis_mac0/udp_rec_data_length[2]} {axis_mac0/udp_rec_data_length[3]} {axis_mac0/udp_rec_data_length[4]} {axis_mac0/udp_rec_data_length[5]} {axis_mac0/udp_rec_data_length[6]} {axis_mac0/udp_rec_data_length[7]} {axis_mac0/udp_rec_data_length[8]} {axis_mac0/udp_rec_data_length[9]} {axis_mac0/udp_rec_data_length[10]} {axis_mac0/udp_rec_data_length[11]} {axis_mac0/udp_rec_data_length[12]} {axis_mac0/udp_rec_data_length[13]} {axis_mac0/udp_rec_data_length[14]} {axis_mac0/udp_rec_data_length[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
+set_property port_width 3 [get_debug_ports u_ila_0/probe10]
+connect_debug_port u_ila_0/probe10 [get_nets [list {axis_mac0/tx_state[0]} {axis_mac0/tx_state[1]} {axis_mac0/tx_state[2]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
+set_property port_width 8 [get_debug_ports u_ila_0/probe11]
+connect_debug_port u_ila_0/probe11 [get_nets [list {axis_mac0/s_axis_tx_tdata[0]} {axis_mac0/s_axis_tx_tdata[1]} {axis_mac0/s_axis_tx_tdata[2]} {axis_mac0/s_axis_tx_tdata[3]} {axis_mac0/s_axis_tx_tdata[4]} {axis_mac0/s_axis_tx_tdata[5]} {axis_mac0/s_axis_tx_tdata[6]} {axis_mac0/s_axis_tx_tdata[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
+set_property port_width 2 [get_debug_ports u_ila_0/probe12]
+connect_debug_port u_ila_0/probe12 [get_nets [list {axis_mac0/rx_state[0]} {axis_mac0/rx_state[1]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
+set_property port_width 16 [get_debug_ports u_ila_0/probe13]
+connect_debug_port u_ila_0/probe13 [get_nets [list {axis_mac0/rx_payload_len[0]} {axis_mac0/rx_payload_len[1]} {axis_mac0/rx_payload_len[2]} {axis_mac0/rx_payload_len[3]} {axis_mac0/rx_payload_len[4]} {axis_mac0/rx_payload_len[5]} {axis_mac0/rx_payload_len[6]} {axis_mac0/rx_payload_len[7]} {axis_mac0/rx_payload_len[8]} {axis_mac0/rx_payload_len[9]} {axis_mac0/rx_payload_len[10]} {axis_mac0/rx_payload_len[11]} {axis_mac0/rx_payload_len[12]} {axis_mac0/rx_payload_len[13]} {axis_mac0/rx_payload_len[14]} {axis_mac0/rx_payload_len[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
+set_property port_width 16 [get_debug_ports u_ila_0/probe14]
+connect_debug_port u_ila_0/probe14 [get_nets [list {axis_mac0/rx_index[0]} {axis_mac0/rx_index[1]} {axis_mac0/rx_index[2]} {axis_mac0/rx_index[3]} {axis_mac0/rx_index[4]} {axis_mac0/rx_index[5]} {axis_mac0/rx_index[6]} {axis_mac0/rx_index[7]} {axis_mac0/rx_index[8]} {axis_mac0/rx_index[9]} {axis_mac0/rx_index[10]} {axis_mac0/rx_index[11]} {axis_mac0/rx_index[12]} {axis_mac0/rx_index[13]} {axis_mac0/rx_index[14]} {axis_mac0/rx_index[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
+set_property port_width 8 [get_debug_ports u_ila_0/probe15]
+connect_debug_port u_ila_0/probe15 [get_nets [list {axis_mac0/m_axis_rx_tdata[0]} {axis_mac0/m_axis_rx_tdata[1]} {axis_mac0/m_axis_rx_tdata[2]} {axis_mac0/m_axis_rx_tdata[3]} {axis_mac0/m_axis_rx_tdata[4]} {axis_mac0/m_axis_rx_tdata[5]} {axis_mac0/m_axis_rx_tdata[6]} {axis_mac0/m_axis_rx_tdata[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
+set_property port_width 16 [get_debug_ports u_ila_0/probe16]
+connect_debug_port u_ila_0/probe16 [get_nets [list {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[0]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[1]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[2]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[3]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[4]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[5]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[6]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[7]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[8]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[9]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[10]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[11]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[12]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[13]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[14]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
+set_property port_width 12 [get_debug_ports u_ila_0/probe17]
+connect_debug_port u_ila_0/probe17 [get_nets [list {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[0]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[1]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[2]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[3]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[4]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[5]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[6]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[7]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[8]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[9]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[10]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[11]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
+set_property port_width 8 [get_debug_ports u_ila_0/probe18]
+connect_debug_port u_ila_0/probe18 [get_nets [list {axis_mac0/mac_top0/mac_tx0/ram_wr_data[0]} {axis_mac0/mac_top0/mac_tx0/ram_wr_data[1]} {axis_mac0/mac_top0/mac_tx0/ram_wr_data[2]} {axis_mac0/mac_top0/mac_tx0/ram_wr_data[3]} {axis_mac0/mac_top0/mac_tx0/ram_wr_data[4]} {axis_mac0/mac_top0/mac_tx0/ram_wr_data[5]} {axis_mac0/mac_top0/mac_tx0/ram_wr_data[6]} {axis_mac0/mac_top0/mac_tx0/ram_wr_data[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
+set_property port_width 8 [get_debug_ports u_ila_0/probe19]
+connect_debug_port u_ila_0/probe19 [get_nets [list {axis_mac0/mac_top0/mac_tx0/mac_tx_data[0]} {axis_mac0/mac_top0/mac_tx0/mac_tx_data[1]} {axis_mac0/mac_top0/mac_tx0/mac_tx_data[2]} {axis_mac0/mac_top0/mac_tx0/mac_tx_data[3]} {axis_mac0/mac_top0/mac_tx0/mac_tx_data[4]} {axis_mac0/mac_top0/mac_tx0/mac_tx_data[5]} {axis_mac0/mac_top0/mac_tx0/mac_tx_data[6]} {axis_mac0/mac_top0/mac_tx0/mac_tx_data[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
+set_property port_width 4 [get_debug_ports u_ila_0/probe20]
+connect_debug_port u_ila_0/probe20 [get_nets [list {axis_mac0/mac_top0/mac_tx0/udp0/usedw[0]} {axis_mac0/mac_top0/mac_tx0/udp0/usedw[1]} {axis_mac0/mac_top0/mac_tx0/udp0/usedw[2]} {axis_mac0/mac_top0/mac_tx0/udp0/usedw[3]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
+set_property port_width 6 [get_debug_ports u_ila_0/probe21]
+connect_debug_port u_ila_0/probe21 [get_nets [list {axis_mac0/mac_top0/mac_tx0/udp0/state[0]} {axis_mac0/mac_top0/mac_tx0/udp0/state[1]} {axis_mac0/mac_top0/mac_tx0/udp0/state[2]} {axis_mac0/mac_top0/mac_tx0/udp0/state[3]} {axis_mac0/mac_top0/mac_tx0/udp0/state[4]} {axis_mac0/mac_top0/mac_tx0/udp0/state[5]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
+set_property port_width 16 [get_debug_ports u_ila_0/probe22]
+connect_debug_port u_ila_0/probe22 [get_nets [list {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[0]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[1]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[2]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[3]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[4]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[5]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[6]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[7]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[8]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[9]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[10]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[11]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[12]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[13]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[14]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
+set_property port_width 11 [get_debug_ports u_ila_0/probe23]
+connect_debug_port u_ila_0/probe23 [get_nets [list {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[0]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[1]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[2]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[3]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[4]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[5]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[6]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[7]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[8]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[9]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[10]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
+set_property port_width 8 [get_debug_ports u_ila_0/probe24]
+connect_debug_port u_ila_0/probe24 [get_nets [list {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[0]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[1]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[2]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[3]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[4]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[5]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[6]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
+set_property port_width 16 [get_debug_ports u_ila_0/probe25]
+connect_debug_port u_ila_0/probe25 [get_nets [list {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[0]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[1]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[2]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[3]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[4]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[5]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[6]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[7]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[8]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[9]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[10]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[11]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[12]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[13]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[14]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
+set_property port_width 8 [get_debug_ports u_ila_0/probe26]
+connect_debug_port u_ila_0/probe26 [get_nets [list {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[0]} {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[1]} {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[2]} {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[3]} {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[4]} {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[5]} {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[6]} {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
+set_property port_width 16 [get_debug_ports u_ila_0/probe27]
+connect_debug_port u_ila_0/probe27 [get_nets [list {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[0]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[1]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[2]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[3]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[4]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[5]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[6]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[7]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[8]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[9]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[10]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[11]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[12]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[13]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[14]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
+set_property port_width 8 [get_debug_ports u_ila_0/probe28]
+connect_debug_port u_ila_0/probe28 [get_nets [list {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[0]} {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[1]} {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[2]} {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[3]} {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[4]} {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[5]} {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[6]} {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
+set_property port_width 11 [get_debug_ports u_ila_0/probe29]
+connect_debug_port u_ila_0/probe29 [get_nets [list {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[0]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[1]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[2]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[3]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[4]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[5]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[6]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[7]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[8]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[9]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[10]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
+set_property port_width 2 [get_debug_ports u_ila_0/probe30]
+connect_debug_port u_ila_0/probe30 [get_nets [list {test_state[0]} {test_state[1]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
+set_property port_width 1 [get_debug_ports u_ila_0/probe31]
+connect_debug_port u_ila_0/probe31 [get_nets [list axis_mac0/mac_top0/mac_tx0/almost_full]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
+set_property port_width 1 [get_debug_ports u_ila_0/probe32]
+connect_debug_port u_ila_0/probe32 [get_nets [list axis_mac0/arp_found]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
+set_property port_width 1 [get_debug_ports u_ila_0/probe33]
+connect_debug_port u_ila_0/probe33 [get_nets [list arbi_inst/rx_buffer_inst/e10_100_rx_dv]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
+set_property port_width 1 [get_debug_ports u_ila_0/probe34]
+connect_debug_port u_ila_0/probe34 [get_nets [list arbi_inst/e_rx_dv]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
+set_property port_width 1 [get_debug_ports u_ila_0/probe35]
+connect_debug_port u_ila_0/probe35 [get_nets [list arbi_inst/e_tx_en]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
+set_property port_width 1 [get_debug_ports u_ila_0/probe36]
+connect_debug_port u_ila_0/probe36 [get_nets [list arbi_inst/gmii_rx_dv]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
+set_property port_width 1 [get_debug_ports u_ila_0/probe37]
+connect_debug_port u_ila_0/probe37 [get_nets [list arbi_inst/rx_buffer_inst/gmii_rx_dv_d0]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
+set_property port_width 1 [get_debug_ports u_ila_0/probe38]
+connect_debug_port u_ila_0/probe38 [get_nets [list arbi_inst/rx_buffer_inst/gmii_rx_dv_d1]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39]
+set_property port_width 1 [get_debug_ports u_ila_0/probe39]
+connect_debug_port u_ila_0/probe39 [get_nets [list arbi_inst/gmii_tx_en]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40]
+set_property port_width 1 [get_debug_ports u_ila_0/probe40]
+connect_debug_port u_ila_0/probe40 [get_nets [list axis_mac0/m_axis_rx_tlast]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41]
+set_property port_width 1 [get_debug_ports u_ila_0/probe41]
+connect_debug_port u_ila_0/probe41 [get_nets [list axis_mac0/m_axis_rx_tready]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42]
+set_property port_width 1 [get_debug_ports u_ila_0/probe42]
+connect_debug_port u_ila_0/probe42 [get_nets [list axis_mac0/m_axis_rx_tvalid]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43]
+set_property port_width 1 [get_debug_ports u_ila_0/probe43]
+connect_debug_port u_ila_0/probe43 [get_nets [list axis_mac0/mac_top0/mac_tx0/mac_data_valid]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44]
+set_property port_width 1 [get_debug_ports u_ila_0/probe44]
+connect_debug_port u_ila_0/probe44 [get_nets [list axis_mac0/mac_top0/mac_tx0/mac_send_end]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45]
+set_property port_width 1 [get_debug_ports u_ila_0/probe45]
+connect_debug_port u_ila_0/probe45 [get_nets [list axis_mac0/mac_top0/mac_rx0/udp0/ram_wr_en]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46]
+set_property port_width 1 [get_debug_ports u_ila_0/probe46]
+connect_debug_port u_ila_0/probe46 [get_nets [list axis_mac0/mac_top0/mac_tx0/ram_wr_en]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47]
+set_property port_width 1 [get_debug_ports u_ila_0/probe47]
+connect_debug_port u_ila_0/probe47 [get_nets [list req_ready]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe48]
+set_property port_width 1 [get_debug_ports u_ila_0/probe48]
+connect_debug_port u_ila_0/probe48 [get_nets [list axis_mac0/req_ready]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe49]
+set_property port_width 1 [get_debug_ports u_ila_0/probe49]
+connect_debug_port u_ila_0/probe49 [get_nets [list axis_mac0/s_axis_tx_tlast]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe50]
+set_property port_width 1 [get_debug_ports u_ila_0/probe50]
+connect_debug_port u_ila_0/probe50 [get_nets [list axis_mac0/s_axis_tx_tready]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe51]
+set_property port_width 1 [get_debug_ports u_ila_0/probe51]
+connect_debug_port u_ila_0/probe51 [get_nets [list axis_mac0/s_axis_tx_tvalid]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe52]
+set_property port_width 1 [get_debug_ports u_ila_0/probe52]
+connect_debug_port u_ila_0/probe52 [get_nets [list axis_mac0/send_req]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe53]
+set_property port_width 1 [get_debug_ports u_ila_0/probe53]
+connect_debug_port u_ila_0/probe53 [get_nets [list send_req]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54]
+set_property port_width 1 [get_debug_ports u_ila_0/probe54]
+connect_debug_port u_ila_0/probe54 [get_nets [list arbi_inst/tx_buffer_inst/tx_rden]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe55]
+set_property port_width 1 [get_debug_ports u_ila_0/probe55]
+connect_debug_port u_ila_0/probe55 [get_nets [list arbi_inst/tx_buffer_inst/tx_wren]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe56]
+set_property port_width 1 [get_debug_ports u_ila_0/probe56]
+connect_debug_port u_ila_0/probe56 [get_nets [list axis_mac0/mac_top0/mac_tx0/udp_ram_data_req]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe57]
+set_property port_width 1 [get_debug_ports u_ila_0/probe57]
+connect_debug_port u_ila_0/probe57 [get_nets [list axis_mac0/mac_top0/mac_rx0/udp_rec_data_valid]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe58]
+set_property port_width 1 [get_debug_ports u_ila_0/probe58]
+connect_debug_port u_ila_0/probe58 [get_nets [list axis_mac0/mac_top0/mac_tx0/udp_tx_end]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe59]
+set_property port_width 1 [get_debug_ports u_ila_0/probe59]
+connect_debug_port u_ila_0/probe59 [get_nets [list axis_mac0/mac_top0/mac_tx0/udp_tx_req]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe60]
+set_property port_width 1 [get_debug_ports u_ila_0/probe60]
+connect_debug_port u_ila_0/probe60 [get_nets [list axis_mac0/mac_top0/mac_tx0/upper_data_req]]
+set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
+set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+connect_debug_port dbg_hub/clk [get_nets rgmii_rxc_IBUF_BUFG]

rtl/ethernet-udp/tests/eth_axis/ethernet_axis_echo.v

@@ -0,0 +1,344 @@
+// project with UDP ethernet echo
+// use axi streams from axis_mac
+// fpga IP: 192.168.0.2
+// host IP: 192.168.0.3
+
+`timescale 1 ns / 1 ns
+
+module ethernet_axis_echo
+(
+    input               sys_clk_p,
+    input               sys_clk_n,
+    input               rst_n,
+    output [3:0]        led,
+    output              e_reset,
+    output              e_mdc,
+    inout               e_mdio,
+    output [3:0]        rgmii_txd,
+    output              rgmii_txctl,
+    output              rgmii_txc,
+    input  [3:0]        rgmii_rxd,
+    input               rgmii_rxctl,
+    input               rgmii_rxc
+);
+
+    // ------------------------------------------------------------
+    // Internal GMII-side signals
+    // ------------------------------------------------------------
+    wire  [7:0] gmii_txd;
+    wire        gmii_tx_en;
+    wire        gmii_tx_er;
+    wire        gmii_tx_clk;
+    wire        gmii_crs;
+    wire        gmii_col;
+    wire  [7:0] gmii_rxd_i;
+    wire        gmii_rx_dv;
+    wire        gmii_rx_er;
+    wire        gmii_rx_clk;
+
+    wire [31:0] pack_total_len;
+
+    wire        e_rx_dv;
+    wire [7:0]  e_rxd;
+    wire        e_tx_en;
+    wire [7:0]  e_txd;
+    wire        e_rst_n;
+    wire        sys_clk;
+
+    wire        duplex_mode;
+
+    assign duplex_mode = 1'b1;
+
+    // ------------------------------------------------------------
+    // System clock buffer
+    // ------------------------------------------------------------
+    IBUFDS sys_clk_ibufgds
+    (
+        .O  (sys_clk),
+        .I  (sys_clk_p),
+        .IB (sys_clk_n)
+    );
+
+    // ------------------------------------------------------------
+    // IDELAYCTRL
+    // ------------------------------------------------------------
+    (* IODELAY_GROUP = "rgmii_idelay_group" *)
+    IDELAYCTRL IDELAYCTRL_inst (
+        .RDY(),
+        .REFCLK(sys_clk),
+        .RST(1'b0)
+    );
+
+    // ------------------------------------------------------------
+    // GMII <-> RGMII conversion
+    // ------------------------------------------------------------
+    util_gmii_to_rgmii util_gmii_to_rgmii_m0
+    (
+        .reset           (1'b0),
+        .rgmii_td        (rgmii_txd),
+        .rgmii_tx_ctl    (rgmii_txctl),
+        .rgmii_txc       (rgmii_txc),
+        .rgmii_rd        (rgmii_rxd),
+        .rgmii_rx_ctl    (rgmii_rxctl),
+        .gmii_rx_clk     (gmii_rx_clk),
+        .gmii_txd        (e_txd),
+        .gmii_tx_en      (e_tx_en),
+        .gmii_tx_er      (1'b0),
+        .gmii_tx_clk     (gmii_tx_clk),
+        .gmii_crs        (gmii_crs),
+        .gmii_col        (gmii_col),
+        .gmii_rxd        (gmii_rxd_i),
+        .rgmii_rxc       (rgmii_rxc),
+        .gmii_rx_dv      (gmii_rx_dv),
+        .gmii_rx_er      (gmii_rx_er),
+        .speed_selection (2'b10),
+        .duplex_mode     (duplex_mode)
+    );
+
+    // ------------------------------------------------------------
+    // GMII arbitration / adaptation
+    // ------------------------------------------------------------
+    gmii_arbi arbi_inst
+    (
+        .clk            (gmii_tx_clk),
+        .rst_n          (rst_n),
+        .speed          (2'b10),
+        .link           (1'b1),
+        .pack_total_len (pack_total_len),
+        .e_rst_n        (e_rst_n),
+        .gmii_rx_dv     (gmii_rx_dv),
+        .gmii_rxd       (gmii_rxd_i),
+        .gmii_tx_en     (gmii_tx_en),
+        .gmii_txd       (gmii_txd),
+        .e_rx_dv        (e_rx_dv),
+        .e_rxd          (e_rxd),
+        .e_tx_en        (e_tx_en),
+        .e_txd          (e_txd)
+    );
+
+    // ------------------------------------------------------------
+    // axis_mac interface
+    // ------------------------------------------------------------
+    (* MARK_DEBUG="true" *)wire        req_ready;
+
+    (* MARK_DEBUG="true" *)reg         send_req;
+    reg  [15:0] data_length;
+
+    reg  [7:0]  s_axis_tx_tdata;
+    reg         s_axis_tx_tvalid;
+    wire        s_axis_tx_tready;
+    reg         s_axis_tx_tlast;
+
+    wire [7:0]  m_axis_rx_tdata;
+    wire        m_axis_rx_tvalid;
+    reg         m_axis_rx_tready;
+    wire        m_axis_rx_tlast;
+
+    // ------------------------------------------------------------
+    // axis_mac
+    // ------------------------------------------------------------
+    axis_mac axis_mac0
+    (
+        .gmii_tx_clk       (gmii_tx_clk),
+        .gmii_rx_clk       (gmii_rx_clk),
+        .rst_n             (e_rst_n),
+
+        .gmii_rx_dv        (e_rx_dv),
+        .gmii_rxd          (e_rxd),
+        .gmii_tx_en        (gmii_tx_en),
+        .gmii_txd          (gmii_txd),
+
+        .send_req          (send_req),
+        .data_length       (data_length),
+        .req_ready         (req_ready),
+
+        .s_axis_tx_tdata   (s_axis_tx_tdata),
+        .s_axis_tx_tvalid  (s_axis_tx_tvalid),
+        .s_axis_tx_tready  (s_axis_tx_tready),
+        .s_axis_tx_tlast   (s_axis_tx_tlast),
+
+        .m_axis_rx_tdata   (m_axis_rx_tdata),
+        .m_axis_rx_tvalid  (m_axis_rx_tvalid),
+        .m_axis_rx_tready  (m_axis_rx_tready),
+        .m_axis_rx_tlast   (m_axis_rx_tlast)
+    );
+
+    // LEDs
+    assign led[0] = req_ready;
+    assign led[1] = !m_axis_rx_tvalid;
+    assign led[2] = !s_axis_tx_tvalid;
+    assign led[3] = e_rst_n;
+
+    // Minimal one-packet echo buffer
+    localparam BUFFER_SIZE = 256;
+    reg [7:0] pkt_mem [0:BUFFER_SIZE-1];
+
+    reg [15:0] rx_wr_ptr;
+    reg [15:0] rx_pkt_len;
+    reg        rx_pkt_pending;
+
+    // TX -> RX acknowledge toggle
+    reg tx_done_toggle;
+    reg tx_done_toggle_rx_d0, tx_done_toggle_rx_d1;
+    wire tx_done_pulse_rx;
+
+    assign tx_done_pulse_rx = tx_done_toggle_rx_d1 ^ tx_done_toggle_rx_d0;
+
+    always @(posedge gmii_rx_clk or negedge e_rst_n) begin
+        if (!e_rst_n) begin
+            tx_done_toggle_rx_d0 <= 1'b0;
+            tx_done_toggle_rx_d1 <= 1'b0;
+        end else begin
+            tx_done_toggle_rx_d0 <= tx_done_toggle;
+            tx_done_toggle_rx_d1 <= tx_done_toggle_rx_d0;
+        end
+    end
+
+    always @(posedge gmii_rx_clk or negedge e_rst_n) begin
+        if (!e_rst_n) begin
+            rx_wr_ptr        <= 16'd0;
+            rx_pkt_len       <= 16'd0;
+            rx_pkt_pending   <= 1'b0;
+            m_axis_rx_tready <= 1'b0;
+        end else begin
+            // pending lock
+            m_axis_rx_tready <= !rx_pkt_pending;
+
+            // tx free
+            if (tx_done_pulse_rx) begin
+                rx_pkt_pending <= 1'b0;
+                rx_wr_ptr      <= 16'd0;
+            end
+
+            if (m_axis_rx_tvalid && m_axis_rx_tready) begin
+                pkt_mem[rx_wr_ptr] <= m_axis_rx_tdata;
+
+                if (m_axis_rx_tlast) begin
+                    rx_pkt_len     <= rx_wr_ptr + 16'd1;
+                    rx_pkt_pending <= 1'b1;
+                end
+
+                rx_wr_ptr <= rx_wr_ptr + 16'd1;
+            end
+        end
+    end
+
+
+    // sync RX pendind to TX domain
+    reg rx_pkt_pending_tx_d0, rx_pkt_pending_tx_d1;
+
+    always @(posedge gmii_tx_clk or negedge e_rst_n) begin
+        if (!e_rst_n) begin
+            rx_pkt_pending_tx_d0 <= 1'b0;
+            rx_pkt_pending_tx_d1 <= 1'b0;
+        end else begin
+            rx_pkt_pending_tx_d0 <= rx_pkt_pending;
+            rx_pkt_pending_tx_d1 <= rx_pkt_pending_tx_d0;
+        end
+    end
+
+    wire rx_pkt_pending_tx = rx_pkt_pending_tx_d1;
+
+    // tx FSM
+    localparam TX_IDLE    = 2'd0;
+    localparam TX_REQ     = 2'd1;
+    localparam TX_STREAM  = 2'd2;
+    localparam TX_TIMEOUT = 2'd3;
+
+    // timeout counter
+    reg [3:0] timeout_cnt;
+
+    (* MARK_DEBUG="true" *) reg [1:0]  test_state;
+    reg        tx_busy;
+    reg [15:0] tx_pkt_len;
+    reg [15:0] tx_rd_ptr;
+
+    always @(posedge gmii_tx_clk or negedge e_rst_n) begin
+        if (!e_rst_n) begin
+            test_state       <= TX_IDLE;
+            tx_busy          <= 1'b0;
+            tx_pkt_len       <= 16'd0;
+            tx_rd_ptr        <= 16'd0;
+
+            send_req         <= 1'b0;
+            data_length      <= 16'd0;
+
+            s_axis_tx_tdata  <= 8'd0;
+            s_axis_tx_tvalid <= 1'b0;
+            s_axis_tx_tlast  <= 1'b0;
+
+            tx_done_toggle   <= 1'b0;
+            timeout_cnt      <= 4'b0;
+        end else begin
+            send_req <= 1'b0;
+
+            case (test_state)
+                TX_IDLE: begin
+                    s_axis_tx_tvalid <= 1'b0;
+                    s_axis_tx_tlast  <= 1'b0;
+                    tx_rd_ptr        <= 16'd0;
+                    tx_busy          <= 1'b0;
+                    timeout_cnt      <= 4'b0;
+
+                    // rx pending and ready to send
+                    if (rx_pkt_pending_tx && req_ready) begin
+                        tx_busy     <= 1'b1;
+                        tx_pkt_len  <= rx_pkt_len;   // length stable while rx_pkt_pending=1
+                        data_length <= rx_pkt_len;
+                        send_req    <= 1'b1;
+                        test_state    <= TX_REQ;
+                    end
+                end
+
+                TX_REQ: begin
+                    // await ready from axis slave
+                    if (s_axis_tx_tready) begin
+                        s_axis_tx_tdata  <= pkt_mem[0];
+                        s_axis_tx_tvalid <= 1'b1;
+                        s_axis_tx_tlast  <= (tx_pkt_len == 16'd1);
+                        tx_rd_ptr        <= 16'd0;
+                        test_state         <= TX_STREAM;
+                    end
+                end
+
+                TX_STREAM: begin
+                    // now ready to send stream
+                    if (s_axis_tx_tvalid && s_axis_tx_tready) begin
+                        if (tx_rd_ptr == tx_pkt_len - 16'd1) begin
+                            // lset
+                            s_axis_tx_tvalid <= 1'b0;
+                            s_axis_tx_tlast  <= 1'b0;
+                            tx_busy          <= 1'b0;
+                            tx_done_toggle   <= ~tx_done_toggle; 
+                            test_state         <= TX_TIMEOUT;
+                        end else begin
+                            tx_rd_ptr        <= tx_rd_ptr + 16'd1;
+                            s_axis_tx_tdata  <= pkt_mem[tx_rd_ptr + 16'd1];
+                            s_axis_tx_tlast  <= (tx_rd_ptr + 16'd1 == tx_pkt_len - 16'd1);
+                        end
+                    end
+                end
+
+                TX_TIMEOUT: begin
+                    // little timeout until signals syncs
+                    timeout_cnt <= timeout_cnt + 1;
+                    if (timeout_cnt == 4'b1111)
+                        test_state <= TX_IDLE;
+                end
+
+                default: begin
+                    test_state <= TX_IDLE;
+                end
+            endcase
+        end
+    end
+
+    // PHY reset generation
+    reset reset_m0
+    (
+        .clk   (sys_clk),
+        .key1  (rst_n),
+        .rst_n (e_reset)
+    );
+
+endmodule

rtl/ethernet-udp/tests/eth_axis/ethernet_axis_echo.xdc

@@ -0,0 +1,346 @@
+# constrains for minimal ethernet stack
+
+create_clock -period 5.000 [get_ports sys_clk_p]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_p]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_n]
+set_property PACKAGE_PIN R4 [get_ports sys_clk_p]
+set_property PACKAGE_PIN T4 [get_ports sys_clk_n]
+
+set_property PACKAGE_PIN F15 [get_ports rst_n]
+set_property IOSTANDARD LVCMOS33 [get_ports rst_n]
+
+set_property PACKAGE_PIN L13 [get_ports {led[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
+set_property PACKAGE_PIN M13 [get_ports {led[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
+set_property PACKAGE_PIN K14 [get_ports {led[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
+set_property PACKAGE_PIN K13 [get_ports {led[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
+#########################ethernet######################
+create_clock -period 8.000 [get_ports rgmii_rxc]
+set_property IOSTANDARD LVCMOS33 [get_ports {rgmii_rxd[*]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {rgmii_txd[*]}]
+set_property SLEW FAST [get_ports {rgmii_txd[*]}]
+
+set_property IOSTANDARD LVCMOS33 [get_ports e_mdc]
+set_property IOSTANDARD LVCMOS33 [get_ports e_mdio]
+set_property IOSTANDARD LVCMOS33 [get_ports e_reset]
+set_property IOSTANDARD LVCMOS33 [get_ports rgmii_rxc]
+set_property IOSTANDARD LVCMOS33 [get_ports rgmii_rxctl]
+set_property IOSTANDARD LVCMOS33 [get_ports rgmii_txc]
+set_property IOSTANDARD LVCMOS33 [get_ports rgmii_txctl]
+set_property SLEW FAST [get_ports rgmii_txc]
+set_property SLEW FAST [get_ports rgmii_txctl]
+
+set_property PACKAGE_PIN P17 [get_ports {rgmii_rxd[3]}]
+set_property PACKAGE_PIN U17 [get_ports {rgmii_rxd[2]}]
+set_property PACKAGE_PIN U18 [get_ports {rgmii_rxd[1]}]
+set_property PACKAGE_PIN P19 [get_ports {rgmii_rxd[0]}]
+set_property PACKAGE_PIN R16 [get_ports {rgmii_txd[3]}]
+set_property PACKAGE_PIN R17 [get_ports {rgmii_txd[2]}]
+set_property PACKAGE_PIN P16 [get_ports {rgmii_txd[1]}]
+set_property PACKAGE_PIN N14 [get_ports {rgmii_txd[0]}]
+set_property PACKAGE_PIN N13 [get_ports e_mdc]
+set_property PACKAGE_PIN P14 [get_ports e_mdio]
+set_property PACKAGE_PIN R14 [get_ports e_reset]
+set_property PACKAGE_PIN V18 [get_ports rgmii_rxc]
+set_property PACKAGE_PIN R19 [get_ports rgmii_rxctl]
+set_property PACKAGE_PIN P15 [get_ports rgmii_txc]
+set_property PACKAGE_PIN N17 [get_ports rgmii_txctl]
+
+
+
+
+connect_debug_port u_ila_0/clk [get_nets [list gmii_tx_clk_IBUF_BUFG]]
+connect_debug_port u_ila_0/probe0 [get_nets [list {dut/mac_top0/mac_tx0/mac_tx_data[0]} {dut/mac_top0/mac_tx0/mac_tx_data[1]} {dut/mac_top0/mac_tx0/mac_tx_data[2]} {dut/mac_top0/mac_tx0/mac_tx_data[3]} {dut/mac_top0/mac_tx0/mac_tx_data[4]} {dut/mac_top0/mac_tx0/mac_tx_data[5]} {dut/mac_top0/mac_tx0/mac_tx_data[6]} {dut/mac_top0/mac_tx0/mac_tx_data[7]}]]
+connect_debug_port u_ila_0/probe1 [get_nets [list {dut/mac_top0/mac_tx0/ram_wr_data[0]} {dut/mac_top0/mac_tx0/ram_wr_data[1]} {dut/mac_top0/mac_tx0/ram_wr_data[2]} {dut/mac_top0/mac_tx0/ram_wr_data[3]} {dut/mac_top0/mac_tx0/ram_wr_data[4]} {dut/mac_top0/mac_tx0/ram_wr_data[5]} {dut/mac_top0/mac_tx0/ram_wr_data[6]} {dut/mac_top0/mac_tx0/ram_wr_data[7]}]]
+connect_debug_port u_ila_0/probe2 [get_nets [list {dut/mac_top0/mac_tx0/udp0/usedw[0]} {dut/mac_top0/mac_tx0/udp0/usedw[1]} {dut/mac_top0/mac_tx0/udp0/usedw[2]} {dut/mac_top0/mac_tx0/udp0/usedw[3]}]]
+connect_debug_port u_ila_0/probe3 [get_nets [list {dut/mac_top0/mac_tx0/udp0/state[0]} {dut/mac_top0/mac_tx0/udp0/state[1]} {dut/mac_top0/mac_tx0/udp0/state[2]} {dut/mac_top0/mac_tx0/udp0/state[3]} {dut/mac_top0/mac_tx0/udp0/state[4]} {dut/mac_top0/mac_tx0/udp0/state[5]}]]
+connect_debug_port u_ila_0/probe4 [get_nets [list {dut/mac_top0/mac_tx0/udp_send_data_length[0]} {dut/mac_top0/mac_tx0/udp_send_data_length[1]} {dut/mac_top0/mac_tx0/udp_send_data_length[2]} {dut/mac_top0/mac_tx0/udp_send_data_length[3]} {dut/mac_top0/mac_tx0/udp_send_data_length[4]} {dut/mac_top0/mac_tx0/udp_send_data_length[5]} {dut/mac_top0/mac_tx0/udp_send_data_length[6]} {dut/mac_top0/mac_tx0/udp_send_data_length[7]} {dut/mac_top0/mac_tx0/udp_send_data_length[8]} {dut/mac_top0/mac_tx0/udp_send_data_length[9]} {dut/mac_top0/mac_tx0/udp_send_data_length[10]} {dut/mac_top0/mac_tx0/udp_send_data_length[11]} {dut/mac_top0/mac_tx0/udp_send_data_length[12]} {dut/mac_top0/mac_tx0/udp_send_data_length[13]} {dut/mac_top0/mac_tx0/udp_send_data_length[14]} {dut/mac_top0/mac_tx0/udp_send_data_length[15]}]]
+connect_debug_port u_ila_0/probe5 [get_nets [list {dut/mac_top0/mac_tx0/udp_ram_data_count[0]} {dut/mac_top0/mac_tx0/udp_ram_data_count[1]} {dut/mac_top0/mac_tx0/udp_ram_data_count[2]} {dut/mac_top0/mac_tx0/udp_ram_data_count[3]} {dut/mac_top0/mac_tx0/udp_ram_data_count[4]} {dut/mac_top0/mac_tx0/udp_ram_data_count[5]} {dut/mac_top0/mac_tx0/udp_ram_data_count[6]} {dut/mac_top0/mac_tx0/udp_ram_data_count[7]} {dut/mac_top0/mac_tx0/udp_ram_data_count[8]} {dut/mac_top0/mac_tx0/udp_ram_data_count[9]} {dut/mac_top0/mac_tx0/udp_ram_data_count[10]} {dut/mac_top0/mac_tx0/udp_ram_data_count[11]}]]
+connect_debug_port u_ila_0/probe6 [get_nets [list {dut/mac_top0/mac_tx0/udp0/ck_state[0]} {dut/mac_top0/mac_tx0/udp0/ck_state[1]} {dut/mac_top0/mac_tx0/udp0/ck_state[2]} {dut/mac_top0/mac_tx0/udp0/ck_state[3]} {dut/mac_top0/mac_tx0/udp0/ck_state[4]} {dut/mac_top0/mac_tx0/udp0/ck_state[5]}]]
+connect_debug_port u_ila_0/probe7 [get_nets [list dut/mac_top0/mac_tx0/almost_full]]
+connect_debug_port u_ila_0/probe8 [get_nets [list dut/mac_top0/mac_tx0/mac_data_valid]]
+connect_debug_port u_ila_0/probe9 [get_nets [list dut/mac_top0/mac_tx0/mac_send_end]]
+connect_debug_port u_ila_0/probe10 [get_nets [list dut/mac_top0/mac_tx0/ram_wr_en]]
+connect_debug_port u_ila_0/probe11 [get_nets [list dut/mac_top0/mac_tx0/udp_ram_data_req]]
+connect_debug_port u_ila_0/probe12 [get_nets [list dut/mac_top0/mac_tx0/udp_tx_end]]
+connect_debug_port u_ila_0/probe13 [get_nets [list dut/mac_top0/mac_tx0/udp_tx_req]]
+connect_debug_port u_ila_0/probe14 [get_nets [list dut/mac_top0/mac_tx0/upper_data_req]]
+connect_debug_port u_ila_1/clk [get_nets [list gmii_rx_clk_IBUF_BUFG]]
+connect_debug_port u_ila_1/probe0 [get_nets [list {dut/udp_rec_data_length[0]} {dut/udp_rec_data_length[1]} {dut/udp_rec_data_length[2]} {dut/udp_rec_data_length[3]} {dut/udp_rec_data_length[4]} {dut/udp_rec_data_length[5]} {dut/udp_rec_data_length[6]} {dut/udp_rec_data_length[7]} {dut/udp_rec_data_length[8]} {dut/udp_rec_data_length[9]} {dut/udp_rec_data_length[10]} {dut/udp_rec_data_length[11]} {dut/udp_rec_data_length[12]} {dut/udp_rec_data_length[13]} {dut/udp_rec_data_length[14]} {dut/udp_rec_data_length[15]}]]
+connect_debug_port u_ila_1/probe1 [get_nets [list {dut/rx_index[0]} {dut/rx_index[1]} {dut/rx_index[2]} {dut/rx_index[3]} {dut/rx_index[4]} {dut/rx_index[5]} {dut/rx_index[6]} {dut/rx_index[7]} {dut/rx_index[8]} {dut/rx_index[9]} {dut/rx_index[10]} {dut/rx_index[11]} {dut/rx_index[12]} {dut/rx_index[13]} {dut/rx_index[14]} {dut/rx_index[15]}]]
+connect_debug_port u_ila_1/probe2 [get_nets [list {dut/m_axis_rx_tdata[0]} {dut/m_axis_rx_tdata[1]} {dut/m_axis_rx_tdata[2]} {dut/m_axis_rx_tdata[3]} {dut/m_axis_rx_tdata[4]} {dut/m_axis_rx_tdata[5]} {dut/m_axis_rx_tdata[6]} {dut/m_axis_rx_tdata[7]}]]
+connect_debug_port u_ila_1/probe3 [get_nets [list {dut/rx_state[0]} {dut/rx_state[1]}]]
+connect_debug_port u_ila_1/probe4 [get_nets [list {dut/rx_payload_len[0]} {dut/rx_payload_len[1]} {dut/rx_payload_len[2]} {dut/rx_payload_len[3]} {dut/rx_payload_len[4]} {dut/rx_payload_len[5]} {dut/rx_payload_len[6]} {dut/rx_payload_len[7]} {dut/rx_payload_len[8]} {dut/rx_payload_len[9]} {dut/rx_payload_len[10]} {dut/rx_payload_len[11]} {dut/rx_payload_len[12]} {dut/rx_payload_len[13]} {dut/rx_payload_len[14]} {dut/rx_payload_len[15]}]]
+connect_debug_port u_ila_1/probe5 [get_nets [list {dut/mac_top0/mac_rx0/ip_total_data_length[0]} {dut/mac_top0/mac_rx0/ip_total_data_length[1]} {dut/mac_top0/mac_rx0/ip_total_data_length[2]} {dut/mac_top0/mac_rx0/ip_total_data_length[3]} {dut/mac_top0/mac_rx0/ip_total_data_length[4]} {dut/mac_top0/mac_rx0/ip_total_data_length[5]} {dut/mac_top0/mac_rx0/ip_total_data_length[6]} {dut/mac_top0/mac_rx0/ip_total_data_length[7]} {dut/mac_top0/mac_rx0/ip_total_data_length[8]} {dut/mac_top0/mac_rx0/ip_total_data_length[9]} {dut/mac_top0/mac_rx0/ip_total_data_length[10]} {dut/mac_top0/mac_rx0/ip_total_data_length[11]} {dut/mac_top0/mac_rx0/ip_total_data_length[12]} {dut/mac_top0/mac_rx0/ip_total_data_length[13]} {dut/mac_top0/mac_rx0/ip_total_data_length[14]} {dut/mac_top0/mac_rx0/ip_total_data_length[15]}]]
+connect_debug_port u_ila_1/probe6 [get_nets [list {dut/mac_top0/mac_rx0/upper_layer_data_length[0]} {dut/mac_top0/mac_rx0/upper_layer_data_length[1]} {dut/mac_top0/mac_rx0/upper_layer_data_length[2]} {dut/mac_top0/mac_rx0/upper_layer_data_length[3]} {dut/mac_top0/mac_rx0/upper_layer_data_length[4]} {dut/mac_top0/mac_rx0/upper_layer_data_length[5]} {dut/mac_top0/mac_rx0/upper_layer_data_length[6]} {dut/mac_top0/mac_rx0/upper_layer_data_length[7]} {dut/mac_top0/mac_rx0/upper_layer_data_length[8]} {dut/mac_top0/mac_rx0/upper_layer_data_length[9]} {dut/mac_top0/mac_rx0/upper_layer_data_length[10]} {dut/mac_top0/mac_rx0/upper_layer_data_length[11]} {dut/mac_top0/mac_rx0/upper_layer_data_length[12]} {dut/mac_top0/mac_rx0/upper_layer_data_length[13]} {dut/mac_top0/mac_rx0/upper_layer_data_length[14]} {dut/mac_top0/mac_rx0/upper_layer_data_length[15]}]]
+connect_debug_port u_ila_1/probe7 [get_nets [list {dut/mac_top0/mac_rx0/udp_rec_ram_read_addr[0]} {dut/mac_top0/mac_rx0/udp_rec_ram_read_addr[1]} {dut/mac_top0/mac_rx0/udp_rec_ram_read_addr[2]} {dut/mac_top0/mac_rx0/udp_rec_ram_read_addr[3]} {dut/mac_top0/mac_rx0/udp_rec_ram_read_addr[4]} {dut/mac_top0/mac_rx0/udp_rec_ram_read_addr[5]} {dut/mac_top0/mac_rx0/udp_rec_ram_read_addr[6]} {dut/mac_top0/mac_rx0/udp_rec_ram_read_addr[7]} {dut/mac_top0/mac_rx0/udp_rec_ram_read_addr[8]} {dut/mac_top0/mac_rx0/udp_rec_ram_read_addr[9]} {dut/mac_top0/mac_rx0/udp_rec_ram_read_addr[10]}]]
+connect_debug_port u_ila_1/probe8 [get_nets [list {dut/mac_top0/mac_rx0/mac_rx_datain[0]} {dut/mac_top0/mac_rx0/mac_rx_datain[1]} {dut/mac_top0/mac_rx0/mac_rx_datain[2]} {dut/mac_top0/mac_rx0/mac_rx_datain[3]} {dut/mac_top0/mac_rx0/mac_rx_datain[4]} {dut/mac_top0/mac_rx0/mac_rx_datain[5]} {dut/mac_top0/mac_rx0/mac_rx_datain[6]} {dut/mac_top0/mac_rx0/mac_rx_datain[7]}]]
+connect_debug_port u_ila_1/probe9 [get_nets [list {dut/mac_top0/mac_rx0/udp_rec_ram_rdata[0]} {dut/mac_top0/mac_rx0/udp_rec_ram_rdata[1]} {dut/mac_top0/mac_rx0/udp_rec_ram_rdata[2]} {dut/mac_top0/mac_rx0/udp_rec_ram_rdata[3]} {dut/mac_top0/mac_rx0/udp_rec_ram_rdata[4]} {dut/mac_top0/mac_rx0/udp_rec_ram_rdata[5]} {dut/mac_top0/mac_rx0/udp_rec_ram_rdata[6]} {dut/mac_top0/mac_rx0/udp_rec_ram_rdata[7]}]]
+connect_debug_port u_ila_1/probe10 [get_nets [list {dut/mac_top0/mac_rx0/mac_rx_dataout[0]} {dut/mac_top0/mac_rx0/mac_rx_dataout[1]} {dut/mac_top0/mac_rx0/mac_rx_dataout[2]} {dut/mac_top0/mac_rx0/mac_rx_dataout[3]} {dut/mac_top0/mac_rx0/mac_rx_dataout[4]} {dut/mac_top0/mac_rx0/mac_rx_dataout[5]} {dut/mac_top0/mac_rx0/mac_rx_dataout[6]} {dut/mac_top0/mac_rx0/mac_rx_dataout[7]}]]
+connect_debug_port u_ila_1/probe11 [get_nets [list {dut/mac_top0/mac_rx0/udp_rec_data_length[0]} {dut/mac_top0/mac_rx0/udp_rec_data_length[1]} {dut/mac_top0/mac_rx0/udp_rec_data_length[2]} {dut/mac_top0/mac_rx0/udp_rec_data_length[3]} {dut/mac_top0/mac_rx0/udp_rec_data_length[4]} {dut/mac_top0/mac_rx0/udp_rec_data_length[5]} {dut/mac_top0/mac_rx0/udp_rec_data_length[6]} {dut/mac_top0/mac_rx0/udp_rec_data_length[7]} {dut/mac_top0/mac_rx0/udp_rec_data_length[8]} {dut/mac_top0/mac_rx0/udp_rec_data_length[9]} {dut/mac_top0/mac_rx0/udp_rec_data_length[10]} {dut/mac_top0/mac_rx0/udp_rec_data_length[11]} {dut/mac_top0/mac_rx0/udp_rec_data_length[12]} {dut/mac_top0/mac_rx0/udp_rec_data_length[13]} {dut/mac_top0/mac_rx0/udp_rec_data_length[14]} {dut/mac_top0/mac_rx0/udp_rec_data_length[15]}]]
+connect_debug_port u_ila_1/probe12 [get_nets [list {dut/mac_top0/mac_rx0/udp0/ram_write_addr[0]} {dut/mac_top0/mac_rx0/udp0/ram_write_addr[1]} {dut/mac_top0/mac_rx0/udp0/ram_write_addr[2]} {dut/mac_top0/mac_rx0/udp0/ram_write_addr[3]} {dut/mac_top0/mac_rx0/udp0/ram_write_addr[4]} {dut/mac_top0/mac_rx0/udp0/ram_write_addr[5]} {dut/mac_top0/mac_rx0/udp0/ram_write_addr[6]} {dut/mac_top0/mac_rx0/udp0/ram_write_addr[7]} {dut/mac_top0/mac_rx0/udp0/ram_write_addr[8]} {dut/mac_top0/mac_rx0/udp0/ram_write_addr[9]} {dut/mac_top0/mac_rx0/udp0/ram_write_addr[10]}]]
+connect_debug_port u_ila_1/probe13 [get_nets [list dut/m_axis_rx_tlast]]
+connect_debug_port u_ila_1/probe14 [get_nets [list dut/m_axis_rx_tvalid]]
+connect_debug_port u_ila_1/probe15 [get_nets [list dut/mac_top0/mac_rx0/udp0/ram_wr_en]]
+connect_debug_port u_ila_1/probe16 [get_nets [list dut/mac_top0/mac_rx0/udp_rec_data_valid]]
+connect_debug_port dbg_hub/clk [get_nets gmii_rx_clk_IBUF_BUFG]
+
+
+
+connect_debug_port u_ila_0/probe4 [get_nets [list {tx_state[0]} {tx_state[1]}]]
+
+connect_debug_port u_ila_0/probe48 [get_nets [list rx_pkt_pulse_tx]]
+
+create_debug_core u_ila_0 ila
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
+set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
+set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
+set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
+set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
+set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
+set_property port_width 1 [get_debug_ports u_ila_0/clk]
+connect_debug_port u_ila_0/clk [get_nets [list rgmii_rxc_IBUF_BUFG]]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
+set_property port_width 8 [get_debug_ports u_ila_0/probe0]
+connect_debug_port u_ila_0/probe0 [get_nets [list {axis_mac0/mac_top0/mac_tx0/ram_wr_data[0]} {axis_mac0/mac_top0/mac_tx0/ram_wr_data[1]} {axis_mac0/mac_top0/mac_tx0/ram_wr_data[2]} {axis_mac0/mac_top0/mac_tx0/ram_wr_data[3]} {axis_mac0/mac_top0/mac_tx0/ram_wr_data[4]} {axis_mac0/mac_top0/mac_tx0/ram_wr_data[5]} {axis_mac0/mac_top0/mac_tx0/ram_wr_data[6]} {axis_mac0/mac_top0/mac_tx0/ram_wr_data[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
+set_property port_width 8 [get_debug_ports u_ila_0/probe1]
+connect_debug_port u_ila_0/probe1 [get_nets [list {axis_mac0/mac_top0/mac_tx0/mac_tx_data[0]} {axis_mac0/mac_top0/mac_tx0/mac_tx_data[1]} {axis_mac0/mac_top0/mac_tx0/mac_tx_data[2]} {axis_mac0/mac_top0/mac_tx0/mac_tx_data[3]} {axis_mac0/mac_top0/mac_tx0/mac_tx_data[4]} {axis_mac0/mac_top0/mac_tx0/mac_tx_data[5]} {axis_mac0/mac_top0/mac_tx0/mac_tx_data[6]} {axis_mac0/mac_top0/mac_tx0/mac_tx_data[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
+set_property port_width 16 [get_debug_ports u_ila_0/probe2]
+connect_debug_port u_ila_0/probe2 [get_nets [list {axis_mac0/rx_payload_len[0]} {axis_mac0/rx_payload_len[1]} {axis_mac0/rx_payload_len[2]} {axis_mac0/rx_payload_len[3]} {axis_mac0/rx_payload_len[4]} {axis_mac0/rx_payload_len[5]} {axis_mac0/rx_payload_len[6]} {axis_mac0/rx_payload_len[7]} {axis_mac0/rx_payload_len[8]} {axis_mac0/rx_payload_len[9]} {axis_mac0/rx_payload_len[10]} {axis_mac0/rx_payload_len[11]} {axis_mac0/rx_payload_len[12]} {axis_mac0/rx_payload_len[13]} {axis_mac0/rx_payload_len[14]} {axis_mac0/rx_payload_len[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
+set_property port_width 16 [get_debug_ports u_ila_0/probe3]
+connect_debug_port u_ila_0/probe3 [get_nets [list {axis_mac0/rx_index[0]} {axis_mac0/rx_index[1]} {axis_mac0/rx_index[2]} {axis_mac0/rx_index[3]} {axis_mac0/rx_index[4]} {axis_mac0/rx_index[5]} {axis_mac0/rx_index[6]} {axis_mac0/rx_index[7]} {axis_mac0/rx_index[8]} {axis_mac0/rx_index[9]} {axis_mac0/rx_index[10]} {axis_mac0/rx_index[11]} {axis_mac0/rx_index[12]} {axis_mac0/rx_index[13]} {axis_mac0/rx_index[14]} {axis_mac0/rx_index[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
+set_property port_width 16 [get_debug_ports u_ila_0/probe4]
+connect_debug_port u_ila_0/probe4 [get_nets [list {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[0]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[1]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[2]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[3]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[4]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[5]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[6]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[7]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[8]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[9]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[10]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[11]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[12]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[13]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[14]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
+set_property port_width 12 [get_debug_ports u_ila_0/probe5]
+connect_debug_port u_ila_0/probe5 [get_nets [list {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[0]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[1]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[2]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[3]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[4]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[5]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[6]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[7]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[8]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[9]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[10]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[11]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
+set_property port_width 11 [get_debug_ports u_ila_0/probe6]
+connect_debug_port u_ila_0/probe6 [get_nets [list {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[0]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[1]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[2]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[3]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[4]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[5]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[6]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[7]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[8]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[9]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[10]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
+set_property port_width 8 [get_debug_ports u_ila_0/probe7]
+connect_debug_port u_ila_0/probe7 [get_nets [list {arbi_inst/e_txd[0]} {arbi_inst/e_txd[1]} {arbi_inst/e_txd[2]} {arbi_inst/e_txd[3]} {arbi_inst/e_txd[4]} {arbi_inst/e_txd[5]} {arbi_inst/e_txd[6]} {arbi_inst/e_txd[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
+set_property port_width 8 [get_debug_ports u_ila_0/probe8]
+connect_debug_port u_ila_0/probe8 [get_nets [list {arbi_inst/tx_buffer_inst/tx_rdata[0]} {arbi_inst/tx_buffer_inst/tx_rdata[1]} {arbi_inst/tx_buffer_inst/tx_rdata[2]} {arbi_inst/tx_buffer_inst/tx_rdata[3]} {arbi_inst/tx_buffer_inst/tx_rdata[4]} {arbi_inst/tx_buffer_inst/tx_rdata[5]} {arbi_inst/tx_buffer_inst/tx_rdata[6]} {arbi_inst/tx_buffer_inst/tx_rdata[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
+set_property port_width 16 [get_debug_ports u_ila_0/probe9]
+connect_debug_port u_ila_0/probe9 [get_nets [list {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[0]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[1]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[2]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[3]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[4]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[5]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[6]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[7]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[8]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[9]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[10]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[11]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[12]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[13]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[14]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
+set_property port_width 8 [get_debug_ports u_ila_0/probe10]
+connect_debug_port u_ila_0/probe10 [get_nets [list {axis_mac0/m_axis_rx_tdata[0]} {axis_mac0/m_axis_rx_tdata[1]} {axis_mac0/m_axis_rx_tdata[2]} {axis_mac0/m_axis_rx_tdata[3]} {axis_mac0/m_axis_rx_tdata[4]} {axis_mac0/m_axis_rx_tdata[5]} {axis_mac0/m_axis_rx_tdata[6]} {axis_mac0/m_axis_rx_tdata[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
+set_property port_width 8 [get_debug_ports u_ila_0/probe11]
+connect_debug_port u_ila_0/probe11 [get_nets [list {arbi_inst/rx_buffer_inst/e10_100_rxd[0]} {arbi_inst/rx_buffer_inst/e10_100_rxd[1]} {arbi_inst/rx_buffer_inst/e10_100_rxd[2]} {arbi_inst/rx_buffer_inst/e10_100_rxd[3]} {arbi_inst/rx_buffer_inst/e10_100_rxd[4]} {arbi_inst/rx_buffer_inst/e10_100_rxd[5]} {arbi_inst/rx_buffer_inst/e10_100_rxd[6]} {arbi_inst/rx_buffer_inst/e10_100_rxd[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
+set_property port_width 8 [get_debug_ports u_ila_0/probe12]
+connect_debug_port u_ila_0/probe12 [get_nets [list {axis_mac0/s_axis_tx_tdata[0]} {axis_mac0/s_axis_tx_tdata[1]} {axis_mac0/s_axis_tx_tdata[2]} {axis_mac0/s_axis_tx_tdata[3]} {axis_mac0/s_axis_tx_tdata[4]} {axis_mac0/s_axis_tx_tdata[5]} {axis_mac0/s_axis_tx_tdata[6]} {axis_mac0/s_axis_tx_tdata[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
+set_property port_width 11 [get_debug_ports u_ila_0/probe13]
+connect_debug_port u_ila_0/probe13 [get_nets [list {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[0]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[1]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[2]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[3]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[4]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[5]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[6]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[7]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[8]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[9]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[10]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
+set_property port_width 8 [get_debug_ports u_ila_0/probe14]
+connect_debug_port u_ila_0/probe14 [get_nets [list {arbi_inst/e_rxd[0]} {arbi_inst/e_rxd[1]} {arbi_inst/e_rxd[2]} {arbi_inst/e_rxd[3]} {arbi_inst/e_rxd[4]} {arbi_inst/e_rxd[5]} {arbi_inst/e_rxd[6]} {arbi_inst/e_rxd[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
+set_property port_width 8 [get_debug_ports u_ila_0/probe15]
+connect_debug_port u_ila_0/probe15 [get_nets [list {arbi_inst/gmii_txd[0]} {arbi_inst/gmii_txd[1]} {arbi_inst/gmii_txd[2]} {arbi_inst/gmii_txd[3]} {arbi_inst/gmii_txd[4]} {arbi_inst/gmii_txd[5]} {arbi_inst/gmii_txd[6]} {arbi_inst/gmii_txd[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
+set_property port_width 16 [get_debug_ports u_ila_0/probe16]
+connect_debug_port u_ila_0/probe16 [get_nets [list {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[0]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[1]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[2]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[3]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[4]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[5]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[6]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[7]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[8]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[9]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[10]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[11]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[12]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[13]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[14]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
+set_property port_width 2 [get_debug_ports u_ila_0/probe17]
+connect_debug_port u_ila_0/probe17 [get_nets [list {test_state[0]} {test_state[1]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
+set_property port_width 8 [get_debug_ports u_ila_0/probe18]
+connect_debug_port u_ila_0/probe18 [get_nets [list {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[0]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[1]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[2]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[3]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[4]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[5]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[6]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
+set_property port_width 6 [get_debug_ports u_ila_0/probe19]
+connect_debug_port u_ila_0/probe19 [get_nets [list {axis_mac0/mac_top0/mac_tx0/udp0/state[0]} {axis_mac0/mac_top0/mac_tx0/udp0/state[1]} {axis_mac0/mac_top0/mac_tx0/udp0/state[2]} {axis_mac0/mac_top0/mac_tx0/udp0/state[3]} {axis_mac0/mac_top0/mac_tx0/udp0/state[4]} {axis_mac0/mac_top0/mac_tx0/udp0/state[5]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
+set_property port_width 8 [get_debug_ports u_ila_0/probe20]
+connect_debug_port u_ila_0/probe20 [get_nets [list {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[0]} {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[1]} {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[2]} {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[3]} {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[4]} {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[5]} {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[6]} {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
+set_property port_width 16 [get_debug_ports u_ila_0/probe21]
+connect_debug_port u_ila_0/probe21 [get_nets [list {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[0]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[1]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[2]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[3]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[4]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[5]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[6]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[7]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[8]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[9]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[10]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[11]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[12]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[13]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[14]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
+set_property port_width 4 [get_debug_ports u_ila_0/probe22]
+connect_debug_port u_ila_0/probe22 [get_nets [list {axis_mac0/mac_top0/mac_tx0/udp0/usedw[0]} {axis_mac0/mac_top0/mac_tx0/udp0/usedw[1]} {axis_mac0/mac_top0/mac_tx0/udp0/usedw[2]} {axis_mac0/mac_top0/mac_tx0/udp0/usedw[3]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
+set_property port_width 6 [get_debug_ports u_ila_0/probe23]
+connect_debug_port u_ila_0/probe23 [get_nets [list {axis_mac0/mac_top0/mac_tx0/udp0/ck_state[0]} {axis_mac0/mac_top0/mac_tx0/udp0/ck_state[1]} {axis_mac0/mac_top0/mac_tx0/udp0/ck_state[2]} {axis_mac0/mac_top0/mac_tx0/udp0/ck_state[3]} {axis_mac0/mac_top0/mac_tx0/udp0/ck_state[4]} {axis_mac0/mac_top0/mac_tx0/udp0/ck_state[5]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
+set_property port_width 8 [get_debug_ports u_ila_0/probe24]
+connect_debug_port u_ila_0/probe24 [get_nets [list {arbi_inst/gmii_rxd[0]} {arbi_inst/gmii_rxd[1]} {arbi_inst/gmii_rxd[2]} {arbi_inst/gmii_rxd[3]} {arbi_inst/gmii_rxd[4]} {arbi_inst/gmii_rxd[5]} {arbi_inst/gmii_rxd[6]} {arbi_inst/gmii_rxd[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
+set_property port_width 2 [get_debug_ports u_ila_0/probe25]
+connect_debug_port u_ila_0/probe25 [get_nets [list {axis_mac0/rx_state[0]} {axis_mac0/rx_state[1]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
+set_property port_width 8 [get_debug_ports u_ila_0/probe26]
+connect_debug_port u_ila_0/probe26 [get_nets [list {arbi_inst/tx_buffer_inst/tx_wdata[0]} {arbi_inst/tx_buffer_inst/tx_wdata[1]} {arbi_inst/tx_buffer_inst/tx_wdata[2]} {arbi_inst/tx_buffer_inst/tx_wdata[3]} {arbi_inst/tx_buffer_inst/tx_wdata[4]} {arbi_inst/tx_buffer_inst/tx_wdata[5]} {arbi_inst/tx_buffer_inst/tx_wdata[6]} {arbi_inst/tx_buffer_inst/tx_wdata[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
+set_property port_width 8 [get_debug_ports u_ila_0/probe27]
+connect_debug_port u_ila_0/probe27 [get_nets [list {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[0]} {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[1]} {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[2]} {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[3]} {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[4]} {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[5]} {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[6]} {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
+set_property port_width 3 [get_debug_ports u_ila_0/probe28]
+connect_debug_port u_ila_0/probe28 [get_nets [list {axis_mac0/tx_state[0]} {axis_mac0/tx_state[1]} {axis_mac0/tx_state[2]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
+set_property port_width 16 [get_debug_ports u_ila_0/probe29]
+connect_debug_port u_ila_0/probe29 [get_nets [list {arbi_inst/tx_buffer_inst/tx_data_cnt[0]} {arbi_inst/tx_buffer_inst/tx_data_cnt[1]} {arbi_inst/tx_buffer_inst/tx_data_cnt[2]} {arbi_inst/tx_buffer_inst/tx_data_cnt[3]} {arbi_inst/tx_buffer_inst/tx_data_cnt[4]} {arbi_inst/tx_buffer_inst/tx_data_cnt[5]} {arbi_inst/tx_buffer_inst/tx_data_cnt[6]} {arbi_inst/tx_buffer_inst/tx_data_cnt[7]} {arbi_inst/tx_buffer_inst/tx_data_cnt[8]} {arbi_inst/tx_buffer_inst/tx_data_cnt[9]} {arbi_inst/tx_buffer_inst/tx_data_cnt[10]} {arbi_inst/tx_buffer_inst/tx_data_cnt[11]} {arbi_inst/tx_buffer_inst/tx_data_cnt[12]} {arbi_inst/tx_buffer_inst/tx_data_cnt[13]} {arbi_inst/tx_buffer_inst/tx_data_cnt[14]} {arbi_inst/tx_buffer_inst/tx_data_cnt[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
+set_property port_width 16 [get_debug_ports u_ila_0/probe30]
+connect_debug_port u_ila_0/probe30 [get_nets [list {axis_mac0/udp_rec_data_length[0]} {axis_mac0/udp_rec_data_length[1]} {axis_mac0/udp_rec_data_length[2]} {axis_mac0/udp_rec_data_length[3]} {axis_mac0/udp_rec_data_length[4]} {axis_mac0/udp_rec_data_length[5]} {axis_mac0/udp_rec_data_length[6]} {axis_mac0/udp_rec_data_length[7]} {axis_mac0/udp_rec_data_length[8]} {axis_mac0/udp_rec_data_length[9]} {axis_mac0/udp_rec_data_length[10]} {axis_mac0/udp_rec_data_length[11]} {axis_mac0/udp_rec_data_length[12]} {axis_mac0/udp_rec_data_length[13]} {axis_mac0/udp_rec_data_length[14]} {axis_mac0/udp_rec_data_length[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
+set_property port_width 1 [get_debug_ports u_ila_0/probe31]
+connect_debug_port u_ila_0/probe31 [get_nets [list axis_mac0/mac_top0/mac_tx0/almost_full]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
+set_property port_width 1 [get_debug_ports u_ila_0/probe32]
+connect_debug_port u_ila_0/probe32 [get_nets [list axis_mac0/arp_found]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
+set_property port_width 1 [get_debug_ports u_ila_0/probe33]
+connect_debug_port u_ila_0/probe33 [get_nets [list arbi_inst/rx_buffer_inst/e10_100_rx_dv]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
+set_property port_width 1 [get_debug_ports u_ila_0/probe34]
+connect_debug_port u_ila_0/probe34 [get_nets [list arbi_inst/e_rx_dv]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
+set_property port_width 1 [get_debug_ports u_ila_0/probe35]
+connect_debug_port u_ila_0/probe35 [get_nets [list arbi_inst/e_tx_en]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
+set_property port_width 1 [get_debug_ports u_ila_0/probe36]
+connect_debug_port u_ila_0/probe36 [get_nets [list arbi_inst/gmii_rx_dv]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
+set_property port_width 1 [get_debug_ports u_ila_0/probe37]
+connect_debug_port u_ila_0/probe37 [get_nets [list arbi_inst/rx_buffer_inst/gmii_rx_dv_d0]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
+set_property port_width 1 [get_debug_ports u_ila_0/probe38]
+connect_debug_port u_ila_0/probe38 [get_nets [list arbi_inst/rx_buffer_inst/gmii_rx_dv_d1]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39]
+set_property port_width 1 [get_debug_ports u_ila_0/probe39]
+connect_debug_port u_ila_0/probe39 [get_nets [list arbi_inst/gmii_tx_en]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40]
+set_property port_width 1 [get_debug_ports u_ila_0/probe40]
+connect_debug_port u_ila_0/probe40 [get_nets [list axis_mac0/m_axis_rx_tlast]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41]
+set_property port_width 1 [get_debug_ports u_ila_0/probe41]
+connect_debug_port u_ila_0/probe41 [get_nets [list axis_mac0/m_axis_rx_tready]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42]
+set_property port_width 1 [get_debug_ports u_ila_0/probe42]
+connect_debug_port u_ila_0/probe42 [get_nets [list axis_mac0/m_axis_rx_tvalid]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43]
+set_property port_width 1 [get_debug_ports u_ila_0/probe43]
+connect_debug_port u_ila_0/probe43 [get_nets [list axis_mac0/mac_top0/mac_tx0/mac_data_valid]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44]
+set_property port_width 1 [get_debug_ports u_ila_0/probe44]
+connect_debug_port u_ila_0/probe44 [get_nets [list axis_mac0/mac_top0/mac_tx0/mac_send_end]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45]
+set_property port_width 1 [get_debug_ports u_ila_0/probe45]
+connect_debug_port u_ila_0/probe45 [get_nets [list axis_mac0/mac_top0/mac_tx0/ram_wr_en]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46]
+set_property port_width 1 [get_debug_ports u_ila_0/probe46]
+connect_debug_port u_ila_0/probe46 [get_nets [list axis_mac0/mac_top0/mac_rx0/udp0/ram_wr_en]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47]
+set_property port_width 1 [get_debug_ports u_ila_0/probe47]
+connect_debug_port u_ila_0/probe47 [get_nets [list req_ready]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe48]
+set_property port_width 1 [get_debug_ports u_ila_0/probe48]
+connect_debug_port u_ila_0/probe48 [get_nets [list axis_mac0/s_axis_tx_tlast]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe49]
+set_property port_width 1 [get_debug_ports u_ila_0/probe49]
+connect_debug_port u_ila_0/probe49 [get_nets [list axis_mac0/s_axis_tx_tready]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe50]
+set_property port_width 1 [get_debug_ports u_ila_0/probe50]
+connect_debug_port u_ila_0/probe50 [get_nets [list axis_mac0/s_axis_tx_tvalid]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe51]
+set_property port_width 1 [get_debug_ports u_ila_0/probe51]
+connect_debug_port u_ila_0/probe51 [get_nets [list send_req]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe52]
+set_property port_width 1 [get_debug_ports u_ila_0/probe52]
+connect_debug_port u_ila_0/probe52 [get_nets [list arbi_inst/tx_buffer_inst/tx_rden]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe53]
+set_property port_width 1 [get_debug_ports u_ila_0/probe53]
+connect_debug_port u_ila_0/probe53 [get_nets [list arbi_inst/tx_buffer_inst/tx_wren]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54]
+set_property port_width 1 [get_debug_ports u_ila_0/probe54]
+connect_debug_port u_ila_0/probe54 [get_nets [list axis_mac0/mac_top0/mac_tx0/udp_ram_data_req]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe55]
+set_property port_width 1 [get_debug_ports u_ila_0/probe55]
+connect_debug_port u_ila_0/probe55 [get_nets [list axis_mac0/mac_top0/mac_rx0/udp_rec_data_valid]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe56]
+set_property port_width 1 [get_debug_ports u_ila_0/probe56]
+connect_debug_port u_ila_0/probe56 [get_nets [list axis_mac0/mac_top0/mac_tx0/udp_tx_end]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe57]
+set_property port_width 1 [get_debug_ports u_ila_0/probe57]
+connect_debug_port u_ila_0/probe57 [get_nets [list axis_mac0/mac_top0/mac_tx0/udp_tx_req]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe58]
+set_property port_width 1 [get_debug_ports u_ila_0/probe58]
+connect_debug_port u_ila_0/probe58 [get_nets [list axis_mac0/mac_top0/mac_tx0/upper_data_req]]
+set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
+set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+connect_debug_port dbg_hub/clk [get_nets rgmii_rxc_IBUF_BUFG]

rtl/ethernet-udp/tests/eth_axis/test_axis_mac_rx.sv

@@ -0,0 +1,259 @@
+`timescale 1ns / 1ps
+
+module tb_mac_test;
+
+    reg         rst_n = 1'b0;
+    reg         gmii_rx_clk = 1'b0;
+    reg         gmii_tx_clk = 1'b0;
+    reg         gmii_rx_dv = 1'b0;
+    reg  [7:0]  gmii_rxd = 8'h00;
+
+    wire        gmii_tx_en;
+    wire [7:0]  gmii_txd;
+
+    // rx axis
+    wire [7:0]  m_axis_rx_tdata;
+    wire        m_axis_rx_tvalid;
+    reg         m_axis_rx_tready = 1'b0;
+    wire        m_axis_rx_tlast;
+
+    // tx axis
+    reg  [7:0]  s_axis_tx_tdata;
+    reg         s_axis_tx_tvalid;
+    wire        s_axis_tx_tready = 1'b0;
+    reg         s_axis_tx_tlast;
+
+    reg send_req;
+    wire req_ready;
+
+    reg [15:0] udp_rec_data_length;
+    
+    int cnt = 0;
+
+
+    // DUT
+    axis_mac dut (
+        .rst_n(rst_n),
+        .gmii_tx_clk(gmii_tx_clk),
+        .gmii_rx_clk(gmii_rx_clk),
+        .gmii_rx_dv(gmii_rx_dv),
+        .gmii_rxd(gmii_rxd),
+        .gmii_tx_en(gmii_tx_en),
+        .gmii_txd(gmii_txd),
+        .m_axis_rx_tdata(m_axis_rx_tdata),
+        .m_axis_rx_tvalid(m_axis_rx_tvalid),
+        .m_axis_rx_tready(m_axis_rx_tready),
+        .m_axis_rx_tlast(m_axis_rx_tlast),
+        .s_axis_tx_tdata(s_axis_tx_tdata),
+        .s_axis_tx_tvalid(s_axis_tx_tvalid),
+        .s_axis_tx_tready(s_axis_tx_tready),
+        .s_axis_tx_tlast(s_axis_tx_tlast),
+        .send_req(send_req),
+        .req_ready(req_ready),
+        .udp_rec_data_length(udp_rec_data_length)
+
+    );
+
+    // Clocks
+    always #4 gmii_rx_clk = ~gmii_rx_clk;
+    always #4 gmii_tx_clk = ~gmii_tx_clk;
+
+    // Helpers
+    task automatic gmii_idle;
+        input integer cycles;
+        integer i;
+        begin
+            gmii_rx_dv <= 1'b0;
+            gmii_rxd   <= 8'h00;
+            for (i = 0; i < cycles; i = i + 1) begin
+                @(posedge gmii_rx_clk);
+            end
+        end
+    endtask
+
+    task automatic send_gmii_byte;
+        input [7:0] b;
+        begin
+            @(posedge gmii_rx_clk);
+            gmii_rx_dv <= 1'b1;
+            gmii_rxd   <= b;
+        end
+    endtask
+
+    task automatic end_gmii_frame;
+        begin
+            @(posedge gmii_rx_clk);
+            gmii_rx_dv <= 1'b0;
+            gmii_rxd   <= 8'h00;
+        end
+    endtask
+
+    task automatic send_gmii_frame;
+        input integer frame_len;
+        input [8*2048-1:0] frame_data_flat;
+        integer i;
+        reg [7:0] current_byte;
+        begin
+            gmii_idle(12);
+
+            for (i = 0; i < frame_len; i = i + 1) begin
+                current_byte = frame_data_flat[i*8 +: 8];
+                send_gmii_byte(current_byte);
+            end
+
+            end_gmii_frame();
+
+            // inter-frame gap
+            gmii_idle(12);
+        end
+    endtask
+
+    reg [7:0] frame_mem [0:2047];
+
+    task automatic send_gmii_frame_mem;
+        input integer frame_len;
+        integer i;
+        begin
+            gmii_idle(12);
+
+            for (i = 0; i < frame_len; i = i + 1) begin
+                send_gmii_byte(frame_mem[i]);
+            end
+
+            end_gmii_frame();
+            gmii_idle(12);
+        end
+    endtask
+
+    // Monitor AXIS RX
+    always @(posedge gmii_rx_clk) begin
+        if (m_axis_rx_tvalid && m_axis_rx_tready) begin
+            $write("%02x ", m_axis_rx_tdata);
+            if (m_axis_rx_tlast)
+                $write("<TLAST>");
+        end
+        cnt = cnt + 1;
+        if (cnt % 8 < 6) begin
+            m_axis_rx_tready = 1'b1;
+        end else m_axis_rx_tready = 1'b0;
+    end
+
+    // Test sequence
+    integer i;
+
+    initial begin
+        // init
+        gmii_rx_dv = 1'b0;
+        gmii_rxd   = 8'h00;
+        rst_n      = 1'b0;
+
+        gmii_idle(200);
+        rst_n = 1'b1;
+        gmii_idle(200);
+
+                
+        frame_mem[0]  = 8'h55;
+        frame_mem[1]  = 8'h55;
+        frame_mem[2]  = 8'h55;
+        frame_mem[3]  = 8'h55;
+        frame_mem[4]  = 8'h55;
+        frame_mem[5]  = 8'h55;
+        frame_mem[6]  = 8'h55;
+        frame_mem[7]  = 8'hd5;
+
+        frame_mem[8]  = 8'h00;
+        frame_mem[9]  = 8'h0a;
+        frame_mem[10] = 8'h35;
+        frame_mem[11] = 8'h01;
+        frame_mem[12] = 8'hfe;
+        frame_mem[13] = 8'hc0;
+
+        frame_mem[14] = 8'h30;
+        frame_mem[15] = 8'h56;
+        frame_mem[16] = 8'h0f;
+        frame_mem[17] = 8'ha0;
+        frame_mem[18] = 8'h12;
+        frame_mem[19] = 8'hec;
+
+        frame_mem[20] = 8'h08;
+        frame_mem[21] = 8'h00;
+
+        frame_mem[22] = 8'h45;
+        frame_mem[23] = 8'h00;
+        frame_mem[24] = 8'h00;
+        frame_mem[25] = 8'h23;
+        frame_mem[26] = 8'h65;
+        frame_mem[27] = 8'hfa;
+        frame_mem[28] = 8'h40;
+        frame_mem[29] = 8'h00;
+        frame_mem[30] = 8'h40;
+        frame_mem[31] = 8'h11;
+        frame_mem[32] = 8'h53;
+        frame_mem[33] = 8'h7a;
+
+        frame_mem[34] = 8'hc0;
+        frame_mem[35] = 8'ha8;
+        frame_mem[36] = 8'h00;
+        frame_mem[37] = 8'h03;
+
+        frame_mem[38] = 8'hc0;
+        frame_mem[39] = 8'ha8;
+        frame_mem[40] = 8'h00;
+        frame_mem[41] = 8'h02;
+
+        frame_mem[42] = 8'hc0;
+        frame_mem[43] = 8'h31;
+        frame_mem[44] = 8'h1f;
+        frame_mem[45] = 8'h90;
+
+        frame_mem[46] = 8'h00;
+        frame_mem[47] = 8'h0f;
+        frame_mem[48] = 8'he4;
+        frame_mem[49] = 8'h7f;
+
+        frame_mem[50] = 8'h6e;
+        frame_mem[51] = 8'h65;
+        frame_mem[52] = 8'h77;
+        frame_mem[53] = 8'h5f;
+        frame_mem[54] = 8'h6d;
+        frame_mem[55] = 8'h73;
+        frame_mem[56] = 8'h67;
+
+        // FCS
+        frame_mem[57] = 8'h00;
+        frame_mem[58] = 8'h00;
+        frame_mem[59] = 8'h00;
+        frame_mem[60] = 8'h00;
+
+        frame_mem[61] = 8'h00;
+        frame_mem[62] = 8'h00;
+        frame_mem[63] = 8'h00;
+        frame_mem[64] = 8'h00;
+
+        frame_mem[65] = 8'h00;
+        frame_mem[66] = 8'h00;
+        frame_mem[67] = 8'h00;
+
+        frame_mem[68] = 8'h8c;
+        frame_mem[69] = 8'ha2;
+        frame_mem[70] = 8'h2e;
+        frame_mem[71] = 8'h26;
+        frame_mem[72] = 8'hdd;
+        send_gmii_frame_mem(73);
+
+        gmii_idle(200);
+        send_gmii_frame_mem(57);
+        gmii_idle(20);
+        send_gmii_frame_mem(57);
+        gmii_idle(200);
+        send_gmii_frame_mem(66);
+        gmii_idle(200);
+        send_gmii_frame_mem(66);
+        send_gmii_frame_mem(66);
+        gmii_idle(200);
+
+        $display("\nSimulation done OK");
+        $finish;
+    end
+
+endmodule

rtl/ethernet-udp/tests/eth_minimal/Makefile

@@ -22,6 +22,9 @@ SYN_FILES += $(sort $(shell find ../../src -type f \( -name '*.v' -o -name '*.sv
 
 XCI_FILES = $(sort $(shell find ../../src -type f -name '*.xci'))
 
+XDC_FILES += debug.xdc
+XDC_FILES += ../../../../constraints/ax7a035b.xdc
+
 program: $(PROJECT).bit
 	echo "open_hw_manager" > program.tcl
 	echo "connect_hw_server" >> program.tcl

rtl/ethernet-udp/tests/eth_minimal/axis_mac.sv

@@ -1,229 +0,0 @@
-`timescale 1 ns / 1 ns
-
-module axis_mac
-(
-    input                rst_n,
-    input                gmii_tx_clk,
-    input                gmii_rx_clk,
-    input                gmii_rx_dv,
-    input  [7:0]         gmii_rxd,
-
-    output reg           gmii_tx_en,
-    output reg [7:0]     gmii_txd,
-
-    // AXI-stream RX output (clock domain = gmii_rx_clk)
-    (* MARK_DEBUG="true" *)output reg  [7:0]    m_axis_rx_tdata,
-    (* MARK_DEBUG="true" *)output reg           m_axis_rx_tvalid,
-    input  wire          m_axis_rx_tready,
-    (* MARK_DEBUG="true" *)output reg           m_axis_rx_tlast
-);
-
-    // ----------------------------------------------------------------
-    // GMII RX input registering
-    // ----------------------------------------------------------------
-    reg        gmii_rx_dv_d0;
-    reg [7:0]  gmii_rxd_d0;
-
-    always @(posedge gmii_rx_clk or negedge rst_n) begin
-        if (!rst_n) begin
-            gmii_rx_dv_d0 <= 1'b0;
-            gmii_rxd_d0   <= 8'd0;
-        end else begin
-            gmii_rx_dv_d0 <= gmii_rx_dv;
-            gmii_rxd_d0   <= gmii_rxd;
-        end
-    end
-
-    // ----------------------------------------------------------------
-    // TX path from mac_top
-    // ----------------------------------------------------------------
-    wire       gmii_tx_en_tmp;
-    wire [7:0] gmii_txd_tmp;
-
-    always @(posedge gmii_tx_clk or negedge rst_n) begin
-        if (!rst_n) begin
-            gmii_tx_en <= 1'b0;
-            gmii_txd   <= 8'd0;
-        end else begin
-            gmii_tx_en <= gmii_tx_en_tmp;
-            gmii_txd   <= gmii_txd_tmp;
-        end
-    end
-
-    // ----------------------------------------------------------------
-    // Unused user TX path into mac_top
-    // We disable user UDP TX for now.
-    // ARP replies and ICMP replies inside mac_top still work.
-    // ----------------------------------------------------------------
-    wire       udp_ram_data_req;
-    wire       udp_tx_end;
-    wire       almost_full;
-    wire       mac_send_end;
-    wire       arp_found;
-    wire       mac_not_exist;
-
-    wire [7:0]  udp_rec_ram_rdata;
-    reg  [10:0] udp_rec_ram_read_addr;
-    wire [15:0] udp_rec_data_length;
-    wire        udp_rec_data_valid;
-
-    wire [7:0]  tx_ram_wr_data      = 8'd0;
-    wire        tx_ram_wr_en        = 1'b0;
-    wire [15:0] udp_send_data_length = 16'd0;
-    wire        udp_tx_req          = 1'b0;
-    wire        arp_request_req     = 1'b0;
-
-    mac_top mac_top0 (
-        .gmii_tx_clk               (gmii_tx_clk),
-        .gmii_rx_clk               (gmii_rx_clk),
-        .rst_n                     (rst_n),
-
-        .source_mac_addr           (48'h00_0a_35_01_fe_c0),
-        .TTL                       (8'h80),
-        .source_ip_addr            (32'hc0a80002),   // 192.168.0.2
-        .destination_ip_addr       (32'hc0a80003),   // 192.168.0.3 (не используется для user TX пока)
-        .udp_send_source_port      (16'h1f90),       // 8080
-        .udp_send_destination_port (16'h1f90),       // 8080
-
-        .ram_wr_data               (tx_ram_wr_data),
-        .ram_wr_en                 (tx_ram_wr_en),
-        .udp_ram_data_req          (udp_ram_data_req),
-        .udp_send_data_length      (udp_send_data_length),
-        .udp_tx_end                (udp_tx_end),
-        .almost_full               (almost_full),
-
-        .udp_tx_req                (udp_tx_req),
-        .arp_request_req           (arp_request_req),
-
-        .mac_send_end              (mac_send_end),
-        .mac_data_valid            (gmii_tx_en_tmp),
-        .mac_tx_data               (gmii_txd_tmp),
-
-        .rx_dv                     (gmii_rx_dv_d0),
-        .mac_rx_datain             (gmii_rxd_d0),
-
-        .udp_rec_ram_rdata         (udp_rec_ram_rdata),
-        .udp_rec_ram_read_addr     (udp_rec_ram_read_addr),
-        .udp_rec_data_length       (udp_rec_data_length),
-        .udp_rec_data_valid        (udp_rec_data_valid),
-
-        .arp_found                 (arp_found),
-        .mac_not_exist             (mac_not_exist)
-    );
-
-    // ----------------------------------------------------------------
-    // Detect "new packet ready" on udp_rec_data_valid rising edge
-    // ----------------------------------------------------------------
-    reg udp_rec_data_valid_d0;
-
-    always @(posedge gmii_rx_clk or negedge rst_n) begin
-        if (!rst_n)
-            udp_rec_data_valid_d0 <= 1'b0;
-        else
-            udp_rec_data_valid_d0 <= udp_rec_data_valid;
-    end
-
-    wire udp_pkt_done = udp_rec_data_valid & ~udp_rec_data_valid_d0;
-
-    // ----------------------------------------------------------------
-    // RX RAM -> AXI-stream bridge
-    //
-    // Assumption:
-    //   udp_rec_data_length includes 8-byte UDP header,
-    //   so payload length = udp_rec_data_length - 8
-    //
-    // This implementation is simple and safe:
-    // - start on udp_pkt_done
-    // - read bytes 0 .. payload_len-1 from RX RAM
-    // - output them on AXIS
-    //
-    // Because the BRAM read port is synchronous, this bridge may insert
-    // bubbles between bytes. For first bring-up this is fine.
-    // ----------------------------------------------------------------
-    localparam RX_IDLE  = 2'd0;
-    localparam RX_ADDR  = 2'd1;
-    localparam RX_DATA  = 2'd2;
-
-    (* MARK_DEBUG="true" *) reg [1:0]  rx_state;
-    (* MARK_DEBUG="true" *) reg [15:0] rx_payload_len;
-    (* MARK_DEBUG="true" *) reg [15:0] rx_index;
-
-    always @(posedge gmii_rx_clk or negedge rst_n) begin
-        if (!rst_n) begin
-            rx_state              <= RX_IDLE;
-            rx_payload_len        <= 16'd0;
-            rx_index              <= 16'd0;
-            udp_rec_ram_read_addr <= 11'd0;
-
-            m_axis_rx_tdata       <= 8'd0;
-            m_axis_rx_tvalid      <= 1'b0;
-            m_axis_rx_tlast       <= 1'b0;
-        end else begin
-            case (rx_state)
-                RX_IDLE: begin
-                    m_axis_rx_tvalid <= 1'b0;
-                    m_axis_rx_tlast  <= 1'b0;
-                    rx_index         <= 16'd0;
-                    udp_rec_ram_read_addr <= 11'd0;
-
-                    if (udp_pkt_done) begin
-                        // protect against pathological short values
-                        if (udp_rec_data_length > 16'd8) begin
-                            rx_payload_len        <= udp_rec_data_length - 16'd8;
-                            udp_rec_ram_read_addr <= 11'd0;   // issue read for byte 0
-                            rx_state              <= RX_ADDR;
-                        end else begin
-                            rx_payload_len <= 16'd0;
-                            rx_state       <= RX_IDLE;
-                        end
-                    end
-                end
-
-                // one cycle for synchronous BRAM read latency
-                RX_ADDR: begin
-                    m_axis_rx_tvalid <= 1'b0;
-                    m_axis_rx_tlast  <= 1'b0;
-                    rx_state         <= RX_DATA;
-                end
-
-                RX_DATA: begin
-                    // hold valid until accepted
-                    if (m_axis_rx_tvalid && !m_axis_rx_tready) begin
-                        m_axis_rx_tvalid <= m_axis_rx_tvalid;
-                        m_axis_rx_tlast  <= m_axis_rx_tlast;
-                    end else begin
-                        // present current byte from RAM
-                        m_axis_rx_tdata  <= udp_rec_ram_rdata;
-                        m_axis_rx_tvalid <= 1'b1;
-                        m_axis_rx_tlast  <= (rx_index == rx_payload_len - 1);
-
-                        if (rx_index == rx_payload_len - 1) begin
-                            // last byte accepted immediately if ready=1,
-                            // otherwise valid/last remain asserted until ready
-                            if (m_axis_rx_tready) begin
-                                m_axis_rx_tvalid <= 1'b0;
-                                m_axis_rx_tlast  <= 1'b0;
-                                rx_state         <= RX_IDLE;
-                            end
-                        end else begin
-                            if (m_axis_rx_tready) begin
-                                rx_index <= rx_index + 1'b1;
-                                udp_rec_ram_read_addr <= rx_index + 1'b1; // next byte
-                                rx_state <= RX_ADDR;
-                                m_axis_rx_tvalid <= 1'b0;
-                                m_axis_rx_tlast  <= 1'b0;
-                            end
-                        end
-                    end
-                end
-
-                default: begin
-                    rx_state         <= RX_IDLE;
-                    m_axis_rx_tvalid <= 1'b0;
-                    m_axis_rx_tlast  <= 1'b0;
-                end
-            endcase
-        end
-    end
-
-endmodule

rtl/ethernet-udp/tests/eth_minimal/debug.xdc

@@ -0,0 +1,188 @@
+# debug ILA
+
+create_debug_core u_ila_0 ila
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
+set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
+set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
+set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
+set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
+set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
+set_property port_width 1 [get_debug_ports u_ila_0/clk]
+connect_debug_port u_ila_0/clk [get_nets [list rgmii_rxc_IBUF_BUFG]]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
+set_property port_width 9 [get_debug_ports u_ila_0/probe0]
+connect_debug_port u_ila_0/probe0 [get_nets [list {mac_test0/state[0]} {mac_test0/state[1]} {mac_test0/state[2]} {mac_test0/state[3]} {mac_test0/state[4]} {mac_test0/state[5]} {mac_test0/state[6]} {mac_test0/state[7]} {mac_test0/state[8]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
+set_property port_width 8 [get_debug_ports u_ila_0/probe1]
+connect_debug_port u_ila_0/probe1 [get_nets [list {arbi_inst/rx_buffer_inst/e10_100_rxd[0]} {arbi_inst/rx_buffer_inst/e10_100_rxd[1]} {arbi_inst/rx_buffer_inst/e10_100_rxd[2]} {arbi_inst/rx_buffer_inst/e10_100_rxd[3]} {arbi_inst/rx_buffer_inst/e10_100_rxd[4]} {arbi_inst/rx_buffer_inst/e10_100_rxd[5]} {arbi_inst/rx_buffer_inst/e10_100_rxd[6]} {arbi_inst/rx_buffer_inst/e10_100_rxd[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
+set_property port_width 8 [get_debug_ports u_ila_0/probe2]
+connect_debug_port u_ila_0/probe2 [get_nets [list {arbi_inst/tx_buffer_inst/tx_wdata[0]} {arbi_inst/tx_buffer_inst/tx_wdata[1]} {arbi_inst/tx_buffer_inst/tx_wdata[2]} {arbi_inst/tx_buffer_inst/tx_wdata[3]} {arbi_inst/tx_buffer_inst/tx_wdata[4]} {arbi_inst/tx_buffer_inst/tx_wdata[5]} {arbi_inst/tx_buffer_inst/tx_wdata[6]} {arbi_inst/tx_buffer_inst/tx_wdata[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
+set_property port_width 8 [get_debug_ports u_ila_0/probe3]
+connect_debug_port u_ila_0/probe3 [get_nets [list {arbi_inst/tx_buffer_inst/tx_rdata[0]} {arbi_inst/tx_buffer_inst/tx_rdata[1]} {arbi_inst/tx_buffer_inst/tx_rdata[2]} {arbi_inst/tx_buffer_inst/tx_rdata[3]} {arbi_inst/tx_buffer_inst/tx_rdata[4]} {arbi_inst/tx_buffer_inst/tx_rdata[5]} {arbi_inst/tx_buffer_inst/tx_rdata[6]} {arbi_inst/tx_buffer_inst/tx_rdata[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
+set_property port_width 16 [get_debug_ports u_ila_0/probe4]
+connect_debug_port u_ila_0/probe4 [get_nets [list {arbi_inst/tx_buffer_inst/tx_data_cnt[0]} {arbi_inst/tx_buffer_inst/tx_data_cnt[1]} {arbi_inst/tx_buffer_inst/tx_data_cnt[2]} {arbi_inst/tx_buffer_inst/tx_data_cnt[3]} {arbi_inst/tx_buffer_inst/tx_data_cnt[4]} {arbi_inst/tx_buffer_inst/tx_data_cnt[5]} {arbi_inst/tx_buffer_inst/tx_data_cnt[6]} {arbi_inst/tx_buffer_inst/tx_data_cnt[7]} {arbi_inst/tx_buffer_inst/tx_data_cnt[8]} {arbi_inst/tx_buffer_inst/tx_data_cnt[9]} {arbi_inst/tx_buffer_inst/tx_data_cnt[10]} {arbi_inst/tx_buffer_inst/tx_data_cnt[11]} {arbi_inst/tx_buffer_inst/tx_data_cnt[12]} {arbi_inst/tx_buffer_inst/tx_data_cnt[13]} {arbi_inst/tx_buffer_inst/tx_data_cnt[14]} {arbi_inst/tx_buffer_inst/tx_data_cnt[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
+set_property port_width 16 [get_debug_ports u_ila_0/probe5]
+connect_debug_port u_ila_0/probe5 [get_nets [list {mac_test0/mac_top0/mac_tx0/udp_send_data_length[0]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[1]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[2]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[3]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[4]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[5]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[6]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[7]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[8]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[9]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[10]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[11]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[12]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[13]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[14]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
+set_property port_width 12 [get_debug_ports u_ila_0/probe6]
+connect_debug_port u_ila_0/probe6 [get_nets [list {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[0]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[1]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[2]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[3]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[4]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[5]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[6]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[7]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[8]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[9]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[10]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[11]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
+set_property port_width 8 [get_debug_ports u_ila_0/probe7]
+connect_debug_port u_ila_0/probe7 [get_nets [list {mac_test0/mac_top0/mac_tx0/ram_wr_data[0]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[1]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[2]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[3]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[4]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[5]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[6]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
+set_property port_width 8 [get_debug_ports u_ila_0/probe8]
+connect_debug_port u_ila_0/probe8 [get_nets [list {mac_test0/mac_top0/mac_tx0/mac_tx_data[0]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[1]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[2]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[3]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[4]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[5]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[6]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
+set_property port_width 4 [get_debug_ports u_ila_0/probe9]
+connect_debug_port u_ila_0/probe9 [get_nets [list {mac_test0/mac_top0/mac_tx0/udp0/usedw[0]} {mac_test0/mac_top0/mac_tx0/udp0/usedw[1]} {mac_test0/mac_top0/mac_tx0/udp0/usedw[2]} {mac_test0/mac_top0/mac_tx0/udp0/usedw[3]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
+set_property port_width 6 [get_debug_ports u_ila_0/probe10]
+connect_debug_port u_ila_0/probe10 [get_nets [list {mac_test0/mac_top0/mac_tx0/udp0/state[0]} {mac_test0/mac_top0/mac_tx0/udp0/state[1]} {mac_test0/mac_top0/mac_tx0/udp0/state[2]} {mac_test0/mac_top0/mac_tx0/udp0/state[3]} {mac_test0/mac_top0/mac_tx0/udp0/state[4]} {mac_test0/mac_top0/mac_tx0/udp0/state[5]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
+set_property port_width 6 [get_debug_ports u_ila_0/probe11]
+connect_debug_port u_ila_0/probe11 [get_nets [list {mac_test0/mac_top0/mac_tx0/udp0/ck_state[0]} {mac_test0/mac_top0/mac_tx0/udp0/ck_state[1]} {mac_test0/mac_top0/mac_tx0/udp0/ck_state[2]} {mac_test0/mac_top0/mac_tx0/udp0/ck_state[3]} {mac_test0/mac_top0/mac_tx0/udp0/ck_state[4]} {mac_test0/mac_top0/mac_tx0/udp0/ck_state[5]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
+set_property port_width 16 [get_debug_ports u_ila_0/probe12]
+connect_debug_port u_ila_0/probe12 [get_nets [list {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[0]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[1]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[2]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[3]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[4]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[5]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[6]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[7]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[8]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[9]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[10]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[11]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[12]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[13]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[14]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
+set_property port_width 11 [get_debug_ports u_ila_0/probe13]
+connect_debug_port u_ila_0/probe13 [get_nets [list {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[0]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[1]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[2]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[3]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[4]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[5]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[6]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[7]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[8]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[9]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[10]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
+set_property port_width 8 [get_debug_ports u_ila_0/probe14]
+connect_debug_port u_ila_0/probe14 [get_nets [list {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[0]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[1]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[2]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[3]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[4]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[5]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[6]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
+set_property port_width 16 [get_debug_ports u_ila_0/probe15]
+connect_debug_port u_ila_0/probe15 [get_nets [list {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[0]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[1]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[2]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[3]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[4]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[5]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[6]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[7]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[8]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[9]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[10]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[11]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[12]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[13]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[14]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
+set_property port_width 8 [get_debug_ports u_ila_0/probe16]
+connect_debug_port u_ila_0/probe16 [get_nets [list {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[0]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[1]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[2]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[3]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[4]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[5]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[6]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
+set_property port_width 16 [get_debug_ports u_ila_0/probe17]
+connect_debug_port u_ila_0/probe17 [get_nets [list {mac_test0/mac_top0/mac_rx0/ip_total_data_length[0]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[1]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[2]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[3]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[4]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[5]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[6]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[7]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[8]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[9]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[10]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[11]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[12]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[13]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[14]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
+set_property port_width 8 [get_debug_ports u_ila_0/probe18]
+connect_debug_port u_ila_0/probe18 [get_nets [list {mac_test0/mac_top0/mac_rx0/mac_rx_datain[0]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[1]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[2]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[3]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[4]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[5]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[6]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
+set_property port_width 11 [get_debug_ports u_ila_0/probe19]
+connect_debug_port u_ila_0/probe19 [get_nets [list {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[0]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[1]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[2]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[3]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[4]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[5]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[6]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[7]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[8]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[9]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[10]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
+set_property port_width 8 [get_debug_ports u_ila_0/probe20]
+connect_debug_port u_ila_0/probe20 [get_nets [list {arbi_inst/gmii_txd[0]} {arbi_inst/gmii_txd[1]} {arbi_inst/gmii_txd[2]} {arbi_inst/gmii_txd[3]} {arbi_inst/gmii_txd[4]} {arbi_inst/gmii_txd[5]} {arbi_inst/gmii_txd[6]} {arbi_inst/gmii_txd[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
+set_property port_width 8 [get_debug_ports u_ila_0/probe21]
+connect_debug_port u_ila_0/probe21 [get_nets [list {arbi_inst/gmii_rxd[0]} {arbi_inst/gmii_rxd[1]} {arbi_inst/gmii_rxd[2]} {arbi_inst/gmii_rxd[3]} {arbi_inst/gmii_rxd[4]} {arbi_inst/gmii_rxd[5]} {arbi_inst/gmii_rxd[6]} {arbi_inst/gmii_rxd[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
+set_property port_width 8 [get_debug_ports u_ila_0/probe22]
+connect_debug_port u_ila_0/probe22 [get_nets [list {arbi_inst/e_txd[0]} {arbi_inst/e_txd[1]} {arbi_inst/e_txd[2]} {arbi_inst/e_txd[3]} {arbi_inst/e_txd[4]} {arbi_inst/e_txd[5]} {arbi_inst/e_txd[6]} {arbi_inst/e_txd[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
+set_property port_width 8 [get_debug_ports u_ila_0/probe23]
+connect_debug_port u_ila_0/probe23 [get_nets [list {arbi_inst/e_rxd[0]} {arbi_inst/e_rxd[1]} {arbi_inst/e_rxd[2]} {arbi_inst/e_rxd[3]} {arbi_inst/e_rxd[4]} {arbi_inst/e_rxd[5]} {arbi_inst/e_rxd[6]} {arbi_inst/e_rxd[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
+set_property port_width 1 [get_debug_ports u_ila_0/probe24]
+connect_debug_port u_ila_0/probe24 [get_nets [list mac_test0/mac_top0/mac_tx0/almost_full]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
+set_property port_width 1 [get_debug_ports u_ila_0/probe25]
+connect_debug_port u_ila_0/probe25 [get_nets [list arbi_inst/rx_buffer_inst/e10_100_rx_dv]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
+set_property port_width 1 [get_debug_ports u_ila_0/probe26]
+connect_debug_port u_ila_0/probe26 [get_nets [list arbi_inst/e_rx_dv]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
+set_property port_width 1 [get_debug_ports u_ila_0/probe27]
+connect_debug_port u_ila_0/probe27 [get_nets [list arbi_inst/e_tx_en]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
+set_property port_width 1 [get_debug_ports u_ila_0/probe28]
+connect_debug_port u_ila_0/probe28 [get_nets [list arbi_inst/gmii_rx_dv]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
+set_property port_width 1 [get_debug_ports u_ila_0/probe29]
+connect_debug_port u_ila_0/probe29 [get_nets [list arbi_inst/rx_buffer_inst/gmii_rx_dv_d0]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
+set_property port_width 1 [get_debug_ports u_ila_0/probe30]
+connect_debug_port u_ila_0/probe30 [get_nets [list arbi_inst/rx_buffer_inst/gmii_rx_dv_d1]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
+set_property port_width 1 [get_debug_ports u_ila_0/probe31]
+connect_debug_port u_ila_0/probe31 [get_nets [list arbi_inst/gmii_tx_en]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
+set_property port_width 1 [get_debug_ports u_ila_0/probe32]
+connect_debug_port u_ila_0/probe32 [get_nets [list mac_test0/mac_top0/mac_tx0/mac_data_valid]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
+set_property port_width 1 [get_debug_ports u_ila_0/probe33]
+connect_debug_port u_ila_0/probe33 [get_nets [list mac_test0/mac_top0/mac_tx0/mac_send_end]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
+set_property port_width 1 [get_debug_ports u_ila_0/probe34]
+connect_debug_port u_ila_0/probe34 [get_nets [list mac_test0/mac_top0/mac_rx0/udp0/ram_wr_en]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
+set_property port_width 1 [get_debug_ports u_ila_0/probe35]
+connect_debug_port u_ila_0/probe35 [get_nets [list mac_test0/mac_top0/mac_tx0/ram_wr_en]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
+set_property port_width 1 [get_debug_ports u_ila_0/probe36]
+connect_debug_port u_ila_0/probe36 [get_nets [list arbi_inst/tx_buffer_inst/tx_rden]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
+set_property port_width 1 [get_debug_ports u_ila_0/probe37]
+connect_debug_port u_ila_0/probe37 [get_nets [list arbi_inst/tx_buffer_inst/tx_wren]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
+set_property port_width 1 [get_debug_ports u_ila_0/probe38]
+connect_debug_port u_ila_0/probe38 [get_nets [list mac_test0/mac_top0/mac_tx0/udp_ram_data_req]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39]
+set_property port_width 1 [get_debug_ports u_ila_0/probe39]
+connect_debug_port u_ila_0/probe39 [get_nets [list mac_test0/mac_top0/mac_rx0/udp_rec_data_valid]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40]
+set_property port_width 1 [get_debug_ports u_ila_0/probe40]
+connect_debug_port u_ila_0/probe40 [get_nets [list mac_test0/mac_top0/mac_tx0/udp_tx_end]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41]
+set_property port_width 1 [get_debug_ports u_ila_0/probe41]
+connect_debug_port u_ila_0/probe41 [get_nets [list mac_test0/mac_top0/mac_tx0/udp_tx_req]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42]
+set_property port_width 1 [get_debug_ports u_ila_0/probe42]
+connect_debug_port u_ila_0/probe42 [get_nets [list mac_test0/mac_top0/mac_tx0/upper_data_req]]
+set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
+set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+connect_debug_port dbg_hub/clk [get_nets rgmii_rxc_IBUF_BUFG]

rtl/ethernet-udp/tests/eth_minimal/ethernet_test_minimal.v

@@ -1,31 +1,3 @@
-//////////////////////////////////////////////////////////////////////////////////
-//                                                                              //
-//                                                                              //
-//  Author: lhj                                                                 //
-//                                                                              //
-//          ALINX(shanghai) Technology Co.,Ltd                                  //
-//          heijin                                                              //
-//     WEB: http://www.alinx.com/                                               //
-//     BBS: http://www.heijin.org/                                              //
-//                                                                              //
-//////////////////////////////////////////////////////////////////////////////////
-//                                                                              //
-// Copyright (c) 2017,ALINX(shanghai) Technology Co.,Ltd                        //
-//                    All rights reserved                                       //
-//                                                                              //
-// This source file may be used and distributed without restriction provided    //
-// that this copyright statement is not removed from the file and that any      //
-// derivative work contains the original copyright notice and the associated    //
-// disclaimer.                                                                  //
-//                                                                              //
-//////////////////////////////////////////////////////////////////////////////////
-
-//================================================================================
-//  Revision History:
-//  Date          By            Revision    Change Description
-//--------------------------------------------------------------------------------
-//  2019/08/19   
-//*******************************************************************************/
 module ethernet_test_minimal
 (
 input               sys_clk_p,                       //system clock positive

rtl/ethernet-udp/tests/eth_minimal/ethernet_test_minimal.xdc

@@ -49,3 +49,193 @@ set_property PACKAGE_PIN R19 [get_ports rgmii_rxctl]
 set_property PACKAGE_PIN P15 [get_ports rgmii_txc]
 set_property PACKAGE_PIN N17 [get_ports rgmii_txctl]
 
+
+
+
+
+create_debug_core u_ila_0 ila
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
+set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
+set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
+set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
+set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
+set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
+set_property port_width 1 [get_debug_ports u_ila_0/clk]
+connect_debug_port u_ila_0/clk [get_nets [list rgmii_rxc_IBUF_BUFG]]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
+set_property port_width 9 [get_debug_ports u_ila_0/probe0]
+connect_debug_port u_ila_0/probe0 [get_nets [list {mac_test0/state[0]} {mac_test0/state[1]} {mac_test0/state[2]} {mac_test0/state[3]} {mac_test0/state[4]} {mac_test0/state[5]} {mac_test0/state[6]} {mac_test0/state[7]} {mac_test0/state[8]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
+set_property port_width 8 [get_debug_ports u_ila_0/probe1]
+connect_debug_port u_ila_0/probe1 [get_nets [list {arbi_inst/rx_buffer_inst/e10_100_rxd[0]} {arbi_inst/rx_buffer_inst/e10_100_rxd[1]} {arbi_inst/rx_buffer_inst/e10_100_rxd[2]} {arbi_inst/rx_buffer_inst/e10_100_rxd[3]} {arbi_inst/rx_buffer_inst/e10_100_rxd[4]} {arbi_inst/rx_buffer_inst/e10_100_rxd[5]} {arbi_inst/rx_buffer_inst/e10_100_rxd[6]} {arbi_inst/rx_buffer_inst/e10_100_rxd[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
+set_property port_width 8 [get_debug_ports u_ila_0/probe2]
+connect_debug_port u_ila_0/probe2 [get_nets [list {arbi_inst/gmii_txd[0]} {arbi_inst/gmii_txd[1]} {arbi_inst/gmii_txd[2]} {arbi_inst/gmii_txd[3]} {arbi_inst/gmii_txd[4]} {arbi_inst/gmii_txd[5]} {arbi_inst/gmii_txd[6]} {arbi_inst/gmii_txd[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
+set_property port_width 8 [get_debug_ports u_ila_0/probe3]
+connect_debug_port u_ila_0/probe3 [get_nets [list {arbi_inst/gmii_rxd[0]} {arbi_inst/gmii_rxd[1]} {arbi_inst/gmii_rxd[2]} {arbi_inst/gmii_rxd[3]} {arbi_inst/gmii_rxd[4]} {arbi_inst/gmii_rxd[5]} {arbi_inst/gmii_rxd[6]} {arbi_inst/gmii_rxd[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
+set_property port_width 8 [get_debug_ports u_ila_0/probe4]
+connect_debug_port u_ila_0/probe4 [get_nets [list {arbi_inst/e_txd[0]} {arbi_inst/e_txd[1]} {arbi_inst/e_txd[2]} {arbi_inst/e_txd[3]} {arbi_inst/e_txd[4]} {arbi_inst/e_txd[5]} {arbi_inst/e_txd[6]} {arbi_inst/e_txd[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
+set_property port_width 8 [get_debug_ports u_ila_0/probe5]
+connect_debug_port u_ila_0/probe5 [get_nets [list {arbi_inst/e_rxd[0]} {arbi_inst/e_rxd[1]} {arbi_inst/e_rxd[2]} {arbi_inst/e_rxd[3]} {arbi_inst/e_rxd[4]} {arbi_inst/e_rxd[5]} {arbi_inst/e_rxd[6]} {arbi_inst/e_rxd[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
+set_property port_width 8 [get_debug_ports u_ila_0/probe6]
+connect_debug_port u_ila_0/probe6 [get_nets [list {arbi_inst/tx_buffer_inst/tx_wdata[0]} {arbi_inst/tx_buffer_inst/tx_wdata[1]} {arbi_inst/tx_buffer_inst/tx_wdata[2]} {arbi_inst/tx_buffer_inst/tx_wdata[3]} {arbi_inst/tx_buffer_inst/tx_wdata[4]} {arbi_inst/tx_buffer_inst/tx_wdata[5]} {arbi_inst/tx_buffer_inst/tx_wdata[6]} {arbi_inst/tx_buffer_inst/tx_wdata[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
+set_property port_width 8 [get_debug_ports u_ila_0/probe7]
+connect_debug_port u_ila_0/probe7 [get_nets [list {arbi_inst/tx_buffer_inst/tx_rdata[0]} {arbi_inst/tx_buffer_inst/tx_rdata[1]} {arbi_inst/tx_buffer_inst/tx_rdata[2]} {arbi_inst/tx_buffer_inst/tx_rdata[3]} {arbi_inst/tx_buffer_inst/tx_rdata[4]} {arbi_inst/tx_buffer_inst/tx_rdata[5]} {arbi_inst/tx_buffer_inst/tx_rdata[6]} {arbi_inst/tx_buffer_inst/tx_rdata[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
+set_property port_width 16 [get_debug_ports u_ila_0/probe8]
+connect_debug_port u_ila_0/probe8 [get_nets [list {arbi_inst/tx_buffer_inst/tx_data_cnt[0]} {arbi_inst/tx_buffer_inst/tx_data_cnt[1]} {arbi_inst/tx_buffer_inst/tx_data_cnt[2]} {arbi_inst/tx_buffer_inst/tx_data_cnt[3]} {arbi_inst/tx_buffer_inst/tx_data_cnt[4]} {arbi_inst/tx_buffer_inst/tx_data_cnt[5]} {arbi_inst/tx_buffer_inst/tx_data_cnt[6]} {arbi_inst/tx_buffer_inst/tx_data_cnt[7]} {arbi_inst/tx_buffer_inst/tx_data_cnt[8]} {arbi_inst/tx_buffer_inst/tx_data_cnt[9]} {arbi_inst/tx_buffer_inst/tx_data_cnt[10]} {arbi_inst/tx_buffer_inst/tx_data_cnt[11]} {arbi_inst/tx_buffer_inst/tx_data_cnt[12]} {arbi_inst/tx_buffer_inst/tx_data_cnt[13]} {arbi_inst/tx_buffer_inst/tx_data_cnt[14]} {arbi_inst/tx_buffer_inst/tx_data_cnt[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
+set_property port_width 6 [get_debug_ports u_ila_0/probe9]
+connect_debug_port u_ila_0/probe9 [get_nets [list {mac_test0/mac_top0/mac_tx0/udp0/ck_state[0]} {mac_test0/mac_top0/mac_tx0/udp0/ck_state[1]} {mac_test0/mac_top0/mac_tx0/udp0/ck_state[2]} {mac_test0/mac_top0/mac_tx0/udp0/ck_state[3]} {mac_test0/mac_top0/mac_tx0/udp0/ck_state[4]} {mac_test0/mac_top0/mac_tx0/udp0/ck_state[5]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
+set_property port_width 16 [get_debug_ports u_ila_0/probe10]
+connect_debug_port u_ila_0/probe10 [get_nets [list {mac_test0/mac_top0/mac_tx0/udp_send_data_length[0]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[1]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[2]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[3]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[4]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[5]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[6]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[7]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[8]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[9]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[10]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[11]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[12]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[13]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[14]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
+set_property port_width 8 [get_debug_ports u_ila_0/probe11]
+connect_debug_port u_ila_0/probe11 [get_nets [list {mac_test0/mac_top0/mac_tx0/ram_wr_data[0]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[1]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[2]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[3]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[4]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[5]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[6]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
+set_property port_width 8 [get_debug_ports u_ila_0/probe12]
+connect_debug_port u_ila_0/probe12 [get_nets [list {mac_test0/mac_top0/mac_tx0/mac_tx_data[0]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[1]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[2]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[3]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[4]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[5]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[6]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
+set_property port_width 4 [get_debug_ports u_ila_0/probe13]
+connect_debug_port u_ila_0/probe13 [get_nets [list {mac_test0/mac_top0/mac_tx0/udp0/usedw[0]} {mac_test0/mac_top0/mac_tx0/udp0/usedw[1]} {mac_test0/mac_top0/mac_tx0/udp0/usedw[2]} {mac_test0/mac_top0/mac_tx0/udp0/usedw[3]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
+set_property port_width 6 [get_debug_ports u_ila_0/probe14]
+connect_debug_port u_ila_0/probe14 [get_nets [list {mac_test0/mac_top0/mac_tx0/udp0/state[0]} {mac_test0/mac_top0/mac_tx0/udp0/state[1]} {mac_test0/mac_top0/mac_tx0/udp0/state[2]} {mac_test0/mac_top0/mac_tx0/udp0/state[3]} {mac_test0/mac_top0/mac_tx0/udp0/state[4]} {mac_test0/mac_top0/mac_tx0/udp0/state[5]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
+set_property port_width 12 [get_debug_ports u_ila_0/probe15]
+connect_debug_port u_ila_0/probe15 [get_nets [list {mac_test0/mac_top0/mac_tx0/udp0/dbg_fifo_count[0]} {mac_test0/mac_top0/mac_tx0/udp0/dbg_fifo_count[1]} {mac_test0/mac_top0/mac_tx0/udp0/dbg_fifo_count[2]} {mac_test0/mac_top0/mac_tx0/udp0/dbg_fifo_count[3]} {mac_test0/mac_top0/mac_tx0/udp0/dbg_fifo_count[4]} {mac_test0/mac_top0/mac_tx0/udp0/dbg_fifo_count[5]} {mac_test0/mac_top0/mac_tx0/udp0/dbg_fifo_count[6]} {mac_test0/mac_top0/mac_tx0/udp0/dbg_fifo_count[7]} {mac_test0/mac_top0/mac_tx0/udp0/dbg_fifo_count[8]} {mac_test0/mac_top0/mac_tx0/udp0/dbg_fifo_count[9]} {mac_test0/mac_top0/mac_tx0/udp0/dbg_fifo_count[10]} {mac_test0/mac_top0/mac_tx0/udp0/dbg_fifo_count[11]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
+set_property port_width 16 [get_debug_ports u_ila_0/probe16]
+connect_debug_port u_ila_0/probe16 [get_nets [list {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[0]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[1]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[2]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[3]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[4]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[5]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[6]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[7]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[8]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[9]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[10]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[11]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[12]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[13]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[14]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
+set_property port_width 11 [get_debug_ports u_ila_0/probe17]
+connect_debug_port u_ila_0/probe17 [get_nets [list {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[0]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[1]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[2]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[3]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[4]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[5]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[6]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[7]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[8]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[9]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[10]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
+set_property port_width 8 [get_debug_ports u_ila_0/probe18]
+connect_debug_port u_ila_0/probe18 [get_nets [list {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[0]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[1]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[2]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[3]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[4]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[5]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[6]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
+set_property port_width 16 [get_debug_ports u_ila_0/probe19]
+connect_debug_port u_ila_0/probe19 [get_nets [list {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[0]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[1]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[2]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[3]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[4]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[5]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[6]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[7]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[8]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[9]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[10]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[11]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[12]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[13]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[14]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
+set_property port_width 8 [get_debug_ports u_ila_0/probe20]
+connect_debug_port u_ila_0/probe20 [get_nets [list {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[0]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[1]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[2]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[3]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[4]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[5]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[6]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
+set_property port_width 16 [get_debug_ports u_ila_0/probe21]
+connect_debug_port u_ila_0/probe21 [get_nets [list {mac_test0/mac_top0/mac_rx0/ip_total_data_length[0]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[1]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[2]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[3]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[4]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[5]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[6]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[7]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[8]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[9]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[10]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[11]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[12]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[13]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[14]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
+set_property port_width 8 [get_debug_ports u_ila_0/probe22]
+connect_debug_port u_ila_0/probe22 [get_nets [list {mac_test0/mac_top0/mac_rx0/mac_rx_datain[0]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[1]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[2]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[3]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[4]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[5]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[6]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
+set_property port_width 11 [get_debug_ports u_ila_0/probe23]
+connect_debug_port u_ila_0/probe23 [get_nets [list {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[0]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[1]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[2]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[3]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[4]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[5]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[6]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[7]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[8]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[9]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[10]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
+set_property port_width 1 [get_debug_ports u_ila_0/probe24]
+connect_debug_port u_ila_0/probe24 [get_nets [list mac_test0/mac_top0/mac_tx0/almost_full]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
+set_property port_width 1 [get_debug_ports u_ila_0/probe25]
+connect_debug_port u_ila_0/probe25 [get_nets [list arbi_inst/rx_buffer_inst/e10_100_rx_dv]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
+set_property port_width 1 [get_debug_ports u_ila_0/probe26]
+connect_debug_port u_ila_0/probe26 [get_nets [list arbi_inst/e_rx_dv]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
+set_property port_width 1 [get_debug_ports u_ila_0/probe27]
+connect_debug_port u_ila_0/probe27 [get_nets [list arbi_inst/e_tx_en]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
+set_property port_width 1 [get_debug_ports u_ila_0/probe28]
+connect_debug_port u_ila_0/probe28 [get_nets [list arbi_inst/gmii_rx_dv]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
+set_property port_width 1 [get_debug_ports u_ila_0/probe29]
+connect_debug_port u_ila_0/probe29 [get_nets [list arbi_inst/rx_buffer_inst/gmii_rx_dv_d0]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
+set_property port_width 1 [get_debug_ports u_ila_0/probe30]
+connect_debug_port u_ila_0/probe30 [get_nets [list arbi_inst/rx_buffer_inst/gmii_rx_dv_d1]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
+set_property port_width 1 [get_debug_ports u_ila_0/probe31]
+connect_debug_port u_ila_0/probe31 [get_nets [list arbi_inst/gmii_tx_en]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
+set_property port_width 1 [get_debug_ports u_ila_0/probe32]
+connect_debug_port u_ila_0/probe32 [get_nets [list mac_test0/mac_top0/mac_tx0/mac_data_valid]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
+set_property port_width 1 [get_debug_ports u_ila_0/probe33]
+connect_debug_port u_ila_0/probe33 [get_nets [list mac_test0/mac_top0/mac_tx0/mac_send_end]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
+set_property port_width 1 [get_debug_ports u_ila_0/probe34]
+connect_debug_port u_ila_0/probe34 [get_nets [list mac_test0/mac_top0/mac_tx0/ram_wr_en]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
+set_property port_width 1 [get_debug_ports u_ila_0/probe35]
+connect_debug_port u_ila_0/probe35 [get_nets [list mac_test0/mac_top0/mac_rx0/udp0/ram_wr_en]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
+set_property port_width 1 [get_debug_ports u_ila_0/probe36]
+connect_debug_port u_ila_0/probe36 [get_nets [list arbi_inst/tx_buffer_inst/tx_rden]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
+set_property port_width 1 [get_debug_ports u_ila_0/probe37]
+connect_debug_port u_ila_0/probe37 [get_nets [list arbi_inst/tx_buffer_inst/tx_wren]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
+set_property port_width 1 [get_debug_ports u_ila_0/probe38]
+connect_debug_port u_ila_0/probe38 [get_nets [list mac_test0/mac_top0/mac_tx0/udp_ram_data_req]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39]
+set_property port_width 1 [get_debug_ports u_ila_0/probe39]
+connect_debug_port u_ila_0/probe39 [get_nets [list mac_test0/mac_top0/mac_rx0/udp_rec_data_valid]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40]
+set_property port_width 1 [get_debug_ports u_ila_0/probe40]
+connect_debug_port u_ila_0/probe40 [get_nets [list mac_test0/mac_top0/mac_tx0/udp_tx_end]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41]
+set_property port_width 1 [get_debug_ports u_ila_0/probe41]
+connect_debug_port u_ila_0/probe41 [get_nets [list mac_test0/mac_top0/mac_tx0/udp_tx_req]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42]
+set_property port_width 1 [get_debug_ports u_ila_0/probe42]
+connect_debug_port u_ila_0/probe42 [get_nets [list mac_test0/mac_top0/mac_tx0/upper_data_req]]
+set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
+set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+connect_debug_port dbg_hub/clk [get_nets rgmii_rxc_IBUF_BUFG]

scripts/vivado.mk

@@ -37,7 +37,7 @@
 ###################################################################
 
 # phony targets
-.PHONY: fpga vivado tmpclean clean distclean
+.PHONY: fpga vivado sim sim-gui simclean tmpclean clean distclean
 
 # prevent make from deleting intermediate files and reports
 .PRECIOUS: %.xpr %.bit %.bin %.ltx %.xsa %.mcs %.prm
@@ -46,7 +46,7 @@
 
 FPGA_TOP ?= $(FPGA_TOP)
 PROJECT ?= $(FPGA_TOP)
-XDC_FILES ?= $(PROJECT).xdc
+# XDC_FILES ?= $(PROJECT).xdc
 
 # handle file list files
 process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
@@ -55,6 +55,14 @@ uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $
 SYN_FILES := $(call uniq_base,$(call process_f_files,$(SYN_FILES)))
 INC_FILES := $(call uniq_base,$(call process_f_files,$(INC_FILES)))
 
+# simulation parameters
+SIM_TOP ?= $(FPGA_TOP)_tb
+TB_FILES ?=
+SIM_FILES ?= $(SYN_FILES) $(TB_FILES)
+SIM_DEFS ?= $(DEFS)
+SIM_RUNTIME ?= all
+
+
 ###################################################################
 # Main Targets
 #
@@ -149,3 +157,27 @@ $(PROJECT).bit $(PROJECT).bin $(PROJECT).ltx $(PROJECT).xsa: $(PROJECT).runs/imp
 	cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bin rev/$(PROJECT)_rev$$COUNT.bin; \
 	if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi; \
 	if [ -e $(PROJECT).xsa ]; then cp -pv $(PROJECT).xsa rev/$(PROJECT)_rev$$COUNT.xsa; fi
+
+###################################################################
+# Simulation targets
+###################################################################
+
+gen_ip:
+	echo "open_project $(PROJECT).xpr" > gen_ip.tcl
+	echo "generate_target all [get_ips *]" >> gen_ip.tcl
+	vivado -mode batch -source gen_ip.tcl
+
+
+sim: $(PROJECT).xpr gen_ip
+	echo "open_project $(PROJECT).xpr" > run_sim.tcl
+	echo "add_files -fileset sim_1 $(TB_FILES)" >> run_sim.tcl
+	echo "set_property top $(SIM_TOP) [get_filesets sim_1]" >> run_sim.tcl
+	echo "update_compile_order -fileset sources_1" >> run_sim.tcl
+	echo "update_compile_order -fileset sim_1" >> run_sim.tcl
+	echo "launch_simulation" >> run_sim.tcl
+	echo "run all" >> run_sim.tcl
+	vivado -mode batch -source run_sim.tcl
+
+simclean:
+	-rm -rf xsim.dir *.wdb *.pb *.jou *.log *.vcd *.ltx
+	-rm -f defines_sim.v