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c33afac783
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rtl: implement axis UDP TX logic
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2026-04-10 15:37:19 +03:00 |
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26c627c988
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rtl: add udp ram data count signal logic
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2026-04-10 15:35:26 +03:00 |
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3544e3e2dc
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test: add sample top for axis loopback test
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2026-04-08 19:58:34 +03:00 |
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88db70ede8
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Merge pull request 'rtl: generator added' (#1) from dev/generator into master
Reviewed-on: #1
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2026-04-08 15:25:25 +03:00 |
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7a1c838de3
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rtl: generator added
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2026-04-08 15:13:57 +03:00 |
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100feb0ea1
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rtl: add constrains for axis eth fpga project
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2026-04-01 18:10:17 +03:00 |
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1310555b55
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chore: remove old file
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2026-04-01 18:08:50 +03:00 |
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c75443d170
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test: udp axis rx
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2026-04-01 18:04:01 +03:00 |
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3a58119960
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rtl: eth udp rx -> axis
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2026-04-01 18:03:47 +03:00 |
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221cb055f1
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rtl: sampler ready
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2026-04-01 11:46:59 +03:00 |
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0b9fb64193
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rtl: add axis eth rx prototype
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2026-04-01 11:44:46 +03:00 |
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7fedc36562
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tests: add sample project for minimal eth udp echo
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2026-03-31 15:08:12 +03:00 |
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ded2afc0db
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rtl: add sources for ethernet udp stack
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2026-03-31 12:53:16 +03:00 |
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aa1d45fe15
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infra: init project structure
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2026-03-25 16:17:55 +03:00 |
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