7 Commits

Author	SHA1	Message	Date
babintsev.lv	771225cd77	fix: post-implementation timing sim TB passed	2026-06-23 17:27:20 +03:00
Zer0Nu11	b38a693676	fix: timing. New DAC-ADC line code	2026-06-20 09:33:33 +03:00
Zer0Nu11	4fbecd5e30	upd: sync design log verbosity + optimal delay latency	2026-06-19 20:49:17 +03:00
Zer0Nu11	4923f01322	upd: TB automation, ... DA->AD delay line for signal integrity	2026-06-19 08:00:00 +03:00
babintsev.lv	c165d346a0	update: new synchronizer + half-baked TB	2026-06-10 16:40:53 +03:00
otroubi	c279f1158d	chore: clean code sync_top	2026-05-06 15:37:15 +03:00
otroubi	d26bc29507	rtl: debug synchronizer project	2026-05-06 14:40:33 +03:00