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d71655885c
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rtl: axil wrapper logic for controller
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2026-07-07 17:33:25 +03:00 |
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56e31a6cc6
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rtl: add window_size register
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2026-07-07 17:32:42 +03:00 |
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14a1df8bae
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rtl: controller module deconstruction
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2026-07-07 17:32:13 +03:00 |
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a6ade44b4d
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rtl: eth remove
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2026-07-03 16:28:08 +03:00 |
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14f4a5eb2a
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rtl: register map addition for DMA control
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2026-06-30 17:13:00 +03:00 |
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1eb21b5087
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rtl: controller adc_dac management register map
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2026-06-30 13:12:51 +03:00 |
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ecb2ed3b7f
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rtl: update controller to support different smp_num for adc/dac sides
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2026-05-08 15:59:20 +03:00 |
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c41b08f539
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fix: tricky packet check in ctrl
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2026-04-15 17:56:22 +03:00 |
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003750d972
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rtl: add controller first version
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2026-04-15 12:47:10 +03:00 |
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