baulin.fa/reflectometer_fpga_project
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Code Issues 4 Pull Requests Actions Packages Projects Releases Wiki Activity
16 Commits 14 Branches 0 Tags
c33afac783a7fd7e1baa3ce85b4bdc76ca1ede2c
Commit Graph
10 Commits
Author SHA1 Message Date
Phil c33afac783 rtl: implement axis UDP TX logic 2026-04-10 15:37:19 +03:00
Phil 26c627c988 rtl: add udp ram data count signal logic 2026-04-10 15:35:26 +03:00
Phil 3544e3e2dc test: add sample top for axis loopback test 2026-04-08 19:58:34 +03:00
Phil 100feb0ea1 rtl: add constrains for axis eth fpga project 2026-04-01 18:10:17 +03:00
Phil 1310555b55 chore: remove old file 2026-04-01 18:08:50 +03:00
Phil c75443d170 test: udp axis rx 2026-04-01 18:04:01 +03:00
Phil 3a58119960 rtl: eth udp rx -> axis 2026-04-01 18:03:47 +03:00
Phil 0b9fb64193 rtl: add axis eth rx prototype 2026-04-01 11:44:46 +03:00
Phil 7fedc36562 tests: add sample project for minimal eth udp echo 2026-03-31 15:08:12 +03:00
Phil ded2afc0db rtl: add sources for ethernet udp stack 2026-03-31 12:53:16 +03:00