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99a344d534
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debugging controller
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2026-07-08 17:53:25 +03:00 |
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e7c45101d1
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rst added
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2026-07-08 12:51:38 +03:00 |
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fc3134f2d8
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controller's changes
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2026-07-08 12:50:28 +03:00 |
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a82140feda
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add send signal to start a dma transaction
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2026-07-08 12:49:51 +03:00 |
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bafd084f0d
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rtl: dma descriptor and status transmitter logic
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2026-07-07 17:33:53 +03:00 |
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d71655885c
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rtl: axil wrapper logic for controller
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2026-07-07 17:33:25 +03:00 |
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56e31a6cc6
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rtl: add window_size register
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2026-07-07 17:32:42 +03:00 |
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14a1df8bae
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rtl: controller module deconstruction
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2026-07-07 17:32:13 +03:00 |
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a6ade44b4d
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rtl: eth remove
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2026-07-03 16:28:08 +03:00 |
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14f4a5eb2a
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rtl: register map addition for DMA control
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2026-06-30 17:13:00 +03:00 |
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1eb21b5087
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rtl: controller adc_dac management register map
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2026-06-30 13:12:51 +03:00 |
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1504569fb6
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debug: add waveconfigs
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2026-05-15 14:09:33 +03:00 |
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eacffd44b3
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docs: update ctrl readme
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2026-05-12 13:47:51 +03:00 |
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ecb2ed3b7f
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rtl: update controller to support different smp_num for adc/dac sides
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2026-05-08 15:59:20 +03:00 |
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597be48407
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docs: fix typos
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2026-04-15 18:56:46 +03:00 |
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f98051bc53
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docs: add controller READMEs
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2026-04-15 18:54:07 +03:00 |
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c41b08f539
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fix: tricky packet check in ctrl
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2026-04-15 17:56:22 +03:00 |
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dcf93fb307
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infra: add build Makefile for controller test project
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2026-04-15 13:31:28 +03:00 |
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23f82b9445
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tests: add controller tb
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2026-04-15 13:30:56 +03:00 |
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003750d972
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rtl: add controller first version
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2026-04-15 12:47:10 +03:00 |
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