 babintsev.lv
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489a2f3475
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Merge pull request 'add accum_done signal' (#16) from dev/accum_rework into dev/design
Reviewed-on: #16
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2026-07-28 14:11:28 +03:00 |
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 otroubi
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8fc8df6549
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add accum_done signal
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2026-07-28 14:09:26 +03:00 |
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otroubi
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bec1cee7a8
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transferring tests
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2026-07-28 14:07:40 +03:00 |
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otroubi
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ea9a6ad1e6
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accumulator's changes for dma integration
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2026-07-28 14:07:25 +03:00 |
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babintsev.lv
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5e3b0beef9
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Merge pull request 'dev/accum_rework' (#15) from dev/accum_rework into dev/design
Reviewed-on: #15
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2026-07-28 13:55:21 +03:00 |
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otroubi
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4acaea8d39
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Merge branch 'dev/design' into integration_new_controller
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2026-07-28 12:54:48 +03:00 |
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otroubi
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b731b1b75d
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transferring base tests for new controller design
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2026-07-28 12:51:42 +03:00 |
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otroubi
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32076b19f7
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transferring new controller design
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2026-07-28 12:51:05 +03:00 |
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otroubi
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c21c9d2ab5
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transferring test for controller dma ram connective
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2026-07-28 12:50:30 +03:00 |
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babintsev.lv
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56a0240f8e
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upd: sampler & TB complete
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2026-07-24 17:54:37 +03:00 |
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babintsev.lv
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81970c8b42
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upd: new TB, sampler refactor
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2026-07-21 16:54:06 +03:00 |
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babintsev.lv
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a528838741
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fix: patch for sampler
upd: reflectometer TB readaout data task
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2026-07-17 17:29:58 +03:00 |
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babintsev.lv
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04eb927a25
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fix: encoding issues, generator explicit default state
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2026-07-17 15:21:49 +03:00 |
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otroubi
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4240604f26
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sampler version with debugged OTR and debugged testbench
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2026-07-17 13:38:47 +03:00 |
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Zer0Nu11
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ef65dd1a97
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upd: DUT fully working. TB tests WIP
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2026-07-16 22:45:21 +03:00 |
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Zer0Nu11
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71b825ef2c
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upd:
fix axi-stream interface definition;
successful TB DUT launch
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2026-07-16 19:33:51 +03:00 |
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babintsev.lv
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d80f5ff31f
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fix: revert synchronizer changes (false changes) and sampler
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2026-07-14 13:02:55 +03:00 |
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babintsev.lv
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493d6844c0
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bug: TB tasks broken
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2026-07-10 18:52:52 +03:00 |
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babintsev.lv
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11a9e97691
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upd: reflectometer on axis bus iface + TB
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2026-07-10 18:46:48 +03:00 |
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babintsev.lv
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0ba25a3541
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add: vrtual DAC & ADC subsystem for TB
fix: makefile
upd: clocking wiz IP
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2026-07-10 14:15:49 +03:00 |
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babintsev.lv
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64f94a90e6
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add: virtual DAC (100%) and ADC (80%)
upd: makefile
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2026-07-08 17:47:56 +03:00 |
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babintsev.lv
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7665afd50b
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add: half-baked reflectometer TB
fix: constraints port names;
ready: reflectometer top module
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2026-07-08 14:56:51 +03:00 |
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Phil
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9f99021168
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infra: update gitignore for questa folder
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2026-07-07 17:47:21 +03:00 |
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Phil
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9c70029f3e
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infra: add questa makefile
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2026-07-07 17:47:03 +03:00 |
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Phil
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177c7d0bc2
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infra: update makefile
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2026-07-07 17:45:32 +03:00 |
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babintsev.lv
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c3275d5b46
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upd: ref
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2026-07-07 15:12:48 +03:00 |
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otroubi
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7b96fbddbf
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rtl: sampler modified
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2026-07-07 15:05:14 +03:00 |
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otroubi
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2282eb4e16
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Merge branch 'dev/design' of https://git.radiophotonics.ru/baulin.fa/reflectometer_fpga_project into dev/design
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2026-07-07 14:58:18 +03:00 |
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otroubi
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287d855df4
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rtl: sampler modified
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2026-07-07 14:47:34 +03:00 |
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Phil
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8e5b3929ac
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fix: missing state update
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2026-07-03 18:35:58 +03:00 |
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Phil
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df5469d538
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tests: add new tests for accum
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2026-07-03 18:03:04 +03:00 |
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babintsev.lv
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725826b07c
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add: new reflectometer top design (not ready)
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2026-07-03 16:32:48 +03:00 |
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Phil
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77526c44c2
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tests: update accum TB
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2026-07-02 11:49:31 +03:00 |
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Phil
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5010c42ae3
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rtl: update accum_top to use dynamic window_size
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2026-07-02 11:33:40 +03:00 |
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Phil
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f0542845b0
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rtl: rework out_axis_fifo
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2026-07-01 18:21:11 +03:00 |
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Phil
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46333c3601
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rtl: rework adder for dynamic window_size
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2026-07-01 18:06:56 +03:00 |
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Phil
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2a3796a60f
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rtl: update accum - change window size to signal
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2026-07-01 14:57:23 +03:00 |
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babintsev.lv
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d878bac42a
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upd: new top design WIP
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2026-06-30 17:21:49 +03:00 |
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Phil
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425c922690
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rtl: update accum to support window_size < 3
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2026-06-26 18:39:33 +03:00 |
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Phil
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02416a9621
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rtl: rework memory controls in accum
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2026-06-26 18:07:02 +03:00 |
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babintsev.lv
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771225cd77
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fix: post-implementation timing sim TB passed
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2026-06-23 17:27:20 +03:00 |
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Zer0Nu11
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b38a693676
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fix: timing. New DAC-ADC line code
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2026-06-20 09:33:33 +03:00 |
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Zer0Nu11
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789255fa04
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fix: add timing sim tricks
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2026-06-20 04:05:37 +03:00 |
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Zer0Nu11
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efcd6ef5d0
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upd:
fast fix of sampler OTR.
fix debug.xdc
Major add of full automated testing for TB.
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2026-06-20 03:07:05 +03:00 |
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Zer0Nu11
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4fbecd5e30
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upd: sync design log verbosity + optimal delay latency
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2026-06-19 20:49:17 +03:00 |
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 baulin.fa
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8f342eebd7
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Merge pull request 'dev/sw' (#14) from dev/sw into master
Reviewed-on: #14
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2026-06-19 13:20:58 +03:00 |
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baulin.fa
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646cbb4c31
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Merge branch 'master' into dev/sw
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2026-06-19 13:20:44 +03:00 |
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Zer0Nu11
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d71aaf1650
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fix: request/done protocol
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2026-06-19 08:05:03 +03:00 |
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Zer0Nu11
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035d02234c
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Merge branch 'dev/design' of https://git.radiophotonics.ru/baulin.fa/reflectometer_fpga_project into dev/design
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2026-06-19 08:00:44 +03:00 |
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Zer0Nu11
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4923f01322
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upd: TB automation,
DA->AD delay line for signal integrity
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2026-06-19 08:00:00 +03:00 |
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