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4240604f26
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sampler version with debugged OTR and debugged testbench
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2026-07-17 13:38:47 +03:00 |
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d80f5ff31f
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fix: revert synchronizer changes (false changes) and sampler
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2026-07-14 13:02:55 +03:00 |
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0ba25a3541
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add: vrtual DAC & ADC subsystem for TB
fix: makefile
upd: clocking wiz IP
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2026-07-10 14:15:49 +03:00 |
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7665afd50b
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add: half-baked reflectometer TB
fix: constraints port names;
ready: reflectometer top module
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2026-07-08 14:56:51 +03:00 |
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fd9280737d
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fix: refactoring
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2026-06-16 20:26:45 +03:00 |
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c165d346a0
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update: new synchronizer + half-baked TB
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2026-06-10 16:40:53 +03:00 |
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5b9469560a
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infra: update Makefile for synchronizer project
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2026-05-15 15:08:22 +03:00 |
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c279f1158d
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chore: clean code sync_top
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2026-05-06 15:37:15 +03:00 |
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4fc354955c
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rtl: debug synchronizer project makefile
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2026-05-06 14:41:26 +03:00 |
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57570bea00
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rtl: debug synchronizer project constraints
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2026-05-06 14:41:15 +03:00 |
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03d0abbe86
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rtl: debug synchronizer project testbench
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2026-05-06 14:40:53 +03:00 |
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d26bc29507
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rtl: debug synchronizer project
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2026-05-06 14:40:33 +03:00 |
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