baulin.fa/reflectometer_fpga_project
2
0
Fork 0
Code Issues 4 Pull Requests Actions Packages Projects Releases Wiki Activity

rtl: reconstruction of registers for dma

Browse Source
This commit is contained in:
otroubi
2026-07-20 17:28:48 +03:00
parent 076ad542b2
commit 1c2eccaf1d
6 changed files with 104 additions and 203 deletions
Download Patch File Download Diff File Expand all files Collapse all files

158
rtl/controller/src/controller_wrapper_axil.sv
View File

@ -1,23 +1,12 @@
import dma_reg_pkg::*;
module controller_wrapper_axil #(
parameter int unsigned ADDR_W = 16,
parameter int unsigned DATA_W = 32,
parameter int unsigned USER_W = 1,
parameter int unsigned DAC_DATA_WIDTH = 12,
parameter int unsigned AXI_ADDR_WIDTH = 16,
parameter int unsigned AXIS_ID_WIDTH = 8,
parameter int unsigned LEN_WIDTH = 20,
parameter int unsigned AXIS_USER_WIDTH = 1,
parameter int unsigned AXIS_DEST_WIDTH = 8,
parameter int unsigned TAG_WIDTH = 8,
parameter int unsigned READ_DESC_WIDTH = AXI_ADDR_WIDTH + LEN_WIDTH + TAG_WIDTH + AXIS_ID_WIDTH + AXIS_DEST_WIDTH + AXIS_USER_WIDTH,
parameter int unsigned WRITE_DESC_WIDTH = AXI_ADDR_WIDTH + LEN_WIDTH + TAG_WIDTH,
parameter int unsigned READ_STATUS_WIDTH = TAG_WIDTH + 4,
parameter int unsigned WRITE_STATUS_WIDTH = LEN_WIDTH + TAG_WIDTH + AXIS_ID_WIDTH + AXIS_DEST_WIDTH + AXIS_USER_WIDTH + 4
parameter int unsigned DAC_DATA_WIDTH = 12
)
(
input logic ctrl_clk,
@ -159,28 +148,28 @@ parameter int unsigned WRITE_STATUS_WIDTH = LEN_WIDTH + TAG_WIDTH + AXIS_ID_WIDT
// CONTROLLER DMA
logic [READ_DESC_WIDTH-1:0] desc_read_cmd, desc_read_cmd_out;
assign desc_read_cmd = { desc_read_config[TAG_WIDTH+AXIS_ID_WIDTH+AXIS_DEST_WIDTH+AXIS_USER_WIDTH-1:0], desc_read_len[LEN_WIDTH-1:0], desc_read_addr[AXI_ADDR_WIDTH-1:0]};
dma_read_desc_t desc_read_cmd, desc_read_cmd_out;
assign desc_read_cmd.addr = desc_read_addr;
assign desc_read_cmd.len = desc_read_len;
assign desc_read_cmd.tag = desc_read_config[TAG_WIDTH-1:0];
assign desc_read_cmd.id = desc_read_config[TAG_WIDTH +: AXIS_ID_WIDTH];
assign desc_read_cmd.dest = desc_read_config[TAG_WIDTH+AXIS_ID_WIDTH +: AXIS_DEST_WIDTH];
assign desc_read_cmd.user = desc_read_config[TAG_WIDTH+AXIS_ID_WIDTH+AXIS_DEST_WIDTH +: AXIS_USER_WIDTH];
logic [WRITE_DESC_WIDTH-1:0] desc_write_cmd, desc_write_cmd_out;
assign desc_write_cmd = {desc_write_len_and_tag[LEN_WIDTH+TAG_WIDTH-1:0],desc_write_addr[AXI_ADDR_WIDTH-1:0]};
dma_write_desc_t desc_write_cmd, desc_write_cmd_out;
assign desc_write_cmd.addr = desc_write_addr;
assign desc_write_cmd.len = desc_write_len_and_tag[LEN_WIDTH-1:0];
assign desc_write_cmd.tag = desc_write_len_and_tag[LEN_WIDTH +: TAG_WIDTH];
logic [READ_STATUS_WIDTH-1:0] status_read_cmd, status_read_cmd_in;
assign status_read = status_read_cmd[READ_STATUS_WIDTH-1:0];
dma_read_status_t status_read_cmd, status_read_cmd_in;
assign status_read = { status_read_cmd.error, status_read_cmd.tag};
logic [WRITE_STATUS_WIDTH-1:0] status_write_cmd, status_write_cmd_in;
assign {status_write_config[TAG_WIDTH+AXIS_ID_WIDTH+AXIS_DEST_WIDTH+AXIS_USER_WIDTH+3:0], status_write_len[LEN_WIDTH-1:0]} = status_write_cmd;
dma_write_status_t status_write_cmd, status_write_cmd_in;
assign status_write_len = status_write_cmd.len;
assign status_write_config = { status_write_cmd.error, status_write_cmd.user,
status_write_cmd.dest, status_write_cmd.id, status_write_cmd.tag};
logic ready_desc_read, ready_desc_write, ready_status_read, ready_status_write;
logic valid_desc_read, valid_desc_write, valid_status_read, valid_status_write;
dma_controller
#(
.READ_DESC_WIDTH(READ_DESC_WIDTH),
.WRITE_DESC_WIDTH(WRITE_DESC_WIDTH),
.READ_STATUS_WIDTH(READ_STATUS_WIDTH),
.WRITE_STATUS_WIDTH(WRITE_STATUS_WIDTH)
) dma_controller_inst
dma_controller dma_controller_inst
(
.dma_clk(ctrl_clk),
.rst_n(rst_n),
@ -200,15 +189,15 @@ parameter int unsigned WRITE_STATUS_WIDTH = LEN_WIDTH + TAG_WIDTH + AXIS_ID_WIDT
.status_read_cmd_in(status_read_cmd_in),
.status_write_cmd_in(status_write_cmd_in),
.ready_desc_read(ready_desc_read),
.ready_desc_write(ready_desc_write),
.ready_status_read(ready_status_read),
.ready_status_write(ready_status_write),
.ready_desc_read(m_axis_desc_read.resp.ready),
.ready_desc_write(m_axis_desc_write.resp.ready),
.ready_status_read(s_axis_status_read.resp.ready),
.ready_status_write(s_axis_status_write.resp.ready),
.valid_desc_read(valid_desc_read),
.valid_desc_write(valid_desc_write),
.valid_status_read(valid_status_read),
.valid_status_write(valid_status_write),
.valid_desc_read(m_axis_desc_read.req.t.valid),
.valid_desc_write(m_axis_desc_write.req.t.valid),
.valid_status_read(s_axis_status_read.req.t.valid),
.valid_status_write(s_axis_status_write.req.t.valid),
.desc_read_dma_busy(desc_read_dma_busy),
.desc_write_dma_busy(desc_write_dma_busy),
@ -221,89 +210,12 @@ parameter int unsigned WRITE_STATUS_WIDTH = LEN_WIDTH + TAG_WIDTH + AXIS_ID_WIDT
.status_write_dma_hs(status_write_dma_hs)
);
// AXIS LOGIC TRANSFORMATION
axis_if_to_flat
#(
.DATA_W(READ_STATUS_WIDTH),
.ID_W(8),
.DEST_W(8),
.USER_W(1)
) axis_if_to_flat_status_read
(
.m_axis_tdata(status_read_cmd_in),
.m_axis_tkeep(),
.m_axis_tstrb(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.m_axis_tvalid(valid_status_read),
.m_axis_tready(ready_status_read),
axis_defaults_master defaults_rd (.axis(m_axis_desc_read));
axis_defaults_master defaults_wr (.axis(m_axis_desc_write));
.s_axis(s_axis_status_read)
);
axis_if_to_flat
#(
.DATA_W(WRITE_STATUS_WIDTH),
.ID_W(8),
.DEST_W(8),
.USER_W(1)
) axis_if_to_flat_status_write
(
.m_axis_tdata(status_write_cmd_in),
.m_axis_tkeep(),
.m_axis_tstrb(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.m_axis_tvalid(valid_status_write),
.m_axis_tready(ready_status_write),
.s_axis(s_axis_status_write)
);
axis_flat_to_if
#(
.DATA_W(READ_DESC_WIDTH),
.ID_W(8),
.DEST_W(8),
.USER_W(1)
) axis_flat_to_if_desc_read
(
.m_axis(m_axis_desc_read),
.s_axis_tdata(desc_read_cmd_out),
.s_axis_tkeep(),
.s_axis_tstrb(),
.s_axis_tlast(),
.s_axis_tid(),
.s_axis_tdest(),
.s_axis_tuser(),
.s_axis_tvalid(valid_desc_read),
.s_axis_tready(ready_desc_read)
);
axis_flat_to_if
#(
.DATA_W(WRITE_DESC_WIDTH),
.ID_W(8),
.DEST_W(8),
.USER_W(1)
) axis_flat_to_if_desc_write
(
.m_axis(m_axis_desc_write),
.s_axis_tdata(desc_write_cmd_out),
.s_axis_tkeep(),
.s_axis_tstrb(),
.s_axis_tlast(),
.s_axis_tid(),
.s_axis_tdest(),
.s_axis_tuser(),
.s_axis_tvalid(valid_desc_write),
.s_axis_tready(ready_desc_write)
);
assign m_axis_desc_read.req.t.data = desc_read_cmd_out;
assign m_axis_desc_write.req.t.data = desc_write_cmd_out;
assign status_read_cmd_in = s_axis_status_read.req.t.data;
assign status_write_cmd_in = s_axis_status_write.req.t.data;
endmodule