From 1c2eccaf1daee184749843b1bd9897d27712f652 Mon Sep 17 00:00:00 2001 From: otroubi Date: Mon, 20 Jul 2026 17:28:48 +0300 Subject: [PATCH] rtl: reconstruction of registers for dma --- rtl/controller/src/axis_defaults_helper.sv | 13 ++ rtl/controller/src/axis_flat_to_if.sv | 30 ---- rtl/controller/src/axis_if_to_flat.sv | 30 ---- rtl/controller/src/controller_wrapper_axil.sv | 158 ++++-------------- rtl/controller/src/dma_controller.sv | 34 ++-- rtl/controller/src/dma_reg_pkg.sv | 42 +++++ 6 files changed, 104 insertions(+), 203 deletions(-) create mode 100644 rtl/controller/src/axis_defaults_helper.sv delete mode 100644 rtl/controller/src/axis_flat_to_if.sv delete mode 100644 rtl/controller/src/axis_if_to_flat.sv create mode 100644 rtl/controller/src/dma_reg_pkg.sv diff --git a/rtl/controller/src/axis_defaults_helper.sv b/rtl/controller/src/axis_defaults_helper.sv new file mode 100644 index 0000000..dee900a --- /dev/null +++ b/rtl/controller/src/axis_defaults_helper.sv @@ -0,0 +1,13 @@ +module axis_defaults_master +( + axis_if.master axis +); + +assign axis.req.t.keep = '1; +assign axis.req.t.strb = '1; +assign axis.req.t.last = 1'b1; +assign axis.req.t.id = '0; +assign axis.req.t.dest = '0; +assign axis.req.t.user = '0; + +endmodule \ No newline at end of file diff --git a/rtl/controller/src/axis_flat_to_if.sv b/rtl/controller/src/axis_flat_to_if.sv deleted file mode 100644 index 569e0e2..0000000 --- a/rtl/controller/src/axis_flat_to_if.sv +++ /dev/null @@ -1,30 +0,0 @@ -module axis_flat_to_if #( - parameter int unsigned DATA_W = 64, - parameter int unsigned KEEP_W = DATA_W / 8, - parameter int unsigned ID_W = 8, - parameter int unsigned DEST_W = 8, - parameter int unsigned USER_W = 1 -)( - input logic [DATA_W-1:0] s_axis_tdata, - input logic [KEEP_W-1:0] s_axis_tkeep, - input logic [KEEP_W-1:0] s_axis_tstrb, - input logic s_axis_tlast, - input logic [ID_W-1:0] s_axis_tid, - input logic [DEST_W-1:0] s_axis_tdest, - input logic [USER_W-1:0] s_axis_tuser, - input logic s_axis_tvalid, - output logic s_axis_tready, - - axis_if.master m_axis -); - assign m_axis.req.t.data = s_axis_tdata; - assign m_axis.req.t.keep = s_axis_tkeep; - assign m_axis.req.t.strb = s_axis_tstrb; - assign m_axis.req.t.last = s_axis_tlast; - assign m_axis.req.t.id = s_axis_tid; - assign m_axis.req.t.dest = s_axis_tdest; - assign m_axis.req.t.user = s_axis_tuser; - assign m_axis.req.t.valid = s_axis_tvalid; - - assign s_axis_tready = m_axis.resp.ready; -endmodule : axis_flat_to_if diff --git a/rtl/controller/src/axis_if_to_flat.sv b/rtl/controller/src/axis_if_to_flat.sv deleted file mode 100644 index e5ab45e..0000000 --- a/rtl/controller/src/axis_if_to_flat.sv +++ /dev/null @@ -1,30 +0,0 @@ -module axis_if_to_flat #( - parameter int unsigned DATA_W = 64, - parameter int unsigned KEEP_W = DATA_W / 8, - parameter int unsigned ID_W = 8, - parameter int unsigned DEST_W = 8, - parameter int unsigned USER_W = 1 -)( - axis_if.slave s_axis, - - output logic [DATA_W-1:0] m_axis_tdata, - output logic [KEEP_W-1:0] m_axis_tkeep, - output logic [KEEP_W-1:0] m_axis_tstrb, - output logic m_axis_tlast, - output logic [ID_W-1:0] m_axis_tid, - output logic [DEST_W-1:0] m_axis_tdest, - output logic [USER_W-1:0] m_axis_tuser, - output logic m_axis_tvalid, - input logic m_axis_tready -); - assign m_axis_tdata = s_axis.req.t.data; - assign m_axis_tkeep = s_axis.req.t.keep; - assign m_axis_tstrb = s_axis.req.t.strb; - assign m_axis_tlast = s_axis.req.t.last; - assign m_axis_tid = s_axis.req.t.id; - assign m_axis_tdest = s_axis.req.t.dest; - assign m_axis_tuser = s_axis.req.t.user; - assign m_axis_tvalid = s_axis.req.t.valid; - - assign s_axis.resp.ready = m_axis_tready; -endmodule : axis_if_to_flat diff --git a/rtl/controller/src/controller_wrapper_axil.sv b/rtl/controller/src/controller_wrapper_axil.sv index c59ec4f..f2745ba 100644 --- a/rtl/controller/src/controller_wrapper_axil.sv +++ b/rtl/controller/src/controller_wrapper_axil.sv @@ -1,23 +1,12 @@ +import dma_reg_pkg::*; + module controller_wrapper_axil #( parameter int unsigned ADDR_W = 16, parameter int unsigned DATA_W = 32, parameter int unsigned USER_W = 1, -parameter int unsigned DAC_DATA_WIDTH = 12, - -parameter int unsigned AXI_ADDR_WIDTH = 16, -parameter int unsigned AXIS_ID_WIDTH = 8, -parameter int unsigned LEN_WIDTH = 20, -parameter int unsigned AXIS_USER_WIDTH = 1, -parameter int unsigned AXIS_DEST_WIDTH = 8, -parameter int unsigned TAG_WIDTH = 8, - -parameter int unsigned READ_DESC_WIDTH = AXI_ADDR_WIDTH + LEN_WIDTH + TAG_WIDTH + AXIS_ID_WIDTH + AXIS_DEST_WIDTH + AXIS_USER_WIDTH, -parameter int unsigned WRITE_DESC_WIDTH = AXI_ADDR_WIDTH + LEN_WIDTH + TAG_WIDTH, - -parameter int unsigned READ_STATUS_WIDTH = TAG_WIDTH + 4, -parameter int unsigned WRITE_STATUS_WIDTH = LEN_WIDTH + TAG_WIDTH + AXIS_ID_WIDTH + AXIS_DEST_WIDTH + AXIS_USER_WIDTH + 4 +parameter int unsigned DAC_DATA_WIDTH = 12 ) ( input logic ctrl_clk, @@ -159,28 +148,28 @@ parameter int unsigned WRITE_STATUS_WIDTH = LEN_WIDTH + TAG_WIDTH + AXIS_ID_WIDT // CONTROLLER DMA - logic [READ_DESC_WIDTH-1:0] desc_read_cmd, desc_read_cmd_out; - assign desc_read_cmd = { desc_read_config[TAG_WIDTH+AXIS_ID_WIDTH+AXIS_DEST_WIDTH+AXIS_USER_WIDTH-1:0], desc_read_len[LEN_WIDTH-1:0], desc_read_addr[AXI_ADDR_WIDTH-1:0]}; + dma_read_desc_t desc_read_cmd, desc_read_cmd_out; + assign desc_read_cmd.addr = desc_read_addr; + assign desc_read_cmd.len = desc_read_len; + assign desc_read_cmd.tag = desc_read_config[TAG_WIDTH-1:0]; + assign desc_read_cmd.id = desc_read_config[TAG_WIDTH +: AXIS_ID_WIDTH]; + assign desc_read_cmd.dest = desc_read_config[TAG_WIDTH+AXIS_ID_WIDTH +: AXIS_DEST_WIDTH]; + assign desc_read_cmd.user = desc_read_config[TAG_WIDTH+AXIS_ID_WIDTH+AXIS_DEST_WIDTH +: AXIS_USER_WIDTH]; - logic [WRITE_DESC_WIDTH-1:0] desc_write_cmd, desc_write_cmd_out; - assign desc_write_cmd = {desc_write_len_and_tag[LEN_WIDTH+TAG_WIDTH-1:0],desc_write_addr[AXI_ADDR_WIDTH-1:0]}; + dma_write_desc_t desc_write_cmd, desc_write_cmd_out; + assign desc_write_cmd.addr = desc_write_addr; + assign desc_write_cmd.len = desc_write_len_and_tag[LEN_WIDTH-1:0]; + assign desc_write_cmd.tag = desc_write_len_and_tag[LEN_WIDTH +: TAG_WIDTH]; - logic [READ_STATUS_WIDTH-1:0] status_read_cmd, status_read_cmd_in; - assign status_read = status_read_cmd[READ_STATUS_WIDTH-1:0]; + dma_read_status_t status_read_cmd, status_read_cmd_in; + assign status_read = { status_read_cmd.error, status_read_cmd.tag}; - logic [WRITE_STATUS_WIDTH-1:0] status_write_cmd, status_write_cmd_in; - assign {status_write_config[TAG_WIDTH+AXIS_ID_WIDTH+AXIS_DEST_WIDTH+AXIS_USER_WIDTH+3:0], status_write_len[LEN_WIDTH-1:0]} = status_write_cmd; + dma_write_status_t status_write_cmd, status_write_cmd_in; + assign status_write_len = status_write_cmd.len; + assign status_write_config = { status_write_cmd.error, status_write_cmd.user, + status_write_cmd.dest, status_write_cmd.id, status_write_cmd.tag}; - logic ready_desc_read, ready_desc_write, ready_status_read, ready_status_write; - logic valid_desc_read, valid_desc_write, valid_status_read, valid_status_write; - - dma_controller - #( - .READ_DESC_WIDTH(READ_DESC_WIDTH), - .WRITE_DESC_WIDTH(WRITE_DESC_WIDTH), - .READ_STATUS_WIDTH(READ_STATUS_WIDTH), - .WRITE_STATUS_WIDTH(WRITE_STATUS_WIDTH) - ) dma_controller_inst + dma_controller dma_controller_inst ( .dma_clk(ctrl_clk), .rst_n(rst_n), @@ -200,15 +189,15 @@ parameter int unsigned WRITE_STATUS_WIDTH = LEN_WIDTH + TAG_WIDTH + AXIS_ID_WIDT .status_read_cmd_in(status_read_cmd_in), .status_write_cmd_in(status_write_cmd_in), - .ready_desc_read(ready_desc_read), - .ready_desc_write(ready_desc_write), - .ready_status_read(ready_status_read), - .ready_status_write(ready_status_write), + .ready_desc_read(m_axis_desc_read.resp.ready), + .ready_desc_write(m_axis_desc_write.resp.ready), + .ready_status_read(s_axis_status_read.resp.ready), + .ready_status_write(s_axis_status_write.resp.ready), - .valid_desc_read(valid_desc_read), - .valid_desc_write(valid_desc_write), - .valid_status_read(valid_status_read), - .valid_status_write(valid_status_write), + .valid_desc_read(m_axis_desc_read.req.t.valid), + .valid_desc_write(m_axis_desc_write.req.t.valid), + .valid_status_read(s_axis_status_read.req.t.valid), + .valid_status_write(s_axis_status_write.req.t.valid), .desc_read_dma_busy(desc_read_dma_busy), .desc_write_dma_busy(desc_write_dma_busy), @@ -221,89 +210,12 @@ parameter int unsigned WRITE_STATUS_WIDTH = LEN_WIDTH + TAG_WIDTH + AXIS_ID_WIDT .status_write_dma_hs(status_write_dma_hs) ); - // AXIS LOGIC TRANSFORMATION - axis_if_to_flat - #( - .DATA_W(READ_STATUS_WIDTH), - .ID_W(8), - .DEST_W(8), - .USER_W(1) - ) axis_if_to_flat_status_read - ( - .m_axis_tdata(status_read_cmd_in), - .m_axis_tkeep(), - .m_axis_tstrb(), - .m_axis_tlast(), - .m_axis_tid(), - .m_axis_tdest(), - .m_axis_tuser(), - .m_axis_tvalid(valid_status_read), - .m_axis_tready(ready_status_read), + axis_defaults_master defaults_rd (.axis(m_axis_desc_read)); + axis_defaults_master defaults_wr (.axis(m_axis_desc_write)); - .s_axis(s_axis_status_read) - ); - - axis_if_to_flat - #( - .DATA_W(WRITE_STATUS_WIDTH), - .ID_W(8), - .DEST_W(8), - .USER_W(1) - ) axis_if_to_flat_status_write - ( - .m_axis_tdata(status_write_cmd_in), - .m_axis_tkeep(), - .m_axis_tstrb(), - .m_axis_tlast(), - .m_axis_tid(), - .m_axis_tdest(), - .m_axis_tuser(), - .m_axis_tvalid(valid_status_write), - .m_axis_tready(ready_status_write), - - .s_axis(s_axis_status_write) - ); - - axis_flat_to_if - #( - .DATA_W(READ_DESC_WIDTH), - .ID_W(8), - .DEST_W(8), - .USER_W(1) - ) axis_flat_to_if_desc_read - ( - .m_axis(m_axis_desc_read), - - .s_axis_tdata(desc_read_cmd_out), - .s_axis_tkeep(), - .s_axis_tstrb(), - .s_axis_tlast(), - .s_axis_tid(), - .s_axis_tdest(), - .s_axis_tuser(), - .s_axis_tvalid(valid_desc_read), - .s_axis_tready(ready_desc_read) - ); - - axis_flat_to_if - #( - .DATA_W(WRITE_DESC_WIDTH), - .ID_W(8), - .DEST_W(8), - .USER_W(1) - ) axis_flat_to_if_desc_write - ( - .m_axis(m_axis_desc_write), - - .s_axis_tdata(desc_write_cmd_out), - .s_axis_tkeep(), - .s_axis_tstrb(), - .s_axis_tlast(), - .s_axis_tid(), - .s_axis_tdest(), - .s_axis_tuser(), - .s_axis_tvalid(valid_desc_write), - .s_axis_tready(ready_desc_write) - ); + assign m_axis_desc_read.req.t.data = desc_read_cmd_out; + assign m_axis_desc_write.req.t.data = desc_write_cmd_out; + assign status_read_cmd_in = s_axis_status_read.req.t.data; + assign status_write_cmd_in = s_axis_status_write.req.t.data; endmodule \ No newline at end of file diff --git a/rtl/controller/src/dma_controller.sv b/rtl/controller/src/dma_controller.sv index c34c6ad..a07f4a4 100644 --- a/rtl/controller/src/dma_controller.sv +++ b/rtl/controller/src/dma_controller.sv @@ -1,11 +1,6 @@ -module dma_controller -#( -parameter int unsigned READ_DESC_WIDTH = 128, -parameter int unsigned WRITE_DESC_WIDTH = 128, +import dma_reg_pkg::*; -parameter int unsigned READ_STATUS_WIDTH = 128, -parameter int unsigned WRITE_STATUS_WIDTH = 128 -) +module dma_controller ( input dma_clk, input rst_n, @@ -20,14 +15,14 @@ input logic ready_desc_write, output logic ready_status_read, output logic ready_status_write, -input logic [READ_DESC_WIDTH-1:0] desc_read_cmd, -input logic [WRITE_DESC_WIDTH-1:0] desc_write_cmd, +input dma_read_desc_t desc_read_cmd, +input dma_write_desc_t desc_write_cmd, -output logic [READ_STATUS_WIDTH-1:0] status_read_cmd, -output logic [WRITE_STATUS_WIDTH-1:0] status_write_cmd, +output dma_read_status_t status_read_cmd, +output dma_write_status_t status_write_cmd, -input logic [READ_STATUS_WIDTH-1:0] status_read_cmd_in, -input logic [WRITE_STATUS_WIDTH-1:0] status_write_cmd_in, +input dma_read_status_t status_read_cmd_in, +input dma_write_status_t status_write_cmd_in, output logic desc_read_dma_busy, output logic desc_write_dma_busy, @@ -45,14 +40,13 @@ output logic valid_desc_write, input logic valid_status_read, input logic valid_status_write, -output logic [READ_DESC_WIDTH-1:0] desc_read_cmd_out, -output logic [WRITE_DESC_WIDTH-1:0] desc_write_cmd_out - +output dma_read_desc_t desc_read_cmd_out, +output dma_write_desc_t desc_write_cmd_out ); shaper_axis_desc #( - .DATA_WIDTH(READ_DESC_WIDTH) + .DATA_WIDTH($bits(dma_read_desc_t)) ) shaper_axis_desc_read ( .clk(dma_clk), @@ -68,7 +62,7 @@ shaper_axis_desc shaper_axis_desc #( - .DATA_WIDTH(WRITE_DESC_WIDTH) + .DATA_WIDTH($bits(dma_write_desc_t)) ) shaper_axis_desc_write ( .clk(dma_clk), @@ -84,7 +78,7 @@ shaper_axis_desc shaper_axis_status #( - .DATA_WIDTH(READ_STATUS_WIDTH) + .DATA_WIDTH($bits(dma_read_status_t)) ) shaper_axis_status_read ( .clk(dma_clk), @@ -100,7 +94,7 @@ shaper_axis_status shaper_axis_status #( - .DATA_WIDTH(WRITE_STATUS_WIDTH) + .DATA_WIDTH($bits(dma_write_status_t)) ) shaper_axis_status_write ( .clk(dma_clk), diff --git a/rtl/controller/src/dma_reg_pkg.sv b/rtl/controller/src/dma_reg_pkg.sv new file mode 100644 index 0000000..2daacd9 --- /dev/null +++ b/rtl/controller/src/dma_reg_pkg.sv @@ -0,0 +1,42 @@ +package dma_reg_pkg; + parameter int unsigned AXI_ADDR_WIDTH = 16; + parameter int unsigned LEN_WIDTH = 20; + parameter int unsigned TAG_WIDTH = 8; + parameter int unsigned AXIS_ID_WIDTH = 8; + parameter int unsigned AXIS_DEST_WIDTH = 8; + parameter int unsigned AXIS_USER_WIDTH = 1; + + typedef struct packed { + logic [AXIS_USER_WIDTH-1:0] user; + logic [AXIS_DEST_WIDTH-1:0] dest; + logic [AXIS_ID_WIDTH-1:0] id; + logic [TAG_WIDTH-1:0] tag; + logic [LEN_WIDTH-1:0] len; + logic [AXI_ADDR_WIDTH-1:0] addr; + + } dma_read_desc_t; + + typedef struct packed { + logic [TAG_WIDTH-1:0] tag; + logic [LEN_WIDTH-1:0] len; + logic [AXI_ADDR_WIDTH-1:0] addr; + + } dma_write_desc_t; + + typedef struct packed { + logic [3:0] error; + logic [TAG_WIDTH-1:0] tag; + + } dma_read_status_t; + +typedef struct packed { + logic [3:0] error; + logic [AXIS_USER_WIDTH-1:0] user; + logic [AXIS_DEST_WIDTH-1:0] dest; + logic [AXIS_ID_WIDTH-1:0] id; + logic [TAG_WIDTH-1:0] tag; + logic [LEN_WIDTH-1:0] len; + + } dma_write_status_t; + +endpackage \ No newline at end of file