infra: add verilog-ethernet as a submodule

2026-03-25 16:28:35 +03:00
parent aa1d45fe15
commit 0be4f35152
2 changed files with 4 additions and 0 deletions
--- a/.gitmodules
+++ b/.gitmodules
@ -0,0 +1,3 @@
+[submodule "external/verilog-ethernet"]
+	path = external/verilog-ethernet
+	url = https://github.com/alexforencich/verilog-ethernet.git
--- a/external/verilog-ethernet
+++ b/external/verilog-ethernet