 ChTheo
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f20ad2301b
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fixed relative phases in Mach-Zander and ADC clocks. ADC clock delayed to move ADC sampling time far from the start of modulated period. Now there is 400 ns time reserve.
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2025-04-18 17:05:26 +03:00 |
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ChTheo
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9974606734
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partially solved issue with random modulator and ADC clock stopping at the end of ЛЧМ. Done: when we want to stop clocks -- enable IRQ on sloewr clock (TIM11). In IRQ switches TIM4, TIM11 to one-pulse mode, disables IRQ. When we starting these timers th next time -- we resets their counters, one-pulse mode disables.
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2025-04-15 21:29:24 +03:00 |
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ChTheo
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0829fd0983
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fixed modulation and ADC clocks initial phase to 0. (by TIM->CNT=0)
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2025-04-15 19:00:22 +03:00 |
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ChTheo
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5756dfe749
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configured ADC sync signals at fastest possible frequency: 1.75 MHz
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2025-04-07 19:01:57 +03:00 |
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ChTheo
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61bb0c41db
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configured external ADC sync and Mach-Zander modulation clocks at 2 and 1 MHz respectively
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2025-04-07 17:29:51 +03:00 |
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