82 lines
2.8 KiB
Makefile
82 lines
2.8 KiB
Makefile
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TOPLEVEL_LANG = verilog
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SIM ?= verilator
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PWD := $(shell pwd)
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PROJECT_ROOT ?= $(abspath $(PWD)/../../..)
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AXI_IF_RTL_DIR ?= $(PROJECT_ROOT)/axi/rtl
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FORENCICH_AXI_RTL_DIR ?= $(PROJECT_ROOT)/external/verilog-axi/rtl
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TB_DIR ?= $(PWD)
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TOPLEVEL = tb_axi_dma_wrapper
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MODULE = test_axi_dma_wrapper
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export PYTHONPATH := $(TB_DIR):$(PYTHONPATH)
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# Parameters for a quick make-based run. The pytest entrypoint can be used for
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# wider parameter sweeps.
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AXI_DATA_WIDTH ?= 32
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AXI_ADDR_WIDTH ?= 16
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AXI_ID_WIDTH ?= 8
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AXI_USER_WIDTH ?= 1
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AXI_MAX_BURST_LEN ?= 16
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ENABLE_UNALIGNED ?= 0
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AXI_STRB_WIDTH := $(shell expr $(AXI_DATA_WIDTH) / 8)
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AXIS_DATA_WIDTH ?= $(AXI_DATA_WIDTH)
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AXIS_KEEP_WIDTH := $(shell expr $(AXIS_DATA_WIDTH) / 8)
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AXIS_KEEP_ENABLE := $(shell [ $(AXIS_DATA_WIDTH) -gt 8 ] && echo 1 || echo 0)
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VERILOG_SOURCES += $(AXI_IF_RTL_DIR)/axi_pkg.sv
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VERILOG_SOURCES += $(AXI_IF_RTL_DIR)/axi_if.sv
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VERILOG_SOURCES += $(AXI_IF_RTL_DIR)/axis_if.sv
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VERILOG_SOURCES += $(AXI_IF_RTL_DIR)/axi4_flat_to_if.sv
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VERILOG_SOURCES += $(AXI_IF_RTL_DIR)/axi4_if_to_flat.sv
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VERILOG_SOURCES += $(AXI_IF_RTL_DIR)/axis_flat_to_if.sv
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VERILOG_SOURCES += $(AXI_IF_RTL_DIR)/axis_if_to_flat.sv
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VERILOG_SOURCES += $(FORENCICH_AXI_RTL_DIR)/axi_dma.v
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VERILOG_SOURCES += $(FORENCICH_AXI_RTL_DIR)/axi_dma_rd.v
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VERILOG_SOURCES += $(FORENCICH_AXI_RTL_DIR)/axi_dma_wr.v
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VERILOG_SOURCES += $(AXI_IF_RTL_DIR)/axi_dma_if_wrapper.sv
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VERILOG_SOURCES += $(TB_DIR)/tb_axi_dma_wrapper.sv
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COMPILE_ARGS += -I$(AXI_IF_RTL_DIR)
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COMPILE_ARGS += -I$(WRAPPER_RTL_DIR)
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COMPILE_ARGS += -I$(FORENCICH_AXI_RTL_DIR)
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# took this from forencich to silence 100+ warnings
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COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH -Wno-CASEINCOMPLETE
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ifeq ($(SIM),verilator)
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EXTRA_ARGS += --trace
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EXTRA_ARGS += --trace-structs
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EXTRA_ARGS += -GAXI_DATA_WIDTH=$(AXI_DATA_WIDTH)
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EXTRA_ARGS += -GAXI_ADDR_WIDTH=$(AXI_ADDR_WIDTH)
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EXTRA_ARGS += -GAXI_STRB_WIDTH=$(AXI_STRB_WIDTH)
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EXTRA_ARGS += -GAXI_ID_WIDTH=$(AXI_ID_WIDTH)
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EXTRA_ARGS += -GAXI_USER_WIDTH=$(AXI_USER_WIDTH)
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EXTRA_ARGS += -GAXI_MAX_BURST_LEN=$(AXI_MAX_BURST_LEN)
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EXTRA_ARGS += -GAXIS_DATA_WIDTH=$(AXIS_DATA_WIDTH)
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EXTRA_ARGS += -GAXIS_KEEP_ENABLE=$(AXIS_KEEP_ENABLE)
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EXTRA_ARGS += -GAXIS_KEEP_WIDTH=$(AXIS_KEEP_WIDTH)
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EXTRA_ARGS += -GAXIS_LAST_ENABLE=1
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EXTRA_ARGS += -GAXIS_ID_ENABLE=1
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EXTRA_ARGS += -GAXIS_ID_WIDTH=8
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EXTRA_ARGS += -GAXIS_DEST_ENABLE=0
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EXTRA_ARGS += -GAXIS_DEST_WIDTH=8
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EXTRA_ARGS += -GAXIS_USER_ENABLE=1
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EXTRA_ARGS += -GAXIS_USER_WIDTH=1
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EXTRA_ARGS += -GLEN_WIDTH=20
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EXTRA_ARGS += -GTAG_WIDTH=8
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EXTRA_ARGS += -GENABLE_SG=0
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EXTRA_ARGS += -GENABLE_UNALIGNED=$(ENABLE_UNALIGNED)
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endif
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export PARAM_AXI_DATA_WIDTH=$(AXI_DATA_WIDTH)
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export PARAM_ENABLE_UNALIGNED=$(ENABLE_UNALIGNED)
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include $(shell cocotb-config --makefiles)/Makefile.sim
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