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rtl_libs
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Phil
c18233e16a
chore: add some notes
2026-06-09 18:11:27 +03:00
axi
chore: add some notes
2026-06-09 18:11:27 +03:00
external
infra: add forencich repository as a submodule
2026-06-09 17:37:55 +03:00
.gitignore
infra: update gitignore
2026-06-09 15:30:07 +03:00
.gitmodules
infra: add forencich repository as a submodule
2026-06-09 17:37:55 +03:00
README.md
chore: first commit
2026-05-28 16:40:47 +03:00
README.md
RTL Libs
AXI Defines
Description
universal components for FPGA development
Readme
98
KiB
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SystemVerilog
100%
