baulin.fa/rtl_libs
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Phil 7bafa8534f rtl: add write desc converters
2026-06-11 15:47:59 +03:00
axi
rtl: add write desc converters
2026-06-11 15:47:59 +03:00
external
infra: add forencich repository as a submodule
2026-06-09 17:37:55 +03:00
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README.md
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README.md

RTL Libs

AXI Defines

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Description
universal components for FPGA development
Readme
131 KiB
Languages
SystemVerilog 83.8%
Python 13.5%
Makefile 2.7%