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Phil 6374dba26d infra: update gitignore
2026-06-09 15:30:07 +03:00
axi
tests: add simple read/write test
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infra: update gitignore
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README.md
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README.md

RTL Libs

AXI Defines

Description
universal components for FPGA development
Readme 98 KiB
Languages
SystemVerilog 100%