baulin.fa/rtl_libs
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Phil 43e2460124 docs: add README for tests
2026-06-09 16:00:58 +03:00
axi
docs: add README for tests
2026-06-09 16:00:58 +03:00
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infra: update gitignore
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README.md
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README.md

RTL Libs

AXI Defines

Description
universal components for FPGA development
Readme 98 KiB
Languages
SystemVerilog 100%