14 lines
374 B
Systemverilog
14 lines
374 B
Systemverilog
module axis_loopback #(
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parameter int unsigned DATA_W = 64,
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parameter int unsigned KEEP_W = DATA_W / 8,
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parameter int unsigned ID_W = 8,
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parameter int unsigned DEST_W = 8,
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parameter int unsigned USER_W = 1
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)(
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axis_if.slave s_axis,
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axis_if.master m_axis
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);
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assign m_axis.req = s_axis.req;
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assign s_axis.resp = m_axis.resp;
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endmodule : axis_loopback
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