baulin.fa/rtl_libs
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Phil 35ed5d6e6e tests: add dma test
2026-06-09 18:00:12 +03:00
axi
tests: add dma test
2026-06-09 18:00:12 +03:00
external
infra: add forencich repository as a submodule
2026-06-09 17:37:55 +03:00
.gitignore
infra: update gitignore
2026-06-09 15:30:07 +03:00
.gitmodules
infra: add forencich repository as a submodule
2026-06-09 17:37:55 +03:00
README.md
chore: first commit
2026-05-28 16:40:47 +03:00

README.md

RTL Libs

AXI Defines

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Description
universal components for FPGA development
Readme
131 KiB
Languages
SystemVerilog 83.8%
Python 13.5%
Makefile 2.7%