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30fa85d01c3544990e4a188abee2435d39c71b84
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Phil
30fa85d01c
tests: add axis loopback test
2026-06-09 17:23:07 +03:00
axi
tests: add axis loopback test
2026-06-09 17:23:07 +03:00
.gitignore
infra: update gitignore
2026-06-09 15:30:07 +03:00
README.md
chore: first commit
2026-05-28 16:40:47 +03:00
README.md
RTL Libs
AXI Defines
Description
universal components for FPGA development
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98
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SystemVerilog
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