baulin.fa/rtl_libs
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Phil 0c314bf2ae infra: add gitignore for sim builds
2026-06-09 14:59:49 +03:00
axi
infra: add tb mock and test makefile
2026-06-09 14:57:16 +03:00
.gitignore
infra: add gitignore for sim builds
2026-06-09 14:59:49 +03:00
README.md
chore: first commit
2026-05-28 16:40:47 +03:00

README.md

RTL Libs

AXI Defines

Description
universal components for FPGA development
Readme 98 KiB
Languages
SystemVerilog 100%