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baulin.fa/rtl_libs
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baulin.fa e4311214eb Merge pull request 'fix: axi dma wrapper' (#2) from dev into master
Reviewed-on: #2
2026-07-14 12:14:48 +03:00
axi
Merge pull request 'fix: axi dma wrapper' (#2) from dev into master
2026-07-14 12:14:48 +03:00
external
infra: add forencich repository as a submodule
2026-06-09 17:37:55 +03:00
.gitignore
infra: add tb result to gitignore
2026-06-17 17:24:23 +03:00
.gitmodules
infra: add forencich repository as a submodule
2026-06-09 17:37:55 +03:00
README.md
chore: first commit
2026-05-28 16:40:47 +03:00

README.md

RTL Libs

AXI Defines

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Description
universal components for FPGA development
Readme
131 KiB
Languages
SystemVerilog 83.8%
Python 13.5%
Makefile 2.7%
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