31 lines
1.0 KiB
Systemverilog
31 lines
1.0 KiB
Systemverilog
module axis_if_to_flat #(
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parameter int unsigned DATA_W = 64,
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parameter int unsigned KEEP_W = DATA_W / 8,
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parameter int unsigned ID_W = 8,
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parameter int unsigned DEST_W = 8,
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parameter int unsigned USER_W = 1
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)(
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axis_if.slave s_axis,
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output logic [DATA_W-1:0] m_axis_tdata,
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output logic [KEEP_W-1:0] m_axis_tkeep,
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output logic [KEEP_W-1:0] m_axis_tstrb,
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output logic m_axis_tlast,
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output logic [ID_W-1:0] m_axis_tid,
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output logic [DEST_W-1:0] m_axis_tdest,
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output logic [USER_W-1:0] m_axis_tuser,
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output logic m_axis_tvalid,
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input logic m_axis_tready
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);
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assign m_axis_tdata = s_axis.req.t.data;
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assign m_axis_tkeep = s_axis.req.t.keep;
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assign m_axis_tstrb = s_axis.req.t.strb;
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assign m_axis_tlast = s_axis.req.t.last;
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assign m_axis_tid = s_axis.req.t.id;
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assign m_axis_tdest = s_axis.req.t.dest;
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assign m_axis_tuser = s_axis.req.t.user;
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assign m_axis_tvalid = s_axis.req.t.valid;
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assign s_axis.resp.ready = m_axis_tready;
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endmodule : axis_if_to_flat
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