infra: add tb mock and test makefile

axi/tb/axi_cocotb_loopback_test/Makefile

@@ -0,0 +1,17 @@
+# Minimal cocotb + cocotbext-axi test for compact AXI interface loopback.
+# Run:
+#   make SIM=verilator
+# or:
+#   make SIM=questa
+
+TOPLEVEL_LANG = verilog
+SIM ?= verilator
+
+PWD := $(shell pwd)
+
+RTL_DIR = $(PWD)/../../rtl
+
+VERILOG_SOURCES += $(RTL_DIR)/axi_pkg.sv
+VERILOG_SOURCES += $(RTL_DIR)/axi_if.sv
+VERILOG_SOURCES += $(RTL_DIR)/axi4_flat_to_if.sv
+VERILOG_SOURCES += $(RTL_DIR)/axi4_if_to_flat.sv