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rtl_libs/axi/tb/axi_cocotb_loopback_test/Makefile
2026-06-09 14:57:16 +03:00

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Makefile

# Minimal cocotb + cocotbext-axi test for compact AXI interface loopback.
# Run:
# make SIM=verilator
# or:
# make SIM=questa
TOPLEVEL_LANG = verilog
SIM ?= verilator
PWD := $(shell pwd)
RTL_DIR = $(PWD)/../../rtl
VERILOG_SOURCES += $(RTL_DIR)/axi_pkg.sv
VERILOG_SOURCES += $(RTL_DIR)/axi_if.sv
VERILOG_SOURCES += $(RTL_DIR)/axi4_flat_to_if.sv
VERILOG_SOURCES += $(RTL_DIR)/axi4_if_to_flat.sv