refactor: add rtl dir

axi/rtl/axi_if.sv

@@ -0,0 +1,43 @@
+interface axi4_if #(
+  parameter int unsigned ADDR_W = 32,
+  parameter int unsigned DATA_W = 32,
+  parameter int unsigned ID_W   = 4,
+  parameter int unsigned USER_W = 1
+)(
+  input logic aclk,
+  input logic aresetn
+);
+  import axi_pkg::*;
+  typedef logic [ADDR_W-1:0]   addr_t;
+  typedef logic [DATA_W-1:0]   data_t;
+  typedef logic [DATA_W/8-1:0] strb_t;
+  typedef logic [ID_W-1:0]     id_t;
+  typedef logic [USER_W-1:0]   user_t;
+  `AXI4_TYPEDEF_ALL(axi, addr_t, data_t, strb_t, id_t, user_t)
+  axi_req_t  req;
+  axi_resp_t resp;
+  modport master (input aclk, aresetn, output req, input resp);
+  modport slave  (input aclk, aresetn, input req, output resp);
+  modport monitor(input aclk, aresetn, input req, input resp);
+endinterface : axi4_if
+
+interface axi4l_if #(
+  parameter int unsigned ADDR_W = 32,
+  parameter int unsigned DATA_W = 32,
+  parameter int unsigned USER_W = 1
+)(
+  input logic aclk,
+  input logic aresetn
+);
+  import axi_pkg::*;
+  typedef logic [ADDR_W-1:0]   addr_t;
+  typedef logic [DATA_W-1:0]   data_t;
+  typedef logic [DATA_W/8-1:0] strb_t;
+  typedef logic [USER_W-1:0]   user_t;
+  `AXI4L_TYPEDEF_ALL(axil, addr_t, data_t, strb_t, user_t)
+  axil_req_t  req;
+  axil_resp_t resp;
+  modport master (input aclk, aresetn, output req, input resp);
+  modport slave  (input aclk, aresetn, input req, output resp);
+  modport monitor(input aclk, aresetn, input req, input resp);
+endinterface : axi4l_if