refactor: add rtl dir

axi/rtl/axi4l_flat_to_if.sv

@@ -0,0 +1,58 @@
+module axi4l_flat_to_if #(
+  parameter int unsigned ADDR_W = 32,
+  parameter int unsigned DATA_W = 32,
+  parameter int unsigned USER_W = 1
+)(
+  input  logic aclk,
+  input  logic aresetn,
+  input  logic [ADDR_W-1:0]   s_axil_awaddr,
+  input  logic [2:0]          s_axil_awprot,
+  input  logic [USER_W-1:0]   s_axil_awuser,
+  input  logic                s_axil_awvalid,
+  output logic                s_axil_awready,
+  input  logic [DATA_W-1:0]   s_axil_wdata,
+  input  logic [DATA_W/8-1:0] s_axil_wstrb,
+  input  logic [USER_W-1:0]   s_axil_wuser,
+  input  logic                s_axil_wvalid,
+  output logic                s_axil_wready,
+  output logic [1:0]          s_axil_bresp,
+  output logic [USER_W-1:0]   s_axil_buser,
+  output logic                s_axil_bvalid,
+  input  logic                s_axil_bready,
+  input  logic [ADDR_W-1:0]   s_axil_araddr,
+  input  logic [2:0]          s_axil_arprot,
+  input  logic [USER_W-1:0]   s_axil_aruser,
+  input  logic                s_axil_arvalid,
+  output logic                s_axil_arready,
+  output logic [DATA_W-1:0]   s_axil_rdata,
+  output logic [1:0]          s_axil_rresp,
+  output logic [USER_W-1:0]   s_axil_ruser,
+  output logic                s_axil_rvalid,
+  input  logic                s_axil_rready,
+  axi4l_if.master             m_axil
+);
+  assign m_axil.req.aw.addr   = s_axil_awaddr;
+  assign m_axil.req.aw.prot   = s_axil_awprot;
+  assign m_axil.req.aw.user   = s_axil_awuser;
+  assign m_axil.req.aw.valid  = s_axil_awvalid;
+  assign s_axil_awready       = m_axil.resp.aw_ready;
+  assign m_axil.req.w.data    = s_axil_wdata;
+  assign m_axil.req.w.strb    = s_axil_wstrb;
+  assign m_axil.req.w.user    = s_axil_wuser;
+  assign m_axil.req.w.valid   = s_axil_wvalid;
+  assign s_axil_wready        = m_axil.resp.w_ready;
+  assign s_axil_bresp         = m_axil.resp.b.resp;
+  assign s_axil_buser         = m_axil.resp.b.user;
+  assign s_axil_bvalid        = m_axil.resp.b.valid;
+  assign m_axil.req.b_ready   = s_axil_bready;
+  assign m_axil.req.ar.addr   = s_axil_araddr;
+  assign m_axil.req.ar.prot   = s_axil_arprot;
+  assign m_axil.req.ar.user   = s_axil_aruser;
+  assign m_axil.req.ar.valid  = s_axil_arvalid;
+  assign s_axil_arready       = m_axil.resp.ar_ready;
+  assign s_axil_rdata         = m_axil.resp.r.data;
+  assign s_axil_rresp         = m_axil.resp.r.resp;
+  assign s_axil_ruser         = m_axil.resp.r.user;
+  assign s_axil_rvalid        = m_axil.resp.r.valid;
+  assign m_axil.req.r_ready   = s_axil_rready;
+endmodule