rtl: add axis iface

This commit is contained in:
Phil
2026-06-09 17:18:56 +03:00
parent 43e2460124
commit 52a2bccc77
3 changed files with 107 additions and 0 deletions

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module axis_flat_to_if #(
parameter int unsigned DATA_W = 64,
parameter int unsigned KEEP_W = DATA_W / 8,
parameter int unsigned ID_W = 8,
parameter int unsigned DEST_W = 8,
parameter int unsigned USER_W = 1
)(
input logic [DATA_W-1:0] s_axis_tdata,
input logic [KEEP_W-1:0] s_axis_tkeep,
input logic [KEEP_W-1:0] s_axis_tstrb,
input logic s_axis_tlast,
input logic [ID_W-1:0] s_axis_tid,
input logic [DEST_W-1:0] s_axis_tdest,
input logic [USER_W-1:0] s_axis_tuser,
input logic s_axis_tvalid,
output logic s_axis_tready,
axis_if.master m_axis
);
assign m_axis.req.t.data = s_axis_tdata;
assign m_axis.req.t.keep = s_axis_tkeep;
assign m_axis.req.t.strb = s_axis_tstrb;
assign m_axis.req.t.last = s_axis_tlast;
assign m_axis.req.t.id = s_axis_tid;
assign m_axis.req.t.dest = s_axis_tdest;
assign m_axis.req.t.user = s_axis_tuser;
assign m_axis.req.t.valid = s_axis_tvalid;
assign s_axis_tready = m_axis.resp.ready;
endmodule : axis_flat_to_if

47
axi/rtl/axis_if.sv Normal file
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`define AXIS_TYPEDEF_ALL(__name, __data_t, __keep_t, __strb_t, __id_t, __dest_t, __user_t) \
typedef struct packed { \
__data_t data; \
__keep_t keep; \
__strb_t strb; \
logic last; \
__id_t id; \
__dest_t dest; \
__user_t user; \
logic valid; \
} __name``_chan_t; \
typedef struct packed { \
__name``_chan_t t; \
} __name``_req_t; \
typedef struct packed { \
logic ready; \
} __name``_resp_t;
interface axis_if #(
parameter int unsigned DATA_W = 64,
parameter int unsigned KEEP_W = DATA_W / 8,
parameter int unsigned ID_W = 8,
parameter int unsigned DEST_W = 8,
parameter int unsigned USER_W = 1
)(
input logic aclk,
input logic aresetn
);
typedef logic [DATA_W-1:0] data_t;
typedef logic [KEEP_W-1:0] keep_t;
typedef logic [KEEP_W-1:0] strb_t;
typedef logic [ID_W-1:0] id_t;
typedef logic [DEST_W-1:0] dest_t;
typedef logic [USER_W-1:0] user_t;
`AXIS_TYPEDEF_ALL(axis, data_t, keep_t, strb_t, id_t, dest_t, user_t)
axis_req_t req;
axis_resp_t resp;
modport master (input aclk, aresetn, output req, input resp);
modport slave (input aclk, aresetn, input req, output resp);
modport monitor (input aclk, aresetn, input req, input resp);
endinterface : axis_if

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module axis_if_to_flat #(
parameter int unsigned DATA_W = 64,
parameter int unsigned KEEP_W = DATA_W / 8,
parameter int unsigned ID_W = 8,
parameter int unsigned DEST_W = 8,
parameter int unsigned USER_W = 1
)(
axis_if.slave s_axis,
output logic [DATA_W-1:0] m_axis_tdata,
output logic [KEEP_W-1:0] m_axis_tkeep,
output logic [KEEP_W-1:0] m_axis_tstrb,
output logic m_axis_tlast,
output logic [ID_W-1:0] m_axis_tid,
output logic [DEST_W-1:0] m_axis_tdest,
output logic [USER_W-1:0] m_axis_tuser,
output logic m_axis_tvalid,
input logic m_axis_tready
);
assign m_axis_tdata = s_axis.req.t.data;
assign m_axis_tkeep = s_axis.req.t.keep;
assign m_axis_tstrb = s_axis.req.t.strb;
assign m_axis_tlast = s_axis.req.t.last;
assign m_axis_tid = s_axis.req.t.id;
assign m_axis_tdest = s_axis.req.t.dest;
assign m_axis_tuser = s_axis.req.t.user;
assign m_axis_tvalid = s_axis.req.t.valid;
assign s_axis.resp.ready = m_axis_tready;
endmodule : axis_if_to_flat