rtl: add axis iface

axi/rtl/axis_if.sv

@@ -0,0 +1,47 @@
+`define AXIS_TYPEDEF_ALL(__name, __data_t, __keep_t, __strb_t, __id_t, __dest_t, __user_t) \
+  typedef struct packed { \
+    __data_t data; \
+    __keep_t keep; \
+    __strb_t strb; \
+    logic    last; \
+    __id_t   id; \
+    __dest_t dest; \
+    __user_t user; \
+    logic    valid; \
+  } __name``_chan_t; \
+  typedef struct packed { \
+    __name``_chan_t t; \
+  } __name``_req_t; \
+  typedef struct packed { \
+    logic ready; \
+  } __name``_resp_t;
+
+
+
+interface axis_if #(
+  parameter int unsigned DATA_W = 64,
+  parameter int unsigned KEEP_W = DATA_W / 8,
+  parameter int unsigned ID_W   = 8,
+  parameter int unsigned DEST_W = 8,
+  parameter int unsigned USER_W = 1
+)(
+  input logic aclk,
+  input logic aresetn
+);
+  typedef logic [DATA_W-1:0] data_t;
+  typedef logic [KEEP_W-1:0] keep_t;
+  typedef logic [KEEP_W-1:0] strb_t;
+  typedef logic [ID_W-1:0]   id_t;
+  typedef logic [DEST_W-1:0] dest_t;
+  typedef logic [USER_W-1:0] user_t;
+
+  `AXIS_TYPEDEF_ALL(axis, data_t, keep_t, strb_t, id_t, dest_t, user_t)
+
+  axis_req_t  req;
+  axis_resp_t resp;
+
+  modport master  (input aclk, aresetn, output req, input  resp);
+  modport slave   (input aclk, aresetn, input  req, output resp);
+  modport monitor (input aclk, aresetn, input  req, input  resp);
+endinterface : axis_if
+