tests: add dma test
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Phil
81
axi/tb/axi_dma_wrapper/Makefile
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81
axi/tb/axi_dma_wrapper/Makefile
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TOPLEVEL_LANG = verilog
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SIM ?= verilator
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PWD := $(shell pwd)
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PROJECT_ROOT ?= $(abspath $(PWD)/../../..)
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AXI_IF_RTL_DIR ?= $(PROJECT_ROOT)/axi/rtl
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FORENCICH_AXI_RTL_DIR ?= $(PROJECT_ROOT)/external/verilog-axi/rtl
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TB_DIR ?= $(PWD)
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TOPLEVEL = tb_axi_dma_wrapper
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MODULE = test_axi_dma_wrapper
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export PYTHONPATH := $(TB_DIR):$(PYTHONPATH)
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# Parameters for a quick make-based run. The pytest entrypoint can be used for
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# wider parameter sweeps.
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AXI_DATA_WIDTH ?= 32
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AXI_ADDR_WIDTH ?= 16
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AXI_ID_WIDTH ?= 8
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AXI_USER_WIDTH ?= 1
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AXI_MAX_BURST_LEN ?= 16
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ENABLE_UNALIGNED ?= 0
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AXI_STRB_WIDTH := $(shell expr $(AXI_DATA_WIDTH) / 8)
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AXIS_DATA_WIDTH ?= $(AXI_DATA_WIDTH)
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AXIS_KEEP_WIDTH := $(shell expr $(AXIS_DATA_WIDTH) / 8)
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AXIS_KEEP_ENABLE := $(shell [ $(AXIS_DATA_WIDTH) -gt 8 ] && echo 1 || echo 0)
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VERILOG_SOURCES += $(AXI_IF_RTL_DIR)/axi_pkg.sv
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VERILOG_SOURCES += $(AXI_IF_RTL_DIR)/axi_if.sv
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VERILOG_SOURCES += $(AXI_IF_RTL_DIR)/axis_if.sv
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VERILOG_SOURCES += $(AXI_IF_RTL_DIR)/axi4_flat_to_if.sv
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VERILOG_SOURCES += $(AXI_IF_RTL_DIR)/axi4_if_to_flat.sv
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VERILOG_SOURCES += $(AXI_IF_RTL_DIR)/axis_flat_to_if.sv
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VERILOG_SOURCES += $(AXI_IF_RTL_DIR)/axis_if_to_flat.sv
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VERILOG_SOURCES += $(FORENCICH_AXI_RTL_DIR)/axi_dma.v
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VERILOG_SOURCES += $(FORENCICH_AXI_RTL_DIR)/axi_dma_rd.v
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VERILOG_SOURCES += $(FORENCICH_AXI_RTL_DIR)/axi_dma_wr.v
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VERILOG_SOURCES += $(AXI_IF_RTL_DIR)/forencich_axi_dma_wrapper.sv
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VERILOG_SOURCES += $(TB_DIR)/tb_axi_dma_wrapper.sv
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COMPILE_ARGS += -I$(AXI_IF_RTL_DIR)
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COMPILE_ARGS += -I$(WRAPPER_RTL_DIR)
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COMPILE_ARGS += -I$(FORENCICH_AXI_RTL_DIR)
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# took this from forencich to silence 100+ warnings
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COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH -Wno-CASEINCOMPLETE
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ifeq ($(SIM),verilator)
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EXTRA_ARGS += --trace
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EXTRA_ARGS += --trace-structs
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EXTRA_ARGS += -GAXI_DATA_WIDTH=$(AXI_DATA_WIDTH)
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EXTRA_ARGS += -GAXI_ADDR_WIDTH=$(AXI_ADDR_WIDTH)
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EXTRA_ARGS += -GAXI_STRB_WIDTH=$(AXI_STRB_WIDTH)
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EXTRA_ARGS += -GAXI_ID_WIDTH=$(AXI_ID_WIDTH)
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EXTRA_ARGS += -GAXI_USER_WIDTH=$(AXI_USER_WIDTH)
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EXTRA_ARGS += -GAXI_MAX_BURST_LEN=$(AXI_MAX_BURST_LEN)
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EXTRA_ARGS += -GAXIS_DATA_WIDTH=$(AXIS_DATA_WIDTH)
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EXTRA_ARGS += -GAXIS_KEEP_ENABLE=$(AXIS_KEEP_ENABLE)
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EXTRA_ARGS += -GAXIS_KEEP_WIDTH=$(AXIS_KEEP_WIDTH)
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EXTRA_ARGS += -GAXIS_LAST_ENABLE=1
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EXTRA_ARGS += -GAXIS_ID_ENABLE=1
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EXTRA_ARGS += -GAXIS_ID_WIDTH=8
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EXTRA_ARGS += -GAXIS_DEST_ENABLE=0
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EXTRA_ARGS += -GAXIS_DEST_WIDTH=8
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EXTRA_ARGS += -GAXIS_USER_ENABLE=1
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EXTRA_ARGS += -GAXIS_USER_WIDTH=1
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EXTRA_ARGS += -GLEN_WIDTH=20
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EXTRA_ARGS += -GTAG_WIDTH=8
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EXTRA_ARGS += -GENABLE_SG=0
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EXTRA_ARGS += -GENABLE_UNALIGNED=$(ENABLE_UNALIGNED)
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endif
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export PARAM_AXI_DATA_WIDTH=$(AXI_DATA_WIDTH)
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export PARAM_ENABLE_UNALIGNED=$(ENABLE_UNALIGNED)
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include $(shell cocotb-config --makefiles)/Makefile.sim
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237
axi/tb/axi_dma_wrapper/test_axi_dma_wrapper.py
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237
axi/tb/axi_dma_wrapper/test_axi_dma_wrapper.py
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# SPDX-License-Identifier: MIT
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"""
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Small cocotb/pytest test for tb_axi_dma_wrapper.
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It intentionally keeps the same flat prefixes that alexforencich/verilog-axi
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uses for axi_dma, while the SystemVerilog top routes the traffic through
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local axi4_if/axis_if adapters and forencich_axi_dma_wrapper.
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"""
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import os
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import logging
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import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import RisingEdge
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from cocotbext.axi import AxiBus, AxiRam
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from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
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from cocotbext.axi.stream import define_stream
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DescBus, DescTransaction, DescSource, DescSink, DescMonitor = define_stream(
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"Desc",
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signals=["addr", "len", "tag", "valid", "ready"],
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optional_signals=["id", "dest", "user"],
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)
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DescStatusBus, DescStatusTransaction, DescStatusSource, DescStatusSink, DescStatusMonitor = define_stream(
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"DescStatus",
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signals=["tag", "error", "valid"],
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optional_signals=["len", "id", "dest", "user"],
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)
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class TB:
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def __init__(self, dut):
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self.dut = dut
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self.log = logging.getLogger("cocotb.tb")
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self.log.setLevel(logging.DEBUG)
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cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
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# Descriptor and status streams are flat, exactly like Forencich tests.
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self.read_desc_source = DescSource(
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DescBus.from_prefix(dut, "s_axis_read_desc"), dut.clk, dut.rst
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)
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self.read_desc_status_sink = DescStatusSink(
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DescStatusBus.from_prefix(dut, "m_axis_read_desc_status"), dut.clk, dut.rst
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)
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self.write_desc_source = DescSource(
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DescBus.from_prefix(dut, "s_axis_write_desc"), dut.clk, dut.rst
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)
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self.write_desc_status_sink = DescStatusSink(
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DescStatusBus.from_prefix(dut, "m_axis_write_desc_status"), dut.clk, dut.rst
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)
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# Data streams are also flat from cocotb point of view. The SV top
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# converts them to axis_if before reaching the wrapper.
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self.read_data_sink = AxiStreamSink(
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AxiStreamBus.from_prefix(dut, "m_axis_read_data"), dut.clk, dut.rst
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)
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self.write_data_source = AxiStreamSource(
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AxiStreamBus.from_prefix(dut, "s_axis_write_data"), dut.clk, dut.rst
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)
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# AXI memory model. The SV top converts m_axi flat signals to axi4_if
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# and back, so this also tests the AXI converters.
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self.axi_ram = AxiRam(AxiBus.from_prefix(dut, "m_axi"), dut.clk, dut.rst, size=2**16)
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dut.read_enable.setimmediatevalue(0)
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dut.write_enable.setimmediatevalue(0)
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dut.write_abort.setimmediatevalue(0)
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async def reset(self):
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self.dut.rst.setimmediatevalue(0)
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst.value = 1
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst.value = 0
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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def _make_data(length, seed=0):
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return bytearray(((x + seed) & 0xFF) for x in range(length))
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@cocotb.test()
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async def test_axi_dma_wrapper_write(dut):
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tb = TB(dut)
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await tb.reset()
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tb.dut.write_enable.value = 1
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addr = 0x1000
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data = _make_data(96, seed=0x10)
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tag = 3
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# Guard bytes make it easier to catch wrong offsets/strobes.
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tb.axi_ram.write(addr - 16, b"\xaa" * (len(data) + 32))
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await tb.write_desc_source.send(DescTransaction(addr=addr, len=len(data), tag=tag))
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await tb.write_data_source.send(AxiStreamFrame(data, tid=tag))
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status = await tb.write_desc_status_sink.recv()
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tb.log.info("write status: %s", status)
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assert int(status.error) == 0
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assert int(status.tag) == tag
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assert int(status.len) == len(data)
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assert tb.axi_ram.read(addr - 8, len(data) + 16) == b"\xaa" * 8 + data + b"\xaa" * 8
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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@cocotb.test()
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async def test_axi_dma_wrapper_read(dut):
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tb = TB(dut)
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await tb.reset()
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tb.dut.read_enable.value = 1
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addr = 0x1800
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data = _make_data(113, seed=0x40)
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tag = 5
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stream_id = 7
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tb.axi_ram.write(addr - 16, b"\xcc" * (len(data) + 32))
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tb.axi_ram.write(addr, data)
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await tb.read_desc_source.send(
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DescTransaction(addr=addr, len=len(data), tag=tag, id=stream_id)
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)
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status = await tb.read_desc_status_sink.recv()
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frame = await tb.read_data_sink.recv()
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tb.log.info("read status: %s", status)
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tb.log.info("read frame: %s", frame)
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assert int(status.error) == 0
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assert int(status.tag) == tag
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assert frame.tdata == data
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assert int(frame.tid) == stream_id
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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# -----------------------------------------------------------------------------
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# Optional pytest entrypoint via cocotb-test.
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# Run from this directory with: pytest -q test_axi_dma_wrapper.py
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# -----------------------------------------------------------------------------
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def test_axi_dma_wrapper_pytest(request):
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import cocotb_test.simulator
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tests_dir = os.path.abspath(os.path.dirname(__file__))
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project_root = os.path.abspath(os.path.join(tests_dir, "..", ".."))
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axi_if_rtl_dir = os.environ.get(
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"AXI_IF_RTL_DIR", os.path.join(project_root, "rtl", "axi")
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)
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wrapper_rtl_dir = os.environ.get(
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"WRAPPER_RTL_DIR", os.path.join(project_root, "rtl", "wrappers")
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)
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forencich_rtl_dir = os.environ.get(
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"FORENCICH_AXI_RTL_DIR",
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os.path.join(project_root, "external", "verilog-axi", "rtl"),
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)
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dut = "tb_axi_dma_wrapper"
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module = os.path.splitext(os.path.basename(__file__))[0]
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toplevel = dut
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parameters = {
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"AXI_DATA_WIDTH": int(os.getenv("PARAM_AXI_DATA_WIDTH", "32")),
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"AXI_ADDR_WIDTH": 16,
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"AXI_ID_WIDTH": 8,
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"AXI_USER_WIDTH": 1,
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"AXI_MAX_BURST_LEN": 16,
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"AXIS_ID_ENABLE": 1,
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"AXIS_ID_WIDTH": 8,
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"AXIS_DEST_ENABLE": 0,
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"AXIS_DEST_WIDTH": 8,
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"AXIS_USER_ENABLE": 1,
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"AXIS_USER_WIDTH": 1,
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"LEN_WIDTH": 20,
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"TAG_WIDTH": 8,
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"ENABLE_SG": 0,
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"ENABLE_UNALIGNED": int(os.getenv("PARAM_ENABLE_UNALIGNED", "0")),
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}
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parameters["AXI_STRB_WIDTH"] = parameters["AXI_DATA_WIDTH"] // 8
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parameters["AXIS_DATA_WIDTH"] = parameters["AXI_DATA_WIDTH"]
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parameters["AXIS_KEEP_ENABLE"] = int(parameters["AXIS_DATA_WIDTH"] > 8)
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parameters["AXIS_KEEP_WIDTH"] = parameters["AXIS_DATA_WIDTH"] // 8
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parameters["AXIS_LAST_ENABLE"] = 1
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verilog_sources = [
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os.path.join(axi_if_rtl_dir, "axi_pkg.sv"),
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os.path.join(axi_if_rtl_dir, "axi_if.sv"),
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os.path.join(axi_if_rtl_dir, "axis_if.sv"),
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os.path.join(axi_if_rtl_dir, "axi4_flat_to_if.sv"),
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os.path.join(axi_if_rtl_dir, "axi4_if_to_flat.sv"),
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os.path.join(axi_if_rtl_dir, "axis_flat_to_if.sv"),
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os.path.join(axi_if_rtl_dir, "axis_if_to_flat.sv"),
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os.path.join(forencich_rtl_dir, "axi_dma.v"),
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os.path.join(forencich_rtl_dir, "axi_dma_rd.v"),
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os.path.join(forencich_rtl_dir, "axi_dma_wr.v"),
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os.path.join(wrapper_rtl_dir, "forencich_axi_dma_wrapper.sv"),
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os.path.join(tests_dir, "tb_axi_dma_wrapper.sv"),
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]
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extra_env = {f"PARAM_{k}": str(v) for k, v in parameters.items()}
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sim_build = os.path.join(
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tests_dir,
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"sim_build",
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request.node.name.replace("[", "-").replace("]", ""),
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)
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cocotb_test.simulator.run(
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python_search=[tests_dir],
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verilog_sources=verilog_sources,
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includes=[axi_if_rtl_dir, wrapper_rtl_dir, forencich_rtl_dir],
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toplevel=toplevel,
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module=module,
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parameters=parameters,
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sim_build=sim_build,
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extra_env=extra_env,
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waves=True,
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extra_args=["--trace-structs"] if os.getenv("SIM", "verilator") == "verilator" else [],
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)
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