Files
reflectometer_fpga_project/designs/adc_dac_synchoronizer/debug.xdc

3 lines
147 B
Tcl

# Primary clocks
create_clock -name eth_clk -period 8.000 [get_ports dac_clk_in]
create_clock -name acc_clk -period 15.385 [get_ports adc_clk_in]