53 lines
1.2 KiB
Systemverilog
53 lines
1.2 KiB
Systemverilog
`timescale 1ns / 1ps
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module adder
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#(
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parameter DATA_WIDTH = 12,
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parameter WINDOW_SIZE = 4,
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parameter ACCUM_WIDTH = 32
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)
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(
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input clk_in,
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input rst,
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input [DATA_WIDTH-1:0] s_axis_tdata,
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input s_axis_tvalid,
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output [ACCUM_WIDTH-1:0] sum_data,
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output sum_valid
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);
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logic [ACCUM_WIDTH-1:0] accum, res;
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logic [DATA_WIDTH-1:0] axis_data;
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logic res_valid, axis_valid;
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(* MARK_DEBUG = "TRUE" *) logic [15:0] cnt;
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always @(posedge clk_in) begin
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if (rst) begin
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accum <= '0;
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cnt <= '0;
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res <= '0;
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res_valid <= 0;
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end else begin
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res_valid <= 0;
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axis_data <= s_axis_tdata;
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axis_valid <= s_axis_tvalid;
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if ( axis_valid) begin
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if (cnt == WINDOW_SIZE-1) begin
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res <= accum + axis_data;
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res_valid <= 1;
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accum <= '0;
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cnt <= '0;
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end else begin
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accum <= accum + axis_data;
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cnt <= cnt + 1;
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end
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end
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end
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end
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assign sum_valid = res_valid;
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assign sum_data = res;
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endmodule
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