`timescale 1ns / 1ps


module adder
#(
    parameter DATA_WIDTH = 12,
    parameter WINDOW_SIZE = 4,
    parameter ACCUM_WIDTH = 32
    )
(
    input clk_in,
    input rst,
    input [DATA_WIDTH-1:0] s_axis_tdata,
    input s_axis_tvalid,
    
    output [ACCUM_WIDTH-1:0] sum_data,
    output sum_valid
    );

    logic [ACCUM_WIDTH-1:0] accum, res;
    logic [DATA_WIDTH-1:0] axis_data;
    logic res_valid, axis_valid;
 (* MARK_DEBUG = "TRUE" *)   logic [15:0] cnt;
    
    always @(posedge clk_in) begin
        if (rst) begin
            accum <= '0;
            cnt <= '0;
            res <= '0;
            res_valid <= 0;
        end else begin
            res_valid <= 0;
            axis_data <= s_axis_tdata;
            axis_valid <= s_axis_tvalid;
            if ( axis_valid) begin
                if (cnt == WINDOW_SIZE-1) begin
                    res <= accum + axis_data;
                    res_valid <= 1;
                    accum <= '0;
                    cnt <= '0;
                end else begin
                    accum <= accum + axis_data;
                    cnt   <= cnt + 1;
                end
            end
        end
    end 
   
    assign sum_valid = res_valid;
    assign sum_data = res;
    
endmodule