260 lines
8.4 KiB
Systemverilog
260 lines
8.4 KiB
Systemverilog
`timescale 1 ns / 1 ns
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module reflectometer_top #(
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parameter int unsigned DAC_DATA_WIDTH = 14,
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parameter int unsigned ADC_DATA_WIDTH = 12,
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parameter PACK_FACTOR = 1,
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parameter PROCESS_MODE = 0,
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parameter ZERO_LEVEL = 8192,
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parameter ACCUM_WIDTH = 32,
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parameter N_MAX = 4096,
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parameter WINDOW_SIZE = 65,
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parameter PACKET_SIZE = 1024
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)(
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input clk_in,
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input rst_n,
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output [3:0] status_led,
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// Accumulator AXI-S bus
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input wire clk_m_axis, // GMII PHY RX clock
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output logic [7:0] m_axis_tdata,
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output logic m_axis_tvalid,
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input wire m_axis_tready,
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output logic m_axis_tlast,
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// Control AXI-S bus
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input wire clk_s_axis, // GMII PHY TX clock
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input wire [7:0] s_axis__tdata,
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input wire s_axis_tvalid,
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input wire s_axis_tlast,
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output logic s_axis_tready,
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// RTL-MAC handshake
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input wire request_ready,
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output logic send_request,
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// DAC
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output logic clk_dac,
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output logic [DAC_DATA_WIDTH-1:0] dac_data,
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output logic dac_wrt,
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// ADC
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output logic clk_adc,
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input wire [ADC_DATA_WIDTH-1:0] adc_data,
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input wire adc_otr
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);
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// // -------------------------------------------------------------------------
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// // IDELAYCTRL
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// // -------------------------------------------------------------------------
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// (* IODELAY_GROUP = "rgmii_idelay_group" *)
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// IDELAYCTRL IDELAYCTRL_inst (
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// .RDY (),
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// .REFCLK (sys_clk),
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// .RST (1'b0)
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// ); TODO remove
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// -------------------------------------------------------------------------
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// Generated clocks for controller
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// Need to create this IP in Vivado:
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// input resetn
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// input clk_200 : 200 MHz : Reference clock
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// output clk_adc_65 : 65 MHz : ADC RTL clock
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// output clk_adc_65_180 : 65 MHz, phase 180 deg. : ADC PHY clock
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// output clk_adc_125 : 125 MHz : DAC RTL clock
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// output clk_adc_125_180 : 125 MHz, phase 180 deg. : DAC PHY clock
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// output locked
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// -------------------------------------------------------------------------
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wire clk_sampler, clk_adc;
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wire clk_generator, clk_dac;
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wire clk_locked;
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clk_wiz_ctrl_inst_clk_wiz inst
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(
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// Clock in ports
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.clk_200(clk_in)
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// Clock out ports
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.clk_adc_65(clk_adc),
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.clk_adc_65_180(clk_sampler),
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.clk_dac_125(clk_dac),
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.clk_dac_125_180(clk_generator),
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// Status and control signals
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.resetn(rst_n),
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.locked(clk_locked),
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);
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// -------------------------------------------------------------------------
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// Controller reset
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// Use both external reset and clk_wiz lock
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// -------------------------------------------------------------------------
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wire ctrl_rst_n = rst_n & clk_wiz_locked;
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logic finish;
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// Controller outputs to debug
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wire [31:0] dac_pulse_width;
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wire [31:0] dac_pulse_period;
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wire [DAC_DATA_WIDTH-1:0] dac_pulse_height;
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wire [15:0] dac_pulse_num;
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wire [31:0] adc_pulse_period;
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wire [15:0] adc_pulse_num;
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wire dac_start;
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wire adc_start;
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wire dac_rst;
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wire adc_rst;
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// -------------------------------------------------------------------------
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// Controller TODO
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// -------------------------------------------------------------------------
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control #(
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.DAC_DATA_WIDTH(DAC_DATA_WIDTH)
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) udp_ctrl_inst (
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.eth_clk_in (gmii_rx_clk),
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.dac_clk_in (dac_clk),
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.adc_clk_in (adc_clk),
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.rst_n (ctrl_rst_n),
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.s_axis_tdata (m_axis_rx_tdata),
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.s_axis_tvalid (m_axis_rx_tvalid),
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.s_axis_tready (m_axis_rx_tready),
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.s_axis_tlast (m_axis_rx_tlast),
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.finish (finish),
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.dac_pulse_width (dac_pulse_width),
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.dac_pulse_period (dac_pulse_period),
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.dac_pulse_height (dac_pulse_height),
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.dac_pulse_num (dac_pulse_num),
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.adc_pulse_period (adc_pulse_period),
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.adc_pulse_num (adc_pulse_num),
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.dac_start (dac_start),
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.adc_start (adc_start),
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.dac_rst (dac_rst),
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.adc_rst (adc_rst)
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);
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//------------------------------------------------------------
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// DAC -> ADC CDC TODO
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//------------------------------------------------------------
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logic sample_req;
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logic sample_req_sync1;
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logic sample_req_sync2;
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logic sample_req_sync3;
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logic sample_done;
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logic sample_done_sync1;
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logic sample_done_sync2;
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logic sample_done_sync3;
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always_ff @(posedge adc_clk or posedge adc_rst) begin
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if (adc_rst) begin
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sample_req <= 1'b0;
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sample_req_sync2 <= 1'b0;
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sample_req_sync3 <= 1'b0;
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end
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else begin
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sample_req_sync2 <= sample_req_sync1;
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sample_req_sync3 <= sample_req_sync2;
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sample_req <= sample_req_sync3;
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end
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end
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//------------------------------------------------------------
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// ADC -> DAC CDC TODO
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//------------------------------------------------------------
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always_ff @(posedge dac_clk or posedge dac_rst) begin
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if (dac_rst) begin
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sample_done <= 1'b0;
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sample_done_sync2 <= 1'b0;
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sample_done_sync3 <= 1'b0;
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end
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else begin
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sample_done_sync2 <= sample_done_sync1;
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sample_done_sync3 <= sample_done_sync2;
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sample_done <= sample_done_sync3;
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end
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end
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//------------------------------------------------------------
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// Generator (DAC) TODO
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//------------------------------------------------------------
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generator #(
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.DATA_WIDTH(DAC_DATA_WIDTH),
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.ZERO_LEVEL(ZERO_LEVEL)
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) generator_inst (
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.clk_in(dac_clk),
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.rst(dac_rst),
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.start(dac_start),
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.pulse_width(dac_pulse_width),
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.pulse_period(dac_pulse_period),
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.pulse_height(dac_pulse_height),
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.pulse_num(dac_pulse_num),
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.pulse(p2_wrt),
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.pulse_height_out(p2_data),
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.sample_done(sample_done),
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.sample_req(sample_req_sync1)
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);
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// -------------------------------------------------------------------------
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// Sampler (ADC) TODO
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// -------------------------------------------------------------------------
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sampler #(
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.DATA_WIDTH(ADC_DATA_WIDTH),
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.PACK_FACTOR(PACK_FACTOR),
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.PROCESS_MODE(PROCESS_MODE)
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) sampler_dut (
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.clk_in(clk_sampler),
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.rst(adc_rst),
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.data_in(ch2_data),
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.out_of_range(ch2_otr),
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.m_axis_tdata(accum_m_axis_tdata),
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.m_axis_tvalid(acum_m_axis_tvalid),
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.smp_num(adc_pulse_period),
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.sample_req(sample_req),
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.sample_done(sample_done_sync1)
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);
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// -------------------------------------------------------------------------
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// Accumulator TODO
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// -------------------------------------------------------------------------
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accumulator_top #(
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.DATA_WIDTH(ADC_DATA_WIDTH),
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.ACCUM_WIDTH(ACCUM_WIDTH),
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.N_MAX(N_MAX),
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.WINDOW_SIZE(WINDOW_SIZE),
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.PACKET_SIZE(PACKET_SIZE)
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) accumulator_top_dut (
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.clk_in(clk_sampler),
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.rst(adc_rst),
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.s_axis_tdata(accum_m_axis_tdata),
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.s_axis_tvalid(acum_m_axis_tvalid),
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.start(adc_start),
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.smp_num(adc_pulse_period),
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.seq_num(adc_pulse_num),
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.eth_clk_in(gmii_tx_clk),
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.req_ready(req_ready),
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.send_req(send_req),
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.m_axis_tdata(s_axis_tx_tdata),
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.m_axis_tvalid(s_axis_tx_tvalid),
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.m_axis_tready(s_axis_tx_tready),
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.m_axis_tlast(s_axis_tx_tlast),
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.finish(finish)
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);
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// -------------------------------------------------------------------------
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// LED status TODO
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// -------------------------------------------------------------------------
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assign led[0] = clk_locked;
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assign led[1] = rst_n;
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// assign led[2] = ;
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// assign led[3] = ;
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endmodule |