`timescale 1 ns / 1 ns module reflectometer_top #( parameter int unsigned DAC_DATA_WIDTH = 14, parameter int unsigned ADC_DATA_WIDTH = 12, parameter PACK_FACTOR = 1, parameter PROCESS_MODE = 0, parameter ZERO_LEVEL = 8192, parameter ACCUM_WIDTH = 32, parameter N_MAX = 4096, parameter WINDOW_SIZE = 65, parameter PACKET_SIZE = 1024 )( input clk_in, input rst_n, output [3:0] status_led, // Accumulator AXI-S bus input wire clk_m_axis, // GMII PHY RX clock output logic [7:0] m_axis_tdata, output logic m_axis_tvalid, input wire m_axis_tready, output logic m_axis_tlast, // Control AXI-S bus input wire clk_s_axis, // GMII PHY TX clock input wire [7:0] s_axis__tdata, input wire s_axis_tvalid, input wire s_axis_tlast, output logic s_axis_tready, // RTL-MAC handshake input wire request_ready, output logic send_request, // DAC output logic clk_dac, output logic [DAC_DATA_WIDTH-1:0] dac_data, output logic dac_wrt, // ADC output logic clk_adc, input wire [ADC_DATA_WIDTH-1:0] adc_data, input wire adc_otr ); // // ------------------------------------------------------------------------- // // IDELAYCTRL // // ------------------------------------------------------------------------- // (* IODELAY_GROUP = "rgmii_idelay_group" *) // IDELAYCTRL IDELAYCTRL_inst ( // .RDY (), // .REFCLK (sys_clk), // .RST (1'b0) // ); TODO remove // ------------------------------------------------------------------------- // Generated clocks for controller // Need to create this IP in Vivado: // input resetn // input clk_200 : 200 MHz : Reference clock // output clk_adc_65 : 65 MHz : ADC RTL clock // output clk_adc_65_180 : 65 MHz, phase 180 deg. : ADC PHY clock // output clk_adc_125 : 125 MHz : DAC RTL clock // output clk_adc_125_180 : 125 MHz, phase 180 deg. : DAC PHY clock // output locked // ------------------------------------------------------------------------- wire clk_sampler, clk_adc; wire clk_generator, clk_dac; wire clk_locked; clk_wiz_ctrl_inst_clk_wiz inst ( // Clock in ports .clk_200(clk_in) // Clock out ports .clk_adc_65(clk_adc), .clk_adc_65_180(clk_sampler), .clk_dac_125(clk_dac), .clk_dac_125_180(clk_generator), // Status and control signals .resetn(rst_n), .locked(clk_locked), ); // ------------------------------------------------------------------------- // Controller reset // Use both external reset and clk_wiz lock // ------------------------------------------------------------------------- wire ctrl_rst_n = rst_n & clk_wiz_locked; logic finish; // Controller outputs to debug wire [31:0] dac_pulse_width; wire [31:0] dac_pulse_period; wire [DAC_DATA_WIDTH-1:0] dac_pulse_height; wire [15:0] dac_pulse_num; wire [31:0] adc_pulse_period; wire [15:0] adc_pulse_num; wire dac_start; wire adc_start; wire dac_rst; wire adc_rst; // ------------------------------------------------------------------------- // Controller TODO // ------------------------------------------------------------------------- control #( .DAC_DATA_WIDTH(DAC_DATA_WIDTH) ) udp_ctrl_inst ( .eth_clk_in (gmii_rx_clk), .dac_clk_in (dac_clk), .adc_clk_in (adc_clk), .rst_n (ctrl_rst_n), .s_axis_tdata (m_axis_rx_tdata), .s_axis_tvalid (m_axis_rx_tvalid), .s_axis_tready (m_axis_rx_tready), .s_axis_tlast (m_axis_rx_tlast), .finish (finish), .dac_pulse_width (dac_pulse_width), .dac_pulse_period (dac_pulse_period), .dac_pulse_height (dac_pulse_height), .dac_pulse_num (dac_pulse_num), .adc_pulse_period (adc_pulse_period), .adc_pulse_num (adc_pulse_num), .dac_start (dac_start), .adc_start (adc_start), .dac_rst (dac_rst), .adc_rst (adc_rst) ); //------------------------------------------------------------ // DAC -> ADC CDC TODO //------------------------------------------------------------ logic sample_req; logic sample_req_sync1; logic sample_req_sync2; logic sample_req_sync3; logic sample_done; logic sample_done_sync1; logic sample_done_sync2; logic sample_done_sync3; always_ff @(posedge adc_clk or posedge adc_rst) begin if (adc_rst) begin sample_req <= 1'b0; sample_req_sync2 <= 1'b0; sample_req_sync3 <= 1'b0; end else begin sample_req_sync2 <= sample_req_sync1; sample_req_sync3 <= sample_req_sync2; sample_req <= sample_req_sync3; end end //------------------------------------------------------------ // ADC -> DAC CDC TODO //------------------------------------------------------------ always_ff @(posedge dac_clk or posedge dac_rst) begin if (dac_rst) begin sample_done <= 1'b0; sample_done_sync2 <= 1'b0; sample_done_sync3 <= 1'b0; end else begin sample_done_sync2 <= sample_done_sync1; sample_done_sync3 <= sample_done_sync2; sample_done <= sample_done_sync3; end end //------------------------------------------------------------ // Generator (DAC) TODO //------------------------------------------------------------ generator #( .DATA_WIDTH(DAC_DATA_WIDTH), .ZERO_LEVEL(ZERO_LEVEL) ) generator_inst ( .clk_in(dac_clk), .rst(dac_rst), .start(dac_start), .pulse_width(dac_pulse_width), .pulse_period(dac_pulse_period), .pulse_height(dac_pulse_height), .pulse_num(dac_pulse_num), .pulse(p2_wrt), .pulse_height_out(p2_data), .sample_done(sample_done), .sample_req(sample_req_sync1) ); // ------------------------------------------------------------------------- // Sampler (ADC) TODO // ------------------------------------------------------------------------- sampler #( .DATA_WIDTH(ADC_DATA_WIDTH), .PACK_FACTOR(PACK_FACTOR), .PROCESS_MODE(PROCESS_MODE) ) sampler_dut ( .clk_in(clk_sampler), .rst(adc_rst), .data_in(ch2_data), .out_of_range(ch2_otr), .m_axis_tdata(accum_m_axis_tdata), .m_axis_tvalid(acum_m_axis_tvalid), .smp_num(adc_pulse_period), .sample_req(sample_req), .sample_done(sample_done_sync1) ); // ------------------------------------------------------------------------- // Accumulator TODO // ------------------------------------------------------------------------- accumulator_top #( .DATA_WIDTH(ADC_DATA_WIDTH), .ACCUM_WIDTH(ACCUM_WIDTH), .N_MAX(N_MAX), .WINDOW_SIZE(WINDOW_SIZE), .PACKET_SIZE(PACKET_SIZE) ) accumulator_top_dut ( .clk_in(clk_sampler), .rst(adc_rst), .s_axis_tdata(accum_m_axis_tdata), .s_axis_tvalid(acum_m_axis_tvalid), .start(adc_start), .smp_num(adc_pulse_period), .seq_num(adc_pulse_num), .eth_clk_in(gmii_tx_clk), .req_ready(req_ready), .send_req(send_req), .m_axis_tdata(s_axis_tx_tdata), .m_axis_tvalid(s_axis_tx_tvalid), .m_axis_tready(s_axis_tx_tready), .m_axis_tlast(s_axis_tx_tlast), .finish(finish) ); // ------------------------------------------------------------------------- // LED status TODO // ------------------------------------------------------------------------- assign led[0] = clk_locked; assign led[1] = rst_n; // assign led[2] = ; // assign led[3] = ; endmodule