132 lines
4.0 KiB
Systemverilog
132 lines
4.0 KiB
Systemverilog
import dma_reg_pkg::*;
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module wrapper_controller_dma
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#(
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parameter int unsigned ADDR_W = 16,
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parameter int unsigned DATA_W = 32,
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parameter int unsigned USER_W = 1,
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parameter int unsigned DAC_DATA_WIDTH = 12,
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parameter int unsigned AXI_DATA_WIDTH = 32,
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parameter int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8,
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parameter int unsigned AXI_ID_WIDTH = 8,
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parameter int unsigned AXI_USER_WIDTH = 1,
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parameter int unsigned AXI_MAX_BURST_LEN = 16,
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parameter int unsigned AXIS_DATA_WIDTH = AXI_DATA_WIDTH,
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parameter int unsigned AXIS_KEEP_ENABLE = AXIS_DATA_WIDTH > 8,
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parameter int unsigned AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH / 8,
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parameter int unsigned AXIS_LAST_ENABLE = 1,
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parameter int unsigned AXIS_ID_ENABLE = 1,
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parameter int unsigned AXIS_DEST_ENABLE = 0,
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parameter int unsigned AXIS_USER_ENABLE = 1,
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parameter int unsigned ENABLE_SG = 0,
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parameter int unsigned ENABLE_UNALIGNED = 0
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)
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(
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input logic ctrl_clk,
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input logic dac_clk_in,
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input logic adc_clk_in,
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input logic rst_n,
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axi4l_if.slave s_axil,
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// adc_clk_in domain
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input logic finish,
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output logic [31:0] adc_window_size,
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// dac_clk_in domain outputs
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output logic [31:0] dac_pulse_width,
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output logic [31:0] dac_pulse_period,
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output logic [DAC_DATA_WIDTH-1:0] dac_pulse_height,
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output logic [15:0] dac_pulse_num,
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// adc_clk_in domain outputs
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output logic [31:0] adc_pulse_period,
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output logic [15:0] adc_pulse_num,
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// pulse outputs
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output logic dac_start,
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output logic adc_start,
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output logic dac_rst,
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output logic adc_rst,
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axis_if.slave s_axis_read_data,
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axis_if.master m_axis_write_data,
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axi4_if.slave s_axi
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);
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axis_if.slave s_axis_status_read;
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axis_if.slave s_axis_status_write;
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axis_if.master m_axis_desc_read;
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axis_if.master m_axis_desc_write;
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controller_wrapper_axil
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#(
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.ADDR_W(ADDR_W),
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.DATA_W(DATA_W),
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.USER_W(USER_W),
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.DAC_DATA_WIDTH(DAC_DATA_WIDTH)
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)
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controller_wrapper_axil_inst
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(
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.ctrl_clk(ctrl_clk),
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.dac_clk_in(dac_clk_in),
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.adc_clk_in(adc_clk_in),
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.rst_n(rst_n),
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.s_axil(s_axil),
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.finish(finish),
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.adc_window_size(adc_window_size),
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.dac_pulse_width(dac_pulse_width),
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.dac_pulse_period(dac_pulse_period),
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.dac_pulse_height(dac_pulse_height),
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.dac_pulse_num(dac_pulse_num),
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.adc_pulse_period(adc_pulse_period),
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.adc_pulse_num(adc_pulse_num),
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.dac_start(dac_start),
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.adc_start(adc_start),
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.dac_rst(dac_rst),
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.adc_rst(adc_rst),
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.s_axis_status_read(s_axis_status_read),
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.s_axis_status_write(s_axis_status_write),
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.m_axis_desc_read(m_axis_desc_read),
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.m_axis_desc_write(m_axis_desc_write)
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);
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axi_dma_wrapper
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#(
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.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
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.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
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.AXI_ID_WIDTH(AXI_ID_WIDTH),
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.AXI_USER_WIDTH(AXI_USER_WIDTH),
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.AXI_MAX_BURST_LEN(AXI_MAX_BURST_LEN),
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.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
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.AXIS_KEEP_ENABLE(AXIS_KEEP_ENABLE),
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.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
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.AXIS_LAST_ENABLE(AXIS_LAST_ENABLE),
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.AXIS_ID_ENABLE(AXIS_ID_ENABLE),
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.AXIS_DEST_ENABLE(AXIS_DEST_ENABLE),
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.AXIS_USER_ENABLE(AXIS_USER_ENABLE),
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.ENABLE_SG(ENABLE_SG),
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.ENABLE_UNALIGNED(ENABLE_UNALIGNED)
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)
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axi_dma_wrapper_inst
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(
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.clk(ctrl_clk),
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.rst(!rst_n),
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.s_axis_read_desc(m_axis_desc_read),
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.m_axis_read_desc_status(s_axis_status_read),
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.m_axis_read_data(s_axis_read_data),
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.s_axis_write_desc(m_axis_desc_write),
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.m_axis_write_desc_status(s_axis_status_write),
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.s_axis_write_data(m_axis_write_data),
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.m_axi(s_axi)
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);
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endmodule |