import dma_reg_pkg::*;

module wrapper_controller_dma 
#(
    parameter int unsigned ADDR_W             = 16,
    parameter int unsigned DATA_W             = 32,
    parameter int unsigned USER_W             = 1,

    parameter int unsigned DAC_DATA_WIDTH     = 12,

    parameter int unsigned AXI_DATA_WIDTH     = 32,

    parameter int unsigned AXI_STRB_WIDTH     = AXI_DATA_WIDTH / 8,
    parameter int unsigned AXI_ID_WIDTH       = 8,
    parameter int unsigned AXI_USER_WIDTH     = 1,
    parameter int unsigned AXI_MAX_BURST_LEN  = 16,

    parameter int unsigned AXIS_DATA_WIDTH    = AXI_DATA_WIDTH,
    parameter int unsigned AXIS_KEEP_ENABLE   = AXIS_DATA_WIDTH > 8,
    parameter int unsigned AXIS_KEEP_WIDTH    = AXIS_DATA_WIDTH / 8,
    parameter int unsigned AXIS_LAST_ENABLE   = 1,
    parameter int unsigned AXIS_ID_ENABLE     = 1,
    parameter int unsigned AXIS_DEST_ENABLE   = 0,
    parameter int unsigned AXIS_USER_ENABLE   = 1,

    parameter int unsigned ENABLE_SG          = 0,
    parameter int unsigned ENABLE_UNALIGNED   = 0
)
(
    input  logic                       ctrl_clk,
    input  logic                       dac_clk_in,
    input  logic                       adc_clk_in,
    input  logic                       rst_n,
    axi4l_if.slave                     s_axil,

    // adc_clk_in domain
    input  logic                       finish,
    output logic [31:0]                adc_window_size,

    // dac_clk_in domain outputs
    output logic [31:0]                dac_pulse_width,
    output logic [31:0]                dac_pulse_period,
    output logic [DAC_DATA_WIDTH-1:0]  dac_pulse_height,
    output logic [15:0]                dac_pulse_num,

    // adc_clk_in domain outputs
    output logic [31:0]                adc_pulse_period,
    output logic [15:0]                adc_pulse_num,

    // pulse outputs
    output logic                       dac_start,
    output logic                       adc_start,
    output logic                       dac_rst,
    output logic                       adc_rst,

    axis_if.slave    s_axis_read_data,
    axis_if.master   m_axis_write_data,

    axi4_if.slave    s_axi
);

axis_if.slave s_axis_status_read;
axis_if.slave s_axis_status_write;

axis_if.master m_axis_desc_read;
axis_if.master m_axis_desc_write;

controller_wrapper_axil
#(
    .ADDR_W(ADDR_W),
    .DATA_W(DATA_W),
    .USER_W(USER_W),
    .DAC_DATA_WIDTH(DAC_DATA_WIDTH)
)
controller_wrapper_axil_inst
(
    .ctrl_clk(ctrl_clk),
    .dac_clk_in(dac_clk_in),
    .adc_clk_in(adc_clk_in),
    .rst_n(rst_n),

    .s_axil(s_axil),

    .finish(finish),
    .adc_window_size(adc_window_size),
    .dac_pulse_width(dac_pulse_width),
    .dac_pulse_period(dac_pulse_period),
    .dac_pulse_height(dac_pulse_height),
    .dac_pulse_num(dac_pulse_num),
    .adc_pulse_period(adc_pulse_period),
    .adc_pulse_num(adc_pulse_num),
    .dac_start(dac_start),
    .adc_start(adc_start),
    .dac_rst(dac_rst),
    .adc_rst(adc_rst),

    .s_axis_status_read(s_axis_status_read),
    .s_axis_status_write(s_axis_status_write),
    .m_axis_desc_read(m_axis_desc_read),
    .m_axis_desc_write(m_axis_desc_write)
);

axi_dma_wrapper
#(
    .AXI_DATA_WIDTH(AXI_DATA_WIDTH),
    .AXI_STRB_WIDTH(AXI_STRB_WIDTH),
    .AXI_ID_WIDTH(AXI_ID_WIDTH),
    .AXI_USER_WIDTH(AXI_USER_WIDTH),
    .AXI_MAX_BURST_LEN(AXI_MAX_BURST_LEN),
    .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
    .AXIS_KEEP_ENABLE(AXIS_KEEP_ENABLE),
    .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
    .AXIS_LAST_ENABLE(AXIS_LAST_ENABLE),
    .AXIS_ID_ENABLE(AXIS_ID_ENABLE),
    .AXIS_DEST_ENABLE(AXIS_DEST_ENABLE),
    .AXIS_USER_ENABLE(AXIS_USER_ENABLE),
    .ENABLE_SG(ENABLE_SG),
    .ENABLE_UNALIGNED(ENABLE_UNALIGNED)
)
axi_dma_wrapper_inst
(
    .clk(ctrl_clk),
    .rst(!rst_n),
    .s_axis_read_desc(m_axis_desc_read),
    .m_axis_read_desc_status(s_axis_status_read),
    .m_axis_read_data(s_axis_read_data),
    .s_axis_write_desc(m_axis_desc_write),
    .m_axis_write_desc_status(s_axis_status_write),
    .s_axis_write_data(m_axis_write_data),
    .m_axi(s_axi)
);
endmodule